Preface
Digital Design Using VHDL and PLDs p. 1
VHDL/PLD Design Methodology p. 1
Requirements Analysis and Specification p. 5
VHDL Design Description p. 6
Verification Using Simulation p. 11
Testbenches p. 13
Functional (Behavioral) Simulation p. 16
Programmable Logic Devices (PLDs) p. 18
SPLDs and the 22V10 p. 21
Logic Synthesis for the Target PLD p. 27
Place-and-Route and Timing Simulation p. 31
Programming and Verifying a Target PLD p. 37
VHDL/PLD Design Methodology Advantages p. 38
VHDL's Development p. 39
VHDL for Synthesis versus VHDL for Simulation p. 39
This Book's Primary Objective p. 40
Entities, Architectures, and Coding Styles p. 44
Design Units, Library Units, and Design Entities p. 44
Entity Declaration p. 45
VHDL Syntax Definitions p. 47
Port Modes p. 50
Architecture Body p. 53
Coding Styles p. 55
Synthesis Results versus Coding Style p. 66
Levels of Abstraction and Synthesis p. 69
Design Hierarchy and Structural Style p. 71
Signals and Data Types p. 82
Object Classes and Object Types p. 82
Signal Objects p. 84
Scalar Types p. 88
Type Std_Logic p. 93
Scalar Literals and Scalar Constants p. 99
Composite Types p. 100
Arrays p. 101
Types Unsigned and Signed p. 107
Composite Literals and Composite Constants p. 110
Integer Types p. 112
Port Types for Synthesis p. 116
Operators and Expressions p. 118
Logical Operators p. 123
Signal Assignments in Dataflow Style Architectures p. 127
Selected Signal Assignment p. 130
Type Boolean and the Relational Operators p. 132
Conditional Signal Assignment p. 134
Priority Encoders p. 139
Don't Care Inputs and Outputs p. 140
Decoders p. 144
Table Lookup p. 147
Three-state Buffers p. 151
Avoiding Combinational Loops p. 155
Behavi oral Style Combinational Design p. 165
Behavioral Style Architecture p. 165
Process Statement p. 169 Sequential Statements p. 170 Case Statement p. 171 If Statement p. 176 Loop Statement p. 181 Variables p. 185
Parity Detector Example p. 188
Synthesis of Processes Describing Combinational Systems p. 193
Event-Driven Simulation p. 201
Simulator Approaches p. 201
Elaboration p. 203
Signal Drivers p. 208
Simulator Kernel Process p. 210
Simulation Initialization p. 212
Simulation Cycles p. 215
Signals versus Variables p. 223
Delta Delays p. 230
Delta Delays and Combinational Feedback p. 235
Multiple Drivers p. 239
Signal Attributes p. 241
Testbenche s for Combinational Designs p. 251
Design Verification p. 251
Functional Verification of Combinational Designs p. 255
A Simple Testbench p. 255
Physical Types p. 258
Single Process Testbench p. 260
Wait Statements p. 263
Records and Table Lookup Testbenches p. 268 Testbenches That Compute Stimulus and Expected Results p. 272
Predefined Shift Operators p. 274
Stimulus Order Based on UUT Functionality p. 276
Comparing a UUT to a Behavioral Intent Model p. 279
Code Coverage and Branch Coverage p. 281
Post-Synthesis and Timing Verifications for Combinational Designs p. 284
Timing Models Using VITAL and SDF p. 288
Latches and Flip - flops p. 304
Sequential Systems and Their Memory Elements p. 304
D Latch p. 308
Detecting Clock Edges p. 315
D Flip-flops p. 317
Enabled (Gated) Flip-flop p. 324
Other Flip-flop Types p. 328
PLD Primitive Memory Elements p. 331
Timing Requirements and Synchronous Input Data p. 332
MultibitLatches, Registers, Counters, and Memory p. 337
Multibit Latches and Registers p. 337
Shift Registers p. 340
Shift Register Counters p. 346
Counters p. 348
Detecting Non-clock Signal Edges p. 360
Microprocessor Compatible Pulse Width Modulated Signal Generator p. 366
Memories p. 370
Finite State Machines p. 380
Finite State Machines p. 380
FSM State Diagrams p. 386
Three Process FSM VHDL Template p. 388
State Diagram Development p. 392
Decoder for an Optical Shaft Encoder p. 403
State Encoding and State Assignment p. 409
Supposedly Safe FSMs p. 414
Inhibit Logic FSM Example p. 418
Counters as Moore FSMs p. 422
ASM Charts and RTL Design p. 431
Algorithmic State Machine Charts p. 431
Converting ASM Charts to VHDL p. 43
System Architecture p. 441
Successive Approximation Register Design Example p. 445
Subprograms p. 469
Subprograms p. 469
Functions p. 473
Procedures p. 480
Array Attributes and Unconstrained Arrays p. 484
Overloading Subprograms and Operators p. 491
Type Conversions p. 494
Packages p. 501
Packages and Package Bodies p. 501
Standard and De Facto Standard Packages p. 505
Package STD_LOGIC_1164 p. 510
Package NUMERIC_STD (IEEE Std 1076.3) p. 516
Package STD_LOGIC_ARITH p. 523
Packages for VHDL Text Output p. 524
Testbenches for Sequential Systems p. 526
Simple Sequential Testbenches p. 526
Generating a System Clock p. 527
Generating the System Reset p. 531
Synchronizing Stimulus Generation and Monitoring p. 532
Testbench for Successive Approximation Register p. 538
Determining a Testbench Stimulus for a Sequential System p. 542
Using Procedures for Stimulus Generation p. 545
Output Verification in Stimulus Procedures p. 550
Bus Functional Models p. 552
Response Monitors p. 560
Modular Design and Hierarchy p. 566
Modular Design, Partitioning, and Hierarchy p. 566
Design Units and Library Units p. 571
Design Libraries p. 573
Using Library Units p. 574
Direct Design Entity Instantiation p. 577
Components and Indirect Design Entity Instantiation p. 580
Configuration Declarations p. 587
Component Connections p. 594
Parameterized Design Entities p. 598
Library of Parameterized Modules (LPM) p. 602
Generate Statement p. 605
More Design Examples p. 615
Microprocessor Compatible Quadrature Decoder/Counter Design p. 615
Verification of Quadrature Decoder/Counter p. 624
Electronic Safe Design p. 630
Verification of Electronic Safe p. 644
Encoder for RF Transmitter Design p. 649
Appendix VHDL Attributes p. 659
Bibliography p. 663
Index
