Chapter 8. Sequential Circuits for Registers and Counters

(1)

Chapter 8

Sequential Circuits for

Registers and Counters

(2)

Lesson 3

COUNTERS

(3)

•

• Counters

Counters

•

• T

T

-

FF

—

Basic Counting element

•

• State Diagram of

State Diagram of

-

ve Pulse

triggered 16

-

state counter

•

• Ripple Counter

Ripple Counter

(4)

Counting

• Often there is a need to count the

number of pulses or triggering at an

input.

• Counting is an essential circuit in

computers.

(5)

Various Features in counters

• Delays at FFs — Synchronous and Ripple

• Output bits at FFs — 4, 8 or 16 bit

• FFs used — D-FF, JK, RS

• Family — TTL, LSTTL, CMOS, HCMOS

• Outputs — Synchronous, Asynchronous

(6)

Modulo-6 Counter

• If a counter returns to original state after Q

_B

= ‘1’, Q

_C

= ‘0’ and Q

_D

= ‘1’, and Q

_A

is

always = ‘0’we say it is modulo-6 counter

• Counter returns to original state of Qs after

(7)

State Diagram of Modulo 7

S

₀

1 S

₁

1 S

₃

1 S

₅

S

₄

1

(8)

Modulo-7 Counter

• If a counter returns to original state after Q

_B

= ‘1’, Q

_C

= ‘1’ and Q

_D

= ‘0’, and Q

_A

is

always = ‘0’, we say it is modulo-7 counter

• Counter returns to original state of Qs after

(9)

State Diagram of Modulo 7

S

₀

1 S

₁

1 S

₃

1 S

₆

(10)

Modulo-10 Counter

• If a counter returns to original state after Q

_A

= ‘1’, Q

_B

= ‘0’ Q

_C

= ‘0’ and Q

_D

= ‘1’, we

say it is modulo-10 counter

• Counter returns to original state of Qs after

10 counts

(11)

State Diagram of Modulo 10

S

₀

1 S

₁

1 S

₃

1 S

₇

S

₉

(12)

Various types of counters

• Ripple Counter— 4, 8 or 16 bit

• Binary Counter — 4, 8 or 16 bit

• Ring Counter — 4, 8 or 16 bit

• Decade Counter - Modulo 10

(13)

•

• Counters

Counters

•

• T

T

-

FF

—

Basic Counting element

•

• State Diagram of

State Diagram of

-

ve Pulse

triggered 16

-

state counter

•

• Ripple Counter

Ripple Counter

(14)

Divide by 2 as Counting Element

• A divide-by-2 circuit produces one

output pulse for every two pulses

applied to its input.

• A divide-by-two circuit is made from a

T-FF

(15)

T and JK FFs for Counting

• 1. Use a circuit of T-type flip-flop

• 2. Use a single JK flip-flop with its J and K

inputs made ‘1’. The T-flip-flop (FF) is

designed from JK or any other method to

act as a divide-by-two circuit and JK input

is now the T-input.

(16)

TD and SR FFs for Counting

• 3.Use a D flip-flop (not D-latch) with its



Q

output feedback to the D input

• 4. Alternatively Use a S-R flip-flop with a

NOT in-between S and R to get a D-FF and

then convert a D-FF into T

(17)

T-FF

• D input = T XOR Q

_n

and Q

_n+1

= Q

_n

• JK FF functions as T-FF if J = 1 and K

(18)

T- from D- Flip-Flop + ve edge

triggered

• Output Q

and



Q



Q

D

Q

D

Divide

by 2

T

+ve Edge

triggered

circuit

↑

(19)

T from JK Flip-Flop – ve edge

triggered

• Output Q

and



Q



Q

K=1

J = 1



Q

1 Divide

by 2FF

Clock

T

-ve Edge

triggered

circuit

↓

R

S

Preset

clear

(20)

• Counters

• T-FF — Basic Counting element

•

• State Diagram of

State Diagram of

-

ve Pulse

triggered 16

-

state counter

(21)

State Diagram

S

₁₅

1 S

₀

1 S

₃

1 S

₇

S

₁₁

(22)

• Counters

• T-FF Basic Counting element

• State Diagram of -ve Pulse

triggered 16-state counter

(23)

Cascading T-FFs

• T FF acts as a divide-by-2 circuit, if Q

output of the FF connects to the T input of

the second FF, and the Q output from the

second FF connects to T-input of the third

flip-flop and so on, the FFs are said to be in

a cascade

(24)

4-bit Ripple Counter (Binary

Asynchronous Counter)

Divide

by 2FF

Q

Divide

by 2FF

Q

Divide

by 2FF

Divide

by 2FF

Asynchronous Counter as each flip flop has

Q

CLR

Count

input A

After t

p

After 4

×

t

p

(25)

Additional feature in ripple counter in IC

7493 to enable its conversion to modulo-6

counter

R

(1)

R

(26)

-ve edge triggered T- FF

CLR = 1, J = K = 1

Inputs

CLR = 1, J = K = 1

Outputs

CLK Count= Q

_n+1(A)

Q

_n+1(B)

Q

_n+1(C)

Q

_n+1(D)

Q

_n+1

means next state after n

th

clock input and

↓

1

0

1 ↓

2

0

1

0

(27)

-ve edge triggered T- FF

CLR = 1, J = K = 1

Inputs

CLR = 1, J = K = 1

Outputs

CLK Count = Q

_n+1(A)

Q

_n+1(B)

Q

_n+1(C)

Q

_n+1(D)

Q

_n+1

means next state after n

th

clock input and

×

↓

4

0

1

0

0 ↓

5

0

1

0

1 ↓

6

0

1

0

(28)

Timing Diagram when -ve edge asynchronous

counter QD delays transition by 4 tp from clock

edge

CLK

(shift)

Q

_A

Q

_B

Q

(29)

(30)

Counters

• T-FF functions as counter, because it

toggles at every negative edge

• T-FF is made from J-K, D-FF when D

=



Q and from RS-FF, when S =



R

and S connects



Q

(31)

Counters

• Counting delay = n times t

_p

for a n-bit

ripple counter

• 16-bit can be converted to modulo-6, 7

and 10 counters by resetting the

counter at next transition when Qs

show count = 5, 6 and 9

(32)

End of Lesson 3

COUNTERS

(33)

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