Solving Network Challenges

Solving Network Challenges

In Advanced

Multicore SoCs

Multicore SoC Network Challenges

• Many heterogeneous cores: various protocols, data

width, address maps, bandwidth, clocking, etc.

• Typically

very high bandwidth

between cores or

to/from main memory

• SoC

floor plan

may be driven by board requirements

• Physical design is

challenging

for large chips

• Need to

maximize performance

while minimizing area

and power consumption

I I I I T T T T I I T T T I I I I I I I I T I I T T I T T I I I I I T T T I R R R R R R R R R R I I T T T I I T

Intelligent agents allow each core to use different protocols,

data widths, address map, clock frequencies, etc.

C S S C C S S C C C S S C C C M M M C C C S M C C C C C

Hypothetical Multicore Network

May want to divide large chips into several different “domains”

(power, clock, voltage, etc)

Some links may be wider

than others

Want network to safely and automatically handle

Network Must Be Scalable

• Want to connect several (maybe dozens or hundreds) of cores to

the network

– Each core may be unique

• “Costs” of network must be

linear

with number of cores even

though communication possibilities increase

quadratically

– Exponential area increase, power increase, latency, etc are all

unacceptable

• Need good support for “unbalanced” networks too

– Initiators ≅ Targets, Initiators 〉〉 Targets, Initiators 〈〈 Targets

• Desire

flexibility

in network topology

Input port unit Input port

unit

Router Design is

Important for Scalability

• Per-port/per-VC buffer sizing

• Full throughput switch

• Wormhole routing

• Credit based flow

control

Credit tracking Input port unit VC Storage Switch

MxN

Router

Flexible Topology Examples

Mem

Ctrl CPUs

A Realistic Multicore Network

Must Be Deadlock Free

• Any possibility of

deadlock

must be eliminated before the

device is manufactured

• Non-blocking flow control is important to avoid deadlock

– Virtual channels (or a similar method) can allow other traffic to bypass blocked traffic

• Without non-blocking flow control, any

loops

in the network

topology become hazardous

• Ideally, network

automatically generates

routes that are

guaranteed deadlock free

– Alternatively, at least a “check” is needed for deadlock possibility – Especially important for a non-uniform network

Performance Verification

• Typically the performance of a network depends on both

the configuration of the network (topology, etc) and the

nature of the traffic carried by that network

• Often “real” traffic is not available

– Need good tools to help develop realistic traffic examples

– Want multiple use cases, possibly with different parts of the SoC powered on/off or with modifications to clock frequencies

• Need to quickly assess performance

– Transaction level modeling can significantly improve speed while maintaining cycle accuracy

Monitoring and Trace

• Performance monitoring and hardware tracing provide

excellent visibility into what is happening

inside

the SoC

– Allows user to trace traffic, monitor bandwidth, etc

• By making the monitor/trace logic

efficient

, one may

choose to leave the function in the final SoC product

– However, security becomes a concern in such cases

– Must ensure this capability does not open a security hole

• Useful even when only included in prototypes

Other Important Considerations

• Cache coherence and I/O coherence

• Support for DRAM scheduling

– Improve DRAM performance by scheduling transactions to minimize page misses and turn-around penalties

• Security features

– Prevent selected cores from accessing private data or secure portions of SoC

– Especially important for devices that can load “apps” in field – Usually want a mix of R/W, Read-Only, and No-access

Sample Security Solution

• Multi-region firewall enforces access policies

– Per-target

– Re-programmable

– Layered architecture supports many domains with variable region sizes

• Target access control

– Per role (e.g. secure/not) – Per access type (RD/WR)

• Flexible security error caching and reporting

Comm Links Strea ming Media Mutually Secure Domains Comm. Links CPU & OS Media Stream

Summary

• The interconnect network plays an important role in

a Multicore SoC

– And presents many challenges

• Bandwidth, scalability, physical design, clocking issues, QoS, performance verification, deadlock avoidance, monitor/trace, power consumption, DRAM scheduling, coherence, security…

• Sonics products solve all of these challenges for you

– A total system approach

– 200+ successful tapeouts

– Over 2 Billion units shipped

– Visit our booth to learn more