ECE331 Lecture 1 9S12Cxx Assembly Language

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ECE331 Lecture 1

9S12Cxx Assembly Language

CSM12C128 Evaluation Module

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•

Our CSMB12C128 development module

(Designed by Axiom Manufacturing) has a

60-pin external interface.

•

Unfortunately, it does not plug directly into a

breadboard, so a breadboard adapter was

made for us by John LaBaio at RHIT Ventures.

•

Since only 60 pins are available, not all of the

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9S12C128 Pins available on

CSMB12C128

CSMB12C128

module. This is

the top view of

the module

pinout.

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A few of the I/O pins that are available:

• _{PA7:0 and PB7:0 – Each of the eight Port A or eight Port B pins may be}

configured as either a digital input or output. These two ports serve as multiplexed (time-shared) address and data pins when the

microcontroller is operated in expanded mode.

• _{PAD7:0 (AN7:0) – Each of the eight “Port AD” pins may be configured as}

either analog input or as digital input/output.

• _{PT7:0 – Each of the eight “Port T” pins may be configured as timer input}

capture, timer output compare, or digital input/output.

• _{PM5:0 – “Port M” pins PM5:3 may be configured as digital input or}

output, in addition, Port M can be used for the following special functions:

• _{PM5:2 => Serial Peripheral Interface (SPI) bus} • _{PM1:0 => CAN serial communication bus}

Do NOT use PM0 or PM1 for general digital I/O, since these two pins are

hardwired to the CAN interface chip on the CSMB12C128 module, and there are no on-board jumpers to break this connection.

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The Inside Story:

CSM12C128 Module

Circuit Diagram

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Connecting two I/O pins to a switch and an

LED on the Project Board

C S M 1 2 C 1 2 8 J 1 C o n n e c t o r

1 2 3 4 5 6 7 8 9 10 11 12

13 15 17 19 21 23 25 27 29

30 31 32 28 26 24 22 20 18 16 14

33 35 37 39 34 36 38 40

41 43 45 47 49 51 53 55 57 42 44 46 48 50 52 54 56 58

59 60 V x P E 1 /I R Q G N D R E S E T P S 1/ T X D M O D C /B K G D P S 0/ R X D P P 7/ K W P 7/ P W M 7/ S C K 2 P P 0/ K W P 0 P A D 07 /A N 07 P P 1/ K W P 1 P A D 06 /A N 06 P T 0 /P W 0/ IO C 0 P T 1 /P W 0/ IO C 1 P M 4 /M O S I P M 2 /M IS O P M 5 /S C K P M 3 /S S P A 7 P A 6 P A 5 P P 2/ K P P 2/ P W M 2 P A 4 P P 3 /K P P 3/ P W M 3 P J6 /K W J6 P J7 /K W J7 P A D 03 /A N 03 O A D 02 /A N 02 P A D 01 /A N 01 P A D 00 /A N 00 P A D 04 /A N 04 P A D 05 /A N 05 P A 3 P A 2 P A 1 P A 0 P P 4 /K P P 4/ P W M 4 P P 5/ K P P 5/ P W M 5 P S 2/ R X D 1 P S 3/ T X D 1 P B 7 P B 6 P B 5 P B 4 P B 3 P B 2 P B 1 P B 0 P M 1 /T X C A N 0 P E 0/ X IR Q P E 2/ R W P E 3/ LS T R B P E 4/ E C L K P T 2/ IO C 2 P T 3/ IO C 3 P T 4/ IO C 4 P T 5/ IO C 5 P T 6/ IO C 6 P M 0 /R X C A N 0 P T 7/ IO C 7 R 2

5 1 0 o h m s

V c c = + 5 V

D a t a L E D

S W 1

C S M B 1 2 C 1 2 8 b o a r d

R 3

1 0 k

D a t a S w i t c h R 1

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Wire NEATLY on left side of breadboard– Wires and component leads cut short, pressed down, do not cross over any part.

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9S12C128 Memory Map

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Status Register Flag Bits

•

Status Register (CCR) = S X H I N Z V C

•

S = “STOP Instruction Disable Flag”

– _{Out of RESET, this bit is set to 1.}

– _{Clearing this flag enables the STOP instruction.} – _{When a STOP instruction executes (if S = 0), the}

processor’s clock oscillator is shut down, and the processor enters a low-power consumption “Sleep Mode” until the processor is awakened by an

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• _{X-bit - Nonmaskable Interrupt Mask Bit}

– _{Out of RESET, X = 1.}

– _{Clearing X enables interrupts on the XIRQ* interrupt}

input line.

– _{Once cleared, the X bit CANNOT be reset by software to}

disable XIRQ interrupts. Thus the XIRQ input is said to be “non-maskable”.)

– _{The only way to set X = 1 is via RESET}_.

• _{I-bit - Maskable Interrupt Mask Bit}

– _{Out of RESET, I = 1.}

– _{Clearing I (via the CLI instruction) enables interrupts on}

the IRQ* interrupt input line.

– _{The I bit CAN be set back to 1 at any time by the software}

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Arithmetic Flags Z N C V H

• _Z…. Zero Flag

– _{Set if result = 0} • _N…. Negative Flag

– _{Indicates sign of result (1 => negative, 0 => pos)} – _{Follows MSB of result}

• _C…. Carry Flag

– _{Set if Carry occurs during addition operation}

– _{Set if Borrow occurs during subtract or compare operation} • _V…. Overflow Flag

– _{Set if two’s complement overflow occurs} • _H…. Half Carry Flag

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Signed (Two’s Complement) Overflow Detection

•

For Addition

–

If addend and augend are of unlike signs

=> no overflow possible (V=0).

–

If addend and augend are of like sign,

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•

For Subtraction

–

If subtrahend and subtractor are of like sign

=> no overflow possible (V = 0).

–

If subtrahend and subtractor are of unlike

signs, and the sign bit of the resulting

difference is NOT consistent with

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Flag Setting Examples

Example #1

• _{LDAA #$38}

ADDA #$A9

=> $38 + $A9 = $E1 (A contains $E1) H = 1 (carry out of lower 4 bit nybble).

C = 0 (no carry out of MSB of result) Z = 0 (result not 0)

N = 1 (result negative)

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Example #2

• LDAA #$9A

ADDA #$A9

=> $9A + $A9 = $43 (A contains $43) H = 1 (carry out of lower 4 bit nybble.

C = 1 (carry out of MSB of result) Z = 0 (result not 0)

N = 0 (result positive)

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Example #3

• LDAA #$FC

ADDA #$04

=> $FC + $04 = $00 (A contains $00) H = 1 (carry out of lower 4 bit nybble.

C = 1 (carry out of MSB of result) Z = 1 (result is 0)

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Example #4

• LDAA #$FC

SUBA #$04

=> $FC - $04 = $F8 (A contains $F8)

H = X (H is not affected by subtract or compare, X simply remains in the state it was in.) C = 0 (no borrow out of MSB was requested) Z = 0 (result is not 0)

N = 1 (result negative)

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Example #5

• _{LDAA #$70}

SUBA #$80

=> $70 - $80 = $F0 (A contains $F0)

H = X (H is not affected by subtract or compare, X simply remains in the state it was in.) C = 1 (Borrow out of MSB was requested)

Z = 0 (result is not 0) N = 1 (result negative)

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Example #6

• _{LDAA #$80}

CMPA #$70

=> $80 - $70 = $10 (But A contains $80 because CMPA does NOT alter A!)

H = ? (H is not affected by subtract or compare, H simply remains in the state it was in.) C = 0 (No borrow out of MSB was requested) Z = 0 (result is not 0)

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Example #7

• LDAA #$E2

CMPA #$E2

=> $E2 - $E2 = 0 (BUT A contains $E2)

H = ? (H is not affected by subtract or compare, H simply remains in the state it was in.) C = 0 (NO Borrow out of MSB was requested) Z = 1 (result is 0)

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Addressing Modes – Tell the processor where to find data.

1. Immediate Addressing

• _{Requires “#” prefix in front of the immediate operand}

• In this addressing mode the data itself is placed IMMEDIATELY after the instruction

OP CODE in program memory.

• Ex: Mem Instr Immed.

Addr OpCd Operand Assy Code (hex) (hex) (hex)

4000 86 40 LDAA #64 ;without preceding “$” ;a value defaults to decimal

• _{4002 86 64 LDAA #$64}

4004 CE 00 64 LDX #$64 ;X is 16-bit reg,

;so 2 bytes data needed LBL: EQU $1234 ;LBL equated to $1234

4007 CE 12 34 LDX #LBL

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16-bit integer data storage

• _{Each memory location in the HC(S)12 address space is one byte (8 bits)}

wide; only 8-bits of data can be stored in a memory location. Memory is said to be “byte-addressable”.

• _{Whenever a 16-bit integer must be encoded on a Freescale}

microcontroller, as in “LDX #$1234”, it is stored in two adjacent memory locations, with the HIGH byte at the LOWER addressed

memory location. This is called the “Big Endian” convention (the “big” end goes first!). Note: Intel microcontrollers use the “Little Endian” convention!

Hex Hex

Addr Contents ORG $4000 LDX #$1234

4000 CE ;LDX Immediate addr mode OP CODE

4001 12 ;High byte of 16-bit immed operand stored here 4002 34 ;Low byte of 16-bit immed operand stored here

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2. Direct (Extended) Addressing Modes

•

One (two) bytes placed after the OP CODE to

indicate the “effective memory address” from

or to which data are read or written.

•

One byte is needed to indicate an address

between $00 - $FF (Direct addressing)

•

Two bytes needed to indicate an address

between $0000 - $FFFF (Extended addressing)

•

These modes are indicated by the

absence

of

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Direct and Extended addressing modes are used to access RAM memory locations as well as I/O PORT registers

• _{Simple Parallel I/O via 8-pin Port T (PT7:0)}

– _{DDRT ($242) Data Direction Register for Port T}

• Writing a 1 to Bit #X in DDRT will make the corresponding I/O pin, PTX,

an output. (Note: X is an integer between 0 and 7)

• Writing a 0 to Bit #X in DDRT will make the corresponding I/O pin, PTX,

an input

• Ex: writing $F0 to DDRT makes PT7:4 outputs, PT3:0 inputs

– _{PTT ($240) Data I/O Register for Port T}

• _{Reading the PTT register will bring in data from the pins configured as}

inputs

• Writing the PTT register will send out data to the pins configured as

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PTAD (AN7:0) 8-bit Analog and Digital I/O

Port

• _{DDRAD ($272) Data Direction Reg (like DDRT)} • _{PTAD ($270) Data I/O Reg (like PTT)}

• _{ATDDIEN ($8D) Digital Input Enable Register}

– _{This extra register is needed because PTAD pins can also} be used as analog inputs to the A/D converter.

– _{If DDRADx = 0, then a “1” must be written into Bit #X of} ATDDIEN to make the corresponding line Anx (or PTADx) a digital input line as opposed to an analog A/D input line. – _{Thus, assuming that DDRAD = $00, writing $C0 into}

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Direct and Extended Addr Modes used to make AN6 output follow AN7 input

• _{Addr Mach. Code Assy Language}

ATDDIEN: EQU $8D ;Digital Input Enable Reg for PTAD

PTAD: EQU $270 ;PTAD Data I/O Register

DDRAD: EQU $272 ;PTAD Data Direction Reg. ORG $4000

4000 86 80 LDAA #$80

;The following line is Direct Addr Mode, since ; the address of ATDDIEN is < $FF.

4002 5A 8D STAA ATDDIEN ; Make AN7 A Digital Input

4004 86 40 LDAA #$40

;Following 2 lines use Extended Addr Mode, since ; the addresses of DDRAD and PTAD are > $FF.

4006 7A 02 72 STAA DDRAD ;Make AN7 an input, AN6 an Output

4009 B6 02 70 AGN: LDAA PTAD ;Read state of AN7 into Bit #7 of A

400C 44 LSRA ;Shift Bit #7 to Bit #6 of Accum A.

400D 7A 02 70 STAA PTAD ;Write state of AN7 out to AN6.

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Where did I get the Op Codes?

• _{Answer: From the CPU12 manual}

document: S12CPUV2.pdf (available for download from the class folder.)

• _{For example, study the CPU12 manual’s description}

of the LDAA, STAA, ASLA, and JMP instructions. Note that this description explains how each of the

arithmetic flags are affected, what the op codes are for each addressing mode, how many bytes are

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3. Inherent Addressing Mode

•

Some instructions do not need to refer to an

external memory location outside of the

CPU12 core.

•

The data they operate on is inherently known,

and is in a CPU register that is INSIDE the

processor core.

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Such instructions require only a 1 (or 2) byte

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Examples of Inherent Mode Instructions

• _{CLI – Clear I-bit in Status Register}

(Enable IRQ interrupts)

• _{DEX – Decrement X register}

• _{INCA – Increment (add 1 to) Accumulator A.} • _{RTS – Return from Subroutine}

• _{PSHA – Push Accumulator A on the Stack} • _{ABA – Add B to A, putting result in A}

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4. (PC) Relative Addressing Mode

• _{Used by branching (transfer of control) instructions}

• _{They indicate their target (transfer) address as an 8 or 16-bit} signed offset from the value of the program counter (PC) at the time the instruction is executed.

• _{Often, the target address of the branch is not far from the} branch instruction (within +127 or -128 bytes of the op code that follows the branch instruction), so a single byte (8-bit) PC-relative offset can often be used, which is more economical than using extended addressing which would require two bytes to indicate the target address.

• _{However, “long branch” instructions featuring a 16-bit (2-byte)} PC relative offset are also available for branching further than +127 or -128 bytes from the current value of the PC.

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Conditional Branch Instructions

•

Conditional Branch instructions of the form

“Bxx” (whose target address is indicated by a

signed 8-bit PC-relative offset) or “LBxx”

(whose target address is indicated by a signed

16-bit PC-relative offset) examine the state of

one or more flags to decide whether to

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•

The complete set of “Bxx” conditional branch

instructions is summarized in the following

table from the CPU12 manual.

•

Just put an “L” prefix in front of these

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Example of Conditional Branching – LED Follows switch

Addr Machine Code Assembly Code ORG $4000

DDRT: EQU $242 PTT: EQU $240

4000 18 0B 40 02 42 MOVB #$40,DDRT ;SW on PT5

;LED on PT6

4005 B6 02 40 LOOP_HR: LDAA PTT

4008 84 20 ANDA #$20 ;If SW high, A = $20 ;If SW low, A = $00 400A 27 07 BEQ SWDOWN

400C 18 0B 40 02 40 SWUP: MOVB #$40,PTT ;Turn ON LED

4011 20 F2 BRA LOOP_HR

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Square Wave Generating Example

(Calls subroutine

DELAY10MS to generate a square wave with

approximately 20 ms period on output pin PM1)

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5 5 ORG $4000 ;This program waits until switch on PM2 6 6 0000 0250 PTM: EQU $250 ;is closed, then it generates 20 ms

7 7 0000 0252 DDRM: EQU $252 ;Square wave on PM1 output. 8 8 0000 0254 PERM: EQU $254 ;PTM pull-up enable reg

9 9 ;See Fig 3.19 of S12C32PIMV1.pdf

10 10 a004000 CF3F 00 Entry: LDS #$1000 ;Init Stk Ptr --- The first byte pushed will 11 11 ;be stored at $0FFF (highest RAM locn) 12 12 a004003 7902 54 CLR PERM ;Disable PTM input pullups

13 13 a004006 180B 0202 MOVB #2, DDRM ;Make PM1 output, PM2 input. 00400A 52

14 14 a00400B B602 50 WT_SW_LOW: LDAA PTM ;A SW is connected to PM2

15 15 a00400E 8404 ANDA #4 ;If SW on PM2 high,A=4; if SW low,A=0 16 16 a004010 26F9 BNE WT_SW_LOW ;Loop here until SW is pressed.

17 17 a004012 180B 0202 NEW_CYCLE: MOVB #2, PTM ;Make PM1 high 004016 50

18 18 a004017 1640 23 JSR DELAY10MS ;Call Subroutine DELAY10MS to wait 10 ms ;JSR pushes PC (which currently holds ;addr of next instr) onto stack, then loads ;PC with entry addr of subr DELAY10MS. 19 19 a00401A 7902 50 CLR PTM ;Make PM1 Low

20 20 a00401D 1640 23 JSR DELAY10MS ;Wait 10 ms

21 21 a004020 0640 12 JMP NEW_CYCLE ;Repeat this forever. 22 22 a004023 34 DELAY10MS: PSHX ;Save X on stack 23 23 a004024 CEFF FF LDX #$FFFF

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Role of Stack Pointer Register “SP”

• _{SP “points to” (holds the address of) the last item}

pushed on the stack.

• _{Stack grows “down” (toward address 0).}

• _{If SP is initialized to address $1000 (via LDS #$1000),}

and then a byte is pushed on the stack (PSHA), SP will first be decremented by 1, and THEN the byte in A will be written to the address in SP = $0FFF. No data is written to $1000.

• _{If a byte is pulled from the stack (PULA), first the}

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•

SP must always point to memory locations

where RAM is available.

•

If a 16-bit address is pushed on the stack (JSR)

or a 16-bit register is pushed on the stack

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Stack Map – After LDS #$1000

Address Contents SP -> 1000

0FFF 0FFE

0FFD

0FFC 0FFB

0FFA

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Stack Map After JSR at $4017

Address Contents 1000

0FFF 1A ;PC low byte (Return Addr)

SP -> 0FFE 40 ;PC high byte (Return Addr) 0FFD

0FFC 0FFB

0FFA

Note: JSR pushes current value of the PC, which points to the OP CODE of the instruction that is just after the JSR. Then JSR loads the entry point of the

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After PSHX in DELAY10MS Subrtn

0FFF 1A ;PC low byte (Return Addr) 0FFE 40 ;PC high byte (Return Addr)

0FFD XL ;Low Byte in X

SP -> 0FFC XH ;High Byte in X 0FFB

0FFA

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Stack Map After PULX in Subroutine

0FFF 1A ;PC low byte (Return Addr)

SP -> 0FFE 40 ;PC high byte (Return Addr)

0FFD

0FFC

0FFB

0FFA

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After RTS

Address Contents

SP -> 1000

0FFF

0FFE

0FFD

0FFC

0FFB

0FFA

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Just after second JSR (at $401D)

0FFF 20 ;Low byte of PC (Return addr)

SP -> 0FFE 40 ;High Byte of PC (Return addr)

0FFD

0FFC

0FFB

0FFA

Current PC value (address of instruction just

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After PSHX in DELAY10MS Subrtn

0FFE 40 ;High Byte of PC (Return addr)

0FFD XL ;Low Byte of X

SP-> 0FFC XH ;High Byte of X 0FFB

0FFA

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After PULX in DELAY10MS subroutine

SP -> 0FFE 40 ;High Byte of PC (Return addr)

0FFD 0FFC 0FFB

0FFA

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After RTS

Address Contents SP -> 1000

0FFF 0FFE

0FFD 0FFC 0FFB

0FFA

NOTE: RTS unstacks $4020 into PC, the addr of next instruction beyond JSR (JMP New_Cycle). Execution returns from subroutine to this instr. Stack now

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Metrowerks True-Time Simulator Demonstration

• _{Select “Simulator” instead of “Monitor” before the}

green “Debug” arrow button is pressed.

• _{Hit RESET button to start program at entry point}

initialized into the Reset Vector, at ($FFFE,$FFFF)

• _{Right click in the “Memory” window and select}

“Address”. Set address to 1000, to display stack area in memory (grows DOWNWARD from 0F00)

• _{Single Step by clicking on “Single Step” button (or}

hitting <F11>)

• _{Watch CPU registers change as you single step.}

• _{Watch SP register change, and also watch data get}

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• _{You will NOT want to single step through the entire}

subroutine, since it has a LARGE wait loop, so set

break point near end of subroutine, say at the PULX. Do this by right clicking on PULX and selecting “Set Breakpoint”. A red arrow appears to the left of this instruction.

• _{Now hit the Green “Start/Continue” arrow button in}

order to run the simulator at speed until it comes out of the wait loop and hits the breakpoint.

• _{From this point, you may continue single-stepping}

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Monitoring an Output Port with the

“IOLED” Simulator Object

• _{Click on “Component – Open – IOLED”}

• _{Right Click to select “Setup”. Set PORT to 250 and}

DDR to 252 (hex addresses for PORT M).

• _{Remove breakpoint from PULX by right clicking on}

the PULX and selecting “Remove Breakpoint”

• _{Set breakpoint at each of the JSR DELAY10MS}

instructions in calling program.

• _{Hit Reset button and then hit Start/Continue button.}

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Debouncing Switches

•

Whenever ANY mechanical switch is operated

(either closed or opened), its contacts will

bounce (chatter) close – open – close – open -

close, etc. for several milliseconds before the

switch contacts finally remain stable in their

closed or opened state.

•

Sometimes this is a problem, other times it is

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Hardware Debouncing SPDT Switch

Q = 1 S\ R\ +5 V +5 V 10 kΩ 10 kΩ SPDT Push Button Switch

Note: Cross-Coupled NAND gates form an SR latch with active-low inputs

NO NC

Wiper

(SPDT => Single Pole, Double Throw)

As button is pressed, and wiper moves to “NO” position, the first bounce clears SR latch output (Q -> 0), then successive bounces at “NO” make no further change in Q! Later when button is released, first bounce on “NC” sets Q -> 1; further

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Hardware Debouncing SPST Switch

+5 V 10 kΩ 10 μF SPST Pushbutton Switch 74HC14 Schmitt Inverter with Vt+=3V, Vt-=2V Vout Vin

When SW pressed, first contact closure shorts capacitor, making Vin = 0, and thus Vout goes high. Then as SW

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Software Debouncing SPST Switch

Vout (To 9S12C128 Input Pin) “Bouncy” SPST Switch

When SW pressed, Vout will go low, but then it will

“chatter” for a few ms (high-low-high-low, etc.)

+5V

10kΩ

When SW released, Vout will go high, but then it will “chatter” For a few ms (low-high-low-high, etc.)

SW

In some software

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Example where software debouncing is needed: Reliably toggling (changing state of) LED

Make PM2 input, PM1 output (SW on PM2, LED on PM1)

PM1 = 0

PM2=0?

PM2=1?

PM1 = ~PM1

Wait until SW is pressed

Wait until SW is released

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Why does LED fail to toggle reliably?

•

Answer: Contact bounce!

•

Contact bouncer occurs on “make” or “break”

of the switch contacts.

•

The “software” solution?

•

Call a wait routine (that waits longer than the

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Make PM2 input, PM1 output (SW on PM2, LED on PM1)

PM1 = 0

PM2=0?

PM2=1?

PM1 = ~PM1

Wait until SW is pressed

Wait until SW is released

Toggle LED Turn LED off

Wait 50 ms

Wait for contact bouncing to die out

Wait for contact bouncing to die out.

No Yes

No

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PTM: EQU $250 ;Toggles LED reliably

DDRM: EQU $252 ;Each time SW is RELEASED! PERM: EQU $254

Entry: LDS #$3F00 ;Init Stk Ptr

CLR PERM ;Disable PTM input pullups MOVB #2,DDRM ;Make PM1 output, PM2 input.

CLR PTM ;Turn OFF LED, which is connected to PM1. WT_SW_LOW: LDAA PTM ;A SW is connected to PM2

ANDA #4 ;If SW on PM2 high,A=4; if SW low,A=0

BNE WT_SW_LOW ;Loop here until SW is pressed (SW goes low) JSR DELAY10MS ;Wait for contact bouncing to die out.

WT_SW_HIGH: LDAA PTM ANDA #4

BEQ WT_SW_HIGH ;Loop here until SW is released

JSR DELAY10MS ;Wait for contact bouncing to die out. LDAA PTM ;State of LED on Bit 1

EORA #2 ;Invert state of LED (Toggle LED) STAA PTM

BRA WT_SW_LOW

;************ End of main program********************* DELAY10MS: PSHX ;Save X on stack

LDX #$FFFF

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Indexed Addressing Modes

• _{So far we have discussed the following addressing}

modes:

– _{Immediate (LDAA #$12, LDX #$1234)} – _{Direct (LDAA $12, STAA $12)}

– _{Extended (LDAA $1234, STAA $1234)} – Inherent (INCA, RTS)

– _{PC Relative (BEQ NearTarg, LBEQ FarTarg)}

• _{Only the indexed addressing modes remain to be}

covered! (But there are EIGHT of them!)

• _{The indexed addressing modes use either the X, Y,}

SP, or PC 16-bit CPU registers as “index registers” along with additional information to form the

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•

Indexed addressing modes consist of an op

code followed by one postbyte plus 0, 1, or 2

extension bytes.

•

Postbyte and extension byte(s) indicate:

– _{Which index register is to be used (X, Y, SP, or PC)} – _{Whether a value in an accumulator is used as an}

offset

– _{Specify size of increment or decrement} – _{Specify use of 5-, 9-, or 16-bit offsets.}

•

Postbyte encoding found in Table 3.2 of

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1. 5-Bit Constant Offset Indexed Addressing

• _{5-bit signed constant offset (-16, +15) is contained in the}

postbyte itself.

• _{No extension bytes => 2-byte instruction}

• _{Effective Address of data=(Index Reg) + offset} • _{Value in the index register is not affected.}

• _{Examples (Assuming X = $4020):}

A6 00 LDAA 0,X ;($4020) -> A

;”($4020 )” means contents of $4020 6A 0C STAA 12,X ;A -> $402C;

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2. 9-bit constant offset index addressing

• _{Uses a 9-bit signed constant offset (-256, 255) that is}

added to the index register to form the effective address of the data.

• _{MSB of 9-bit constant offset in LSB of postbyte.}

• _{Rest of 9-bit constant offset is in ONE extension byte}

=> 3-byte instruction.

• _{Example (assume X = $4020):}

– _{A6 E0 80 LDAA $80,X ;($40A0) -> A}

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3. 16-bit constant offset indexing

•

Indexed addressing mode uses a 16-bit

constant offset (-32768,32767) that is added

to the index register to form the effective

address of the data.

•

Offset is placed in TWO extension bytes after

the postbyte => 4-byte instruction.

•

Examples (assume X = $4020)

E6 E2 10 00 LDAB $1000,X ;($5020) -> B

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Assembly Directive Examples

• _EQU_{– “}_Equate_{” used to define equivalence between a label and a value}

– MySymbol: EQU $1234

• _DC.B_{– “}_{Define Constant Byte}_{” (or its equivalent}_FCB_{– “}_{Form Constant}

Byte”) allocates a constant byte, or a list of bytes, or a string of ASCII

codes (into Flash ROM --- Not into RAM!)

– _{MyByte1: DC.B $12}

– _{MyByteTable: DC.B $12, 34, ‘Text’, $0A, $0D}

• _DC.W_{– “}_{Define Constant Word}_{” (or its equivalent}_FDB_{– “}_{Form Double}

Byte”) allocates a word (pair of bytes), or a list of words into Flash ROM

(NOT into RAM)

– _{MyWord1: DC.W $1234}

– _{MyWordTable: DC.W $1234, 10, 3000, $3BAD}

• DS.B N – “Define N-byte Space” (or its equivalent RMB N – “Reserve N Memory Bytes”) allocates N bytes of RAM.

(87)

Application of Constant Offset Indexing

;*** Example program that adds 10 bytes in the constant array "DatList" ORG RAMStart

; Use DS.B (or RMB) to allocate one word-sized (2-byte) data variable in RAM. result_wd ds.b 2 ;DS.B n "Define Space (n bytes)" allocates n bytes of RAM ;result_wd rmb 2 ;Note RMB n "Reserve Memory (n Bytes) is equivalent! ORG ROMStart

;Use DC.B (or FCB) to allocate a 10-byte data constant table in ROM

DatList: DC.B $12, $EF, $01, $F0, $85 ;DC.B => "Define Constant (byte-size)" FCB $01, $15, $78, $50, $00 ;FCB => "Form Constant Byte",

;FCB is equivalent to DC.B! Entry: ldx #DatList ;Index Reg X points to first byte in list

ldd #0 ;Reg D = A:B will accumulate 16-bit result . Init D=0. nxt_nr: addb 0,x ;Add next byte in list to low byte of Reg D (B)

bcc no_inc_a ;Decide whether to increment high byte of Reg D (A) inca

no_inc_a: inx ;Make X point to the next element in the list

cpx #DatList+10 ;Check to see if all 10 elements have been added. bne nxt_nr

(88)

4. 16-bit constant indirect addressing

• _{Adds 16-bit instruction-supplied offset to index register (X,} Y, SP, or PC) to form the address of a memory location that contains the high byte of the effective address. The next sequential memory location contains the low byte of the effective address.

• _{16-bit offset requires two extension bytes => 4-byte} instruction.

• _{Example: Assume X = $4020, ($4022)=$12, ($4023) = $34,} ($1234) = $45

– A6 E3 00 02 LDAA [2,X] ; $45 -> A

– 6A E3 00 02 STAA [2,X] ; A -> $1234

– _{05 E3 00 02 JMP [2,X] ;Jump to $1234}

– _{05 02 JMP 2,X ;Jump to $4022}

(89)

(90)

Application of 16-bit indirect index

addressing (“Menu Picking”)

org $4000 ;Desired program number

Jump_table: fdb prog0 ;is entered into two

fdb prog1 ;switches on PM1:PM0.

fdb prog2 ;This is a table of program

fdb prog3 ;starting addresses.

Entry: ……….

LDAB PTM ;read in program # to jump to

ANDB #$03 ;on switches on PM1:PM0.

LSLB ;Multiply program nr by 2 by shifting B left

TFR B,X ;Sign Extend(B) -> X

JMP [Jump_table,X] ;Jump to desired program prog0: ……

(91)

5. Auto incremented and

pre-decremented indexed addressing

• These modes automatically increment or decrement the index register by a specified constant (1,8) or (-1,-8) just BEFORE the data is accessed. Note the index register contents are MODIFIED by this addressing mode.

• _{This constant is encoded inside 4 -bits of the postbyte, so the} total instruction length is only 2 bytes.

• _{The index register can be specified as X, Y, or SP, but NOT the} PC, as it makes no sense to automatically modify the PC!

(92)

Examples of incremented and

pre-decremented indexed addressing

Org $4000

Datlist: DC.W $1234, $2345, $34, $45, $5678 400A CE 40 00 Entry: LDX #Datlist ;X = $4000

400D EC 21 LDD 2,+X ;$2345 -> D,X=$4002 400F EC 21 LDD 2,+X ;$0034 -> D, X=$4004 4011 EC 2E LDD 2,-X ;$2345 -> D, X=$4002

(93)

(94)

6. Auto incremented and

post-decremented indexed addressing

• These modes automatically increment or decrement the index register by a specified constant (1,8) or (-1,-8) just

AFTER the data is accessed. Note the index register contents are MODIFIED by this addressing mode.

• _{This constant is encoded inside 4 -bits of the postbyte, so the} total instruction length is only 2 bytes.

• _{The index register can be specified as X, Y, or SP, but NOT the} PC, as it makes no sense to automatically modify the PC!

(95)

Examples of incremented and

post-decremented indexed addressing

Org $4000

Datlist: DC.W $1234, $2345, $34, $45, $5678

400A CE 40 00 Entry: LDX #Datlist ;X = $4000

400D EC 31 LDD 2,X+ ;$1234 -> D, X=$4002 400F EC 31 LDD 2,X+ ;$2345 -> D, X=$4004 4011 EC 3E LDD 2,X- ;$0034 -> D, X=$4002 4013 EC 3E LDD 2,X- ;$2345 -> D, X=$4000

(96)

(97)

Ex #1: Stack Manipulation with

Auto-Indexed Addressing Modes

LDS #$0F00 ;Start of system stack area

STAA 1,-SP ;Same as PSHA, A->$0EFF, S=$0EFF

STX 2,-SP ;Same as PSHX, XH->$0EFD, XL->$0EFE, S=$0EFD LDX 2,SP+ ;Same as PULX, ($0EFD)->XH,($0EFE)->XL, S=$0EFF LDAA 1,SP+ ;Same as PULA, ($0EFF)->A, S = $0F00

;Or user may set up separate program stack area and use ;X or Y as the stack pointer!

LDY #$0E00 ;Start of user program stack area

(98)

Ex #2: Memory-to-Memory Array Moving

;Move a 10-word table from ROM into RAM ORG RAMStart

DatListRAM: DS.W 10 ;Here is 10-word RAM destination area ORG ROMStart

DatListROM: DC.W $1234, $EF, $0178, $0BAD, $FEED DC.W $01, $1567, $78, $50, $1023

Entry: LDX #DatListROM LDY #DatListRAM

LDAA #10 ;Let Acc A be loop counter NxtWd: MOVW 2,X+, 2,Y+ ;Move next word element

DECA

(99)

7. Accumulator Offset Indexed Addressing

• _{In this mode the effective address is the sum of the values in}

the index register and an 8-bit or 16-bit unsigned offset in one of the accumulators (A,B, or D)

• _{Since the identity of the accumulator used is encoded in the}

postbyte, this instruction is only 2 bytes in length.

• _{They permit a variable offset into an array to be modified in}

a loop, while the index register points to the start of the array.

• _Examples:

A6 E5 LDAA B,X 6D E6 STY D,X

(100)

Code Lookup Table Example

;This program translates the input byte read from Port T into a new coded byte and puts

;the coded value in CodedValue result location. $00 put in result location if code is not in table. ;Examples: Port T SW = $9A => DecodedValue = $0B

; Port T SW = $55 => DecodedValue = $00

ORG $0400 ;RAMSTART = $0400

CodedValue: DS.B 1 ;Coded Value put here, $00 if no code found ORG $4000 ;ROMSTART = $4000

CodeTable: DC.B $12,$34,$56,$78,$9A,$BC,$DE CodeValue: DC.B $03,$05,$07,$09,$0B,$10,$13 Entry: LDX #CodeTable

LDY #CodeValue

CLR DDRT ;8 switches on Port T

LDAA PTT ;Load in code word from switches LDAB #7 ;Seven elements in table

CheckNxtEntry: DECB

BLO NoMatchFound CMPA B,X

BEQ MatchFound BRA CheckNxtEntry MatchFound: LDAA B,Y

(101)

(102)

8. Accumulator D Indirect Addressing

• _{This indirect indexed mode adds the value in D to the}

value in the index register to form the address of a memory location M.

• _{The byte found at address M and the byte found at}

address M+1 form the address of the data.

• _{The identity of the register is placed in the postbyte,}

so the overall instruction length is 2 bytes.

• _Example:

If D = $10, X = $5000, ($5010) = $40, ($5011) = $50, and ($4050) = $12

(103)

(104)

Computed GOTO example

Assume D holds one of the values $0000, $0002, or $0004 (determined by the program at some time before the code below is executed.)

JMP [D,PC] ;(Go to PROG1 if D=0, PROG2 if D=2, PROG3 if D=4) GOTOPROG1 DC.W PROG1 ;Starting Address of Program 1 GOTOPROG2 DC.W PROG2 ;Starting Address of Program 2 GOTOPROG3 DC.W PROG3 ;Starting Address of Program 3 …………..

PROG1 NOP ;This is where Program 1 begins ………....

PROG2 NOP ;This is where Program 2 begins ...