5 Combinatorial Components
Use for data transformation, manipulation, interconnection, and for control:
• arithmetic operations - addition, subtraction, multiplication and division.
• logic operations - AND, OR, XOR, and NOT.
• comparison operations - greater than, equal to, and less than.
• bit manipulation operations - shift, rotation, extraction, and insertion.
• interconnect components - selectors, and buses - used to connect different components together.
• conversion components - decoders and encoders - used for conversion between different codes.
• universal components - ROMs and programmable-logic arrays (PLAs) - used primarily in the design of
control units.
5.0 Full adder
i = xi' yi' ci + xi' yi ci' + xi yi' ci' + xi yi ci = (xi' yi + xi yi') ci ' + (xi' yi' + xi yi) ci = (xi⊕ yi) ci' + (xi~ yi) ci = (xi⊕ yi) ⊕ ci ci+1 = xi' yi ci + xi yi' ci + xi yi ci' + xi yi ci = xi yi (ci' + ci) + ci (xi' yi + xi yi') = xi yi• 1 + ci (xi⊕ yi) si ci ci+ 1 xi yiCircuit for Full Adder
Full subtractor
bin x y bout d Comment 0 0 0 0 0 x-bin-y = d = 0-0 = 0 0 0 1 1 1 0-0-1 = borrow 2-1 = 1 0 1 0 0 1 1-0-0=1 with no borrow 0 1 1 0 0 1-0-1=0 with no borrow 1 0 0 1 1 x=0-1=-1 because of bin=1, therefore, borrow 2-1=1. Finally, 1-0=1 1 0 1 1 0 x-bin-y=borrow 2-1-1=0 1 1 0 0 0 1-1-0=0 with no borrow 1 1 1 1 1 x-bin=1-1=0. Then 0-1=borrow 2-1=1 F A X Y C i n C o u t S xi yi ci ci+1 si 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 10 1 1 1 1 0 0 0 1 bin 0 1 4 5 1 0 1 1 1 3 2 7 6 xy x'y y bin x'bin 0 1 1 1 0 0 0 1 bin 0 1 4 5 1 0 1 1 1 1 3 2 7 6 xy in in out xb xy yb b = ′ + ′ + y x b y x b y x b y x y x b xy y x b b y x b y x xyb b y x d in in in in in in in in in ⊕ ⊕ = ⊕ ′ + ′ ⊕ = ′ + ′ ′ + + ′ ′ = ′ ′ + ′ ′ + + ′ ′ = ) ( ) ( ) ( ) ( x y bin bo u t d
Circuit for Full Subtractor
5.1
Ripple-carry adders
F A x0y0 s0 F A x1 y1 s1 F A x2y2 s2 F A x3 y3 s3 F A x4y4 s4 F A x5 y5 s5 F A x6y6 s6 F A x7 y7 s7 co u t cin c2 c3 c4 c5 c6 c7 c15.3
Adder / Subtractor
F A x0 y0 f0 F A x1 y1 f1 F A x2 y2 f2 F A x3 y3 f3 F A x4 y4 f4 F A x5 y5 f5 F A x6 y6 f6 F A x7 y7 f7 co u t c7 c6 c5 c4 c3 c2 c1 c0 S5.4 Logic
Unit
F S X Y bi n bo u t d S Function Comment 0 X + Y Addition 1 X + Y ’ + 1 Subtraction5.5 Arithmetic-Logic
Unit
(ALU)
S
1M
c
4c
1S
0c
0c
2c
3 A E L Ea
0b
0 F Af
0 A E L Ea
1b
1 F Af
1 A E L Ea
2b
2 F Af
2 A E L Ea
3b
3 F Af
3 O v e r f l o wArithmetic Extender (AE)
The AE modifies the second operand and passes it to the FA to perform the arithmetic.
0 1 1 1 1 0 0 0 1 0 1 4 5 1 0 1 1 1 3 2 7 6 S'1bi i bS1S0 S'0b'i yi = MS1’bi + MS0’bi’ Map representation M S1 S0 bi yi A E Schematic diagram
M S1 S0 Function Name Function X Y c0
1 0 0 Decrement A – 1 A all 1’s 0 1 0 1 Add A + B A B 0 1 1 0 Subtract A + B ’ + 1 A B ’ 1 1 1 1 Increment A + 1 A all 0’s 1 Functional table M S1 S0 bi yi 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 Truth table yi = MS1’S0’bi’ + MS1’S0’bi + MS1’S0bi + MS1S0’bi’ = MS0’bi’(S1’ + S1) + MS1’bi(S0’+ S0) = MS0’bi’ + MS1’bi
Logic Extender (LE)
The logic operations are performed in the logic extender. The FAs are used simply as connections for the outputs.
Carry in signal
c0 – Notice that in the AE functional table, c0 = MS1
Overflow signal
c4 – The carry-out of the most significant bit represents an overflow in the case of unsigned arithmetic.
Overflow – The XOR of the carry-outs of the two most significant bits represents the overflow in the case of 2’s complement arithmetic. 0 0 0 1 1 1 1 0 i b i a 1 SS0 1 0 1 1 1 0 0 0 1 4 5 1 0 1 1 1 3 2 7 6 1 8 9 1 1 1 1 0 1 1 1 2 1 3 1 5 1 4 1 1 0 1 0 0 0 1 4 5 1 0 1 1 3 2 7 6 1 1 1 8 9 1 1 1 1 0 1 1 1 2 1 3 1 5 1 4 M = 0 M = 1 xi = M’S1’ S0’ai’ + M’S1 S0bi + S0 ai bi + S1 ai + Mai Map representation M S1 S0 bi xi L E ai Schematic diagram M S1 S0 bi xi L E ai
Simplified schematic diagram
M S1 S0 Function Name Function X Y c0
0 0 0 Complement A ’ A ’ 0 0
0 0 1 AND A AND B A AND B 0 0
0 1 0 Identity A A 0 0 0 1 1 OR A OR B A OR B 0 0 Functional table M S1 S0 xi Indices in map 0 0 0 ai’ 0, 4 0 0 1 ai bi 13 0 1 0 ai 10, 14 0 1 1 ai + bi 7, 11, 15 1 X X ai pass to AE Truth table
5.6 Decoders / Demultiplexers
To enable only one of n components.
E A1 A0 C3 C2 C1 C0 0 × × 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0
5.7 Selectors
/
Multiplexers
(MUX)
S1 S0 Y 0 0 D0 0 1 D1 1 0 D2 1 1 D3 D e c o d e r E 3 2 1 0 C3 C2 C1 C0 A1 A0 2-to-4 Decoder C3 C2 C1 C0 A2 A0 E 1 0 E 1 0 E1 0 E 1 0 E1 0 E1 0 E1 0 A0 E C5 C4 C7 C6
3-to-8 decoder implemented with 1-to-2 decoders
M U X 3 2 1 0 D3 D2 D1 D0 S0 Y S1 4-to-1 MUX D1 D0 D2 D3 D4 D5 D6 D7 0 1 2 3 4 5 6 7 S0 S2 S1 Decoder y
8-to-1 mux implemented with a decoder
D3 D2 D1 D0 S0 S1 0 S1 S2 S1 0 D5 D4 S1 0 D7 D6 S1 0 S1 0 S1 0 S1 0 y
5.8 Buses
A bus is for connecting several components together, however, only one component can send data to the bus at any
one time.
To construct a bus, use a tristate driver, whose output provides three different values, 0, 1, and Z. The value Z represents a high-impedance state which can be thought of as a disconnection from the bus.
D B u s D E0 E1 Y Y
5.9 Priority Encoders
A priority encoder has:
• n inputs, Dn-1, … D0,
• m outputs, Am-1, … A0, where n = 2m, which represents the index (decimal value) of the most significant
input bit Di that has a value equal to 1.
• an additional output call Any, which will be 1 whenever any of the inputs has a value that is different from
0.
2-to-1 priority encoder
E n c o d e r
D1 D0 0 1
A n y A0
4-to-2 priority encoder
E n c o d e r D3 D2 2 3 A n y A1 D1 1 D0 0 A0
5.10 Magnitude Comparators
A comparator compares two positive integers X and Y and then generates two boolean results G and L as follows:
Test G L X > Y 1 X ≤ Y 0 X < Y 1 X ≥ Y 0 X ≠ Y 1 1 X = Y 0 0
For the n-bit integers X and Y, we compare them one bit at a time, starting with the most significant bit,
Gi = (xi > yi) or [(xi = yi) and (Gi-1 > Li-1)]
Li = (xi < yi) or [(xi = yi) and (Gi-1 < Li-1)]
E Y 0 Z 1 D D1 D0 A0 Any 0 0 0 0 0 1 0 1 1 X 1 1 D3 D2 D1 D0 A1 A0 Any 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 X 0 1 1 0 1 X X 1 0 1 1 X X X 1 1 1
x1 y1 x0 y0 G L 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 0 x1 y1 x0 y0 G L
5.11 Shifters and Rotators
Use selectors to implement.
S2 S1 S0 Y Comment
0 0 × D No shift
0 1 × Not used
1 0 0 ShiftLeft(D) Shift left
1 0 1 RotateLeft(D) Rotate left
1 1 0 ShiftRight(D) Shift right
1 1 1 RotateRight(D) Rotate right
1 a0b0 0 0 0 1 0 0 0 1 a1b1 0 1 4 5 1 0 1 1 1 3 2 7 6 1 8 9 1 1 1 1 0 1 1 1 0 1 1 1 2 1 3 1 5 1 4 a0b0 0 1 1 1 1 0 0 0 0 0 1 a1b1 0 1 4 5 1 0 1 1 1 1 3 2 7 6 1 8 9 1 0 1 1 1 0 1 1 1 2 1 3 1 5 1 4 G = a1b1’ + a1a0b0’ + b1’a0b0’ L = a1’b1 + a1’a0’b0 + b1a0’b0
S1 S2 Selector 0 1 2 3 y3 Selector 0 1 2 3 y2 Selector 0 1 2 3 y1 Selector 0 1 2 3 y0 S0 Left Input 0 1 Selector R i g h t Input 0 1 Selector d0 d1 d2 d3
5.12 Read-Only Memories
ROMs can be thought of as a universal logic element that is able to implement concurrently several different Boolean functions that are defined on the same set of variables.
A 16 × 4 ROM can implement 4 functions.
Programmable ANDs and ORs.
a b c d a b c d a b c d a b c d
=
=
Use a 16 × 4 ROM to implement the following two functions:
f0 = w x' y' z + w x' y z' + w' x y' z' f1 = x y + w' z + w x' y
OR array
f
1f
0A
0w
4-to-16 decoder 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15A
1A
2A
3x
y
z
5.13 Programmable Logic Arrays (PLA)
ROMs are not very efficient when we use them to implement sparse functions, i.e. functions with only a small number of 1’s because in such cases, many of the words in the ROM will have a value of 0, which is a waste of silicon area.
A PLA differs from a ROM in the address decoder. Instead of a full decoder, PLAs use a programmable decoder call an AND array.
Use a 4 × 8 × 4 PLA to implement the following two functions:
f0 = w x' y' z + w x' y z' + w' x y' z' f1 = w' x y + w y' z
