Counters_and_RegistersModified.ppt

Introduction: Counters



Counters are circuits that cycle through a specified number of states.



Two types of counters:

 _{synchronous (parallel) counters}  _{asynchronous (ripple) counters}



Ripple counters allow some flip-flop outputs to be used as a source of clock for other flip-flops.

Asynchronous (Ripple)

Counters



Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse.



Also known as ripple counters, as the input clock pulse “ripples” through the counter – cumulative delay is a drawback.



n flip-flops  a MOD (modulus) 2n counter. (Note: A MOD-x counter cycles through x states.)

Asynchronous (Ripple)

Counters



Example: 2-bit ripple binary counter.



Output of one flip-flop is connected to the clock input of the next more-significant flip-flop.

K J

K J HIGH

Q₀ Q₁

Q₀

FF1 FF0

CLK C C

Timing diagram

00



01



10



11



00 ...

4

3 2

1 CLK

Q₀

Asynchronous Down Counters



Example: A 3-bit binary (MOD-8) down counter.

4 3 2 1 CLK Q₀ Q 1 1 1 0 0 0 1 0 0 0 8 7 6 5

1 0 1 0

1 0 1 0 001 000 111 010 011 100 110 101 1 K J K

J Q1

Cascading Asynchronous

Counters



Larger asynchronous (ripple) counter can be constructed by cascading smaller ripple counters.



Connect last-stage output of one counter to the clock input of next counter so as to achieve higher-modulus operation.



Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter.

Cascading Asynchronous

Counters



Example: A 6-bit binary counter (counts from 0 to 63) constructed from two 3-bit counters.

3-bit binary counter

3-bit binary counter

Count pulse

A₀ A₁ A₂ A₃ A₄ A₅

A5 A4 A3 A2 A1 A0

0 0 0 0 0 0

0 0 0 0 0 1

0 0 0 : : :

Synchronous (Parallel)

Counters



Synchronous (parallel) counters: the flip-flops are clocked at the same time by a common clock pulse.



We can design these counters using the sequential logic design process



Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs

A1 A0 A1+ A0+ TA1 TA0

0 0 0 1 0 1

0 1 1 0 1 1

1 0 1 1 0 1

1 1 0 0 1 1

01 00

Synchronous (Parallel)

Counters



Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs

A1 A0 A1+ A0+ TA1 TA0

0 0 0 1 0 1

0 1 1 0 1 1

1 0 1 1 0 1

1 1 0 0 1 1

TA₁ = A₀

TA₀ = 1

1

J A0 J A1

C C

Q

Q'

Q

Q' Q

Synchronous (Parallel)

Counters



Example: 3-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J, K inputs).

Present Next Flip-flop

state state inputs

A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 1 1 0 0 1 1

1 1 0 1 1 1 0 0 1

1 1 1 0 0 0 1 1 1

A2

A1

1 1

A2

A1

1 1 1

1

A2

A1

1 1 1

1

1 1 1

Synchronous (Parallel)

Counters



Example: 3-bit synchronous binary counter (cont’d).

TA2 = A1.A0 TA1 = A0 TA0 = 1

1 A₂

CP

A₁ A₀

K Q

J K

Q

J K

Synchronous (Parallel)

Counters



Example: 4-bit synchronous binary counter. TA₃ = A₂ . A₁ . A₀

TA₂ = A₁ . A₀

TA₁ = A₀

TA₀ = 1 1

K J

K

J A1

A₀ C C CLK Q Q' Q Q' Q Q' _K

J A2

C Q

Q' _K

J A3

C Q

Q' A₁.A_{0 A}

Synchronous (Parallel)

Counters



Example: Synchronous decade/BCD counter. Clock pulse Q3 Q2 Q1 Q0

Initially 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 (recycle) 0 0 0 0

T

₀

= 1

T

₁

=

Q

₃

'

.

Q

₀

T

₂

=

Q

₁

.

Q

₀

Synchronous (Parallel)

Counters



Example: Synchronous decade/BCD counter (cont’d).

T

₀

= 1

T

₁

=

Q

₃

'

.

Q

₀

T

₂

=

Q

₁

.

Q

₀

T

₃

=

Q

₂

.

Q

₁

.

Q

₀

+

Q

₃

.

Q

₀

1 Q1

Q₀ CLK T C Q Q' Q Q'

Q₂ Q₃

Up/Down Synchronous

Counters



Up/down synchronous counter: a bidirectional counter that is capable of counting either up or down.



An input (control) line Up/Down (or simply Up) specifies the direction of counting.

Up/Down Synchronous

Counters



Example: A 3-bit up/down synchronous binary counter. Clock pulse Up Q2 Q1 Q0 Down

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

TQ

₀

= 1

TQ

₁

= (

Q

₀

.

Up

) + (

Q

₀

'

.

Up'

)

TQ

= (

Q

.

Q

.

Up

)

+ (

Q

'

.

Q

'

.

Up'

)

Up counter

TQ₀ = 1

TQ₁ = Q₀

Down counter

TQ₀ = 1

Up/Down Synchronous

Counters



Example: A 3-bit up/down synchronous binary counter (cont’d).

TQ

₀

= 1

TQ

₁

= (

Q

₀

.

Up

) + (

Q

₀

'

.

Up'

)

TQ

₂

= (

Q

₀

.

Q

₁

.

Up

)

+ (

Q

₀

'

.

Q

₁

'

.

Up'

)

1

Q₁ Q₀

T C

Q

Q' Q

Q'

T C

Q

Q' Q

Q'

T C

Q

Q' Q

Q' Up

Designing Synchronous

Counters



Example: A 3-bit Gray code counter (using JK flip-flops).

100

000

001

101

111

110

011

010

Present Next Flip-flop

state state inputs

Q2 Q1 Q0 Q2+ Q1+ Q0+ JQ2 KQ2 JQ1 KQ1 JQ0 KQ0

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 1 0 X 1 X X 0

0 1 0 1 1 0 1 X X 0 0 X

0 1 1 0 1 0 0 X X 0 X 1

1 0 0 0 0 0 X 1 0 X 0 X

1 0 1 1 0 0 X 0 0 X X 1

Designing Synchronous

Counters



3-bit Gray code counter: flip-flop inputs.

0 1

00 01 11 10

Q₂

Q₁Q₀

X X X X

1

JQ₂ = Q₁.Q₀'

0 1

00 01 11 10

Q₂

Q₁Q₀

X X X X

1

0 1

00 01 11 10

Q₂

Q₁Q₀

X X X X 1

JQ₁ = Q₂'.Q₀

0 1

00 01 11 10

Q₂

Q₁Q₀

X X X X 1 0 1

00 01 11 10

Q₂

Q₁Q₀

X X

X X 1

JQ₀ = Q₂.Q₁ + Q₂'.Q₁' = (Q₂  Q₁)'

1

0 1

00 01 11 10

Q₂

Q₁Q₀

X X

X

X 1

Designing Synchronous

Counters

 3-bit Gray code counter: logic diagram.

JQ₂ = Q₁.Q₀' JQ₁ = Q₂'.Q₀ JQ₀ = (Q₂  Q₁)'

KQ₂ = Q₁'.Q₀' KQ₁ = Q₂.Q₀ KQ₀ = Q₂  Q₁

Q₁ Q₀

CLK

Q₂ J

C Q

Q' K

J C

Q

Q' K

J C

Q

Q'

K Q2'

Q₀'

Introduction: Registers



An n-bit register has a group of n flip-flops and some logic gates and is capable of storing n bits of information.



The flip-flops store the information while the gates control when and how new information is transferred into the register.



Some functions of register:  _{retrieve data from register}

Simple Registers



No external gates.



Example: A 4-bit register. A new 4-bit data is loaded every clock cycle.

A₃

CP

A₁ A₀

D Q

D

Q Q

D

A₂

D Q

Registers With Parallel Load



Instead of loading the register at every clock pulse, we may want to control when to load.



Loading a register: transfer new information into the register.

Requires a load control input.

Registers With Parallel Load

A₀

CLK

D Q

Load

I₀

A₁

D Q

A₂

D Q

A₃

D Q

I₁

I₂

I₃

Using Registers to implement

Sequential Circuits

 A sequential circuit may consist of a register (memory) and a combinational circuit.

Register

Combin-ational circuit Clock

Inputs Outputs

Next-state value



The external inputs and present states of the register determine

the next states of the register and the external outputs, through the combinational circuit.

Using Registers to implement

Sequential Circuits



Example 1:

A₁+ ₌



_{m(4,6) = A} 1.x' A₂+ ₌



_{m(1,2,5,6) = A}

2.x' + A2'.x = A2  x y =



m(3,7) = A₂.x

Present Next

state Input State Output A1 A2 x A1+ A2+ y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 0 0 1

1 0 0 1 0 0

1 0 1 0 1 0

1 1 0 1 1 0

1 1 1 0 0 1

A₁

A₂

x y

A₁.x'

Using Registers to implement

Sequential Circuits



Example 2: Repeat example 1, but use a ROM. Address Outputs

1 2 3 1 2 3

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 0 0 1

1 0 0 1 0 0

1 0 1 0 1 0

1 1 0 1 1 0

1 1 1 0 0 1

ROM truth table

A₁

A₂

x y

Shift Registers



Another function of a register, besides storage, is to provide for data

movements.

Shift Registers



Basic data movement in shift registers (four bits are used for illustration).

Data in Data out

(a) Serial in/shift right/serial out

Data in Data out

(b) Serial in/shift left/serial out

Data in

Data out

(c) Parallel in/serial out

Data out Data in

(d) Serial in/parallel out

Data out Data in

Serial In/Serial Out Shift

Registers



Accepts data serially – one bit at a time – and also produces output serially.

Q₀

CLK

D C

Q Q1 Q2 Q3

Serial data input

Serial data output

D C

Q D

C

Q D

Serial In/Serial Out Shift

Registers



Application: Serial transfer of data from one register to another.

Shift register A Shift register B

SI SO SI SO

Clock Shift control

CP

Wordtime Clock

Serial In/Serial Out Shift

Registers



Serial-transfer example.

Timing Pulse Shift register A Shift register B Serial output of B

Initial value 1 0 1 1 0 0 1 0 0

After T1 1 1 0 1 1 0 0 1 1

After T2 1 1 1 0 1 1 0 0 0

After T3 0 1 1 1 0 1 1 0 0

Serial In/Parallel Out Shift

Registers



Accepts data serially.



Outputs of all stages are available simultaneously.

Q₀ CLK

D C

Q

Q₁ D

C Q

Q₂ D

C Q

Q₃ D

C Q Data input

D C CLK

Data input

Parallel In/Serial Out Shift

Registers



Bits are entered simultaneously, but output is serial.

D₀

CLK

D C

Q

D₁

D C

Q

D₂

D C

Q

D₃

D C

Q Data input

Q₀ Q₁ Q_{2 Q}

3

Serial data out SHIFT/LOAD

Parallel In/Serial Out Shift

Registers



Bits are entered simultaneously, but output is serial.

Logic symbol

C

CLK SHIFT/LOAD

D₀D₁D₂D₃

Parallel In/Parallel Out Shift

Registers



Simultaneous input and output of all data bits.

Q₀ CLK

D C

Q

Q₁ D

C Q

Q₂ D

C Q

Q₃ D

C Q Parallel data inputs

D₀ D₁ D₂ D₃

Bidirectional Shift Registers



Data can be shifted either left or right, using a control line

RIGHT/LEFT (or simply RIGHT) to indicate the direction.

D C

Q D

C

Q D

C

Q D

C Q

Q₁ Q₂ Q3

RIGHT/LEFT

Serial data in

Bidirectional Shift Registers



4-bit bidirectional shift register with parallel load.

CLK

I I I I

Serial input for shift-right D Q D Q D Q D Q Clear 4x1 MUX s1 s0

3 2 1 0

4x1 MUX 3 2 1 0

4x1 MUX 3 2 1 0

4x1 MUX 3 2 1 0

A₄ A₃ A₂ A₁

Bidirectional Shift Registers



4-bit bidirectional shift register with parallel load.

Mode Control

s1 s0 Register Operation

0 0 No change

0 1 Shift right

1 0 Shift left

Shift Register Counters



Shift register counter: a shift register with the serial output connected back to the serial input.



They are classified as counters because they give a specified sequence of states.

Ring Counters



One flip-flop (stage) for each state in the sequence.



The output of the last stage is connected to the D input of the first stage.



An n-bit ring counter cycles through n states.

Ring Counters



Example: A 6-bit (MOD-6) ring counter.

CLK

Q₀

D Q D Q Q1 D Q Q2 D Q Q3 D Q Q4 D Q Q5

CLR PRE

Clock Q0 Q1 Q2 Q3 Q4 Q5

0 1 0 0 0 0 0

1 0 1 0 0 0 0

2 0 0 1 0 0 0

3 0 0 0 1 0 0

4 0 0 0 0 1 0

5 0 0 0 0 0 1

100000

010000

001000

000100 000010

Johnson Counters



The complement of the output of the last stage is connected back to the D input of the first stage.



Also called the twisted-ring counter.



Require fewer flip-flops than ring counters but more flip-flops than binary counters.



An n-bit Johnson counter cycles through 2n states.

Johnson Counters



Example: A 4-bit (MOD-8) Johnson counter.

Clock Q0 Q1 Q2 Q3

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

CLK

Q₀

D Q D Q Q1 D Q Q2 D Q

Q₃' CLR

Q'

0000

0001

0011

0111 1110

Johnson Counters



Decoding logic for a 4-bit Johnson counter.

Clock A B C D Decoding

0 0 0 0 0 A'.D'

1 1 0 0 0 A.B'

2 1 1 0 0 B.C'

3 1 1 1 0 C.D'

4 1 1 1 1 A.D

5 0 1 1 1 A'.B

6 0 0 1 1 B'.C

7 0 0 0 1 C'.D

A'

D' State 0

A

State 4 B

C' State 2

C

D' State 3

A

B' State 1

B'