FPGA based Temperature Sensor and Control
A
Project Report
Submitted
As Essential Part of the Course
Hardware Design Methodology
(M. Tech. MI)
Submitted by
ANKITA VERMA (IMI2012003)
RAJAN BHARTI (IMI2012018)
Under the Guidance of:
Dr. Satish Kumar Singh
Assistant Professor
INDIAN INSTITUTE OF INFORMATION TECHNOLOGY
ALLAHABAD-211 012 (INDIA)
Abstract: We need temperature control in various places . It can be used to control the temperature of furnaces or also room temperature.We have used LM35 as temperature sensor whose output is compared to the user input desired value, the resulting signal is used to control the temperature.
Introduction: Field programmable gate arrays (FPGAs) are extensively used in rapid prototyping and verification of a conceptual design and also used in electronic systems when the mask-production of a custom IC becomes prohibitively expensive due to the small quantity. Many system designs that used to be built in custom silicon VLSI are now implemented in Field Programmable Gate Arrays. This is because of the high cost of building a mask production of a custom VLSI especially for small quantity.
In this the main objective is to design a FPGA based temperature sensor and control. We are using LM35 temperature sensor IC. The LM35 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to the Celsius (Centigrade) temperature. The LM35 thus has an advantage over linear temperature sensors calibrated in ˚ Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient Centigrade scaling.Its analog output is given to the analog to digital module converter board (AD7476). Its digital output can be read using FPGA.
Block diagram:
The LM35 is rated to operate over a −55˚ to +150˚C temperature range. Calibrated directly in ˚ Celsius (Centigrade). It has Linear scale factor of +10.0mV/˚C. Its output is given to 12 bit A/D converter.
Methodology and Modeling: We have divided the problem into submodules.In the first module we are reading the data from the sensor output, which is a FSM according to three state. In second module, we are converting the read data to BCD format , which is further displayed on seven segment display. It contains
concurrent processes to compare user and sensor value and take suitable actions, to convert decimal to BCD which is further displayed on a seven segment display.
Implementation:
(A) RTL Description(VHDL Code): To read data from ADC
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity AD1 is Port ( --General usage CLK : in std_logic; RST : in std_logic;
--Pmod interface signals SDATA1 : in std_logic; SCLK : out std_logic; nCS : out std_logic;
--User interface signals
DATA1 : out std_logic_vector(11 downto 0); START : in std_logic;
DONE : out std_logic );
end AD1 ;
architecture AD1 of AD1 is
type states is (Idle, ShiftIn, SyncData);
signal current_state : states; signal next_state : states; signal clk_div:std_logic;
signal temp1 : std_logic_vector(15 downto 0);
shared variable clk_div1: std_logic:='0'; signal clk_counter : std_logic_vector(1 downto 0);
signal shiftCounter : std_logic_vector(3 downto 0) := x"0";
signal enShiftCounter: std_logic; signal enParalelLoad : std_logic;
shared variable count:std_logic_vector(1 downto 0):="00"; begin clock_divide : process(rst,clk) begin if rst = '1' then clk_counter <= "00";
elsif (clk = '1' and clk'event) then count:=count+1; if (count="11") then clk_div1:=not clk_div1; count:="00"; end if; end if; clk_div<=clk_div1; end process; SCLK <= not clk_div;
counter : process(clk_div, enParalelLoad, enShiftCounter)
begin
if (clk_div = '1' and clk_div'event) then
if (enShiftCounter = '1') then temp1 <= temp1(14 downto 0) & SDATA1;
shiftCounter <= shiftCounter + '1'; elsif (enParalelLoad = '1') then shiftCounter <= "0000";
DATA1 <= temp1(11 downto 0); end if; end if; end process; --- --
SYNC_PROC: process (clk_div, rst) begin
if (clk_div'event and clk_div = '1') then if (rst = '1') then current_state <= Idle; else current_state <= next_state; end if; end if; end process;
OUTPUT_DECODE: process (current_state) begin
if current_state = Idle then enShiftCounter <='0'; DONE <='1';
nCS <='1';
enParalelLoad <= '0';
elsif current_state = ShiftIn then enShiftCounter <='1';
DONE <='0'; nCS <='0';
enParalelLoad <= '0';
else --if current_state = SyncData then enShiftCounter <='0'; DONE <='0'; nCS <='1'; enParalelLoad <= '1'; end if; end process;
NEXT_STATE_DECODE: process (current_state, START, shiftCounter)
begin
next_state <= current_state; -- default is to stay in current state case (current_state) is when Idle => if START = '1' then next_state <= ShiftIn; end if; when ShiftIn => if shiftCounter = x"F" then next_state <= SyncData; end if; when SyncData => if START = '0' then next_state <= Idle; end if; when others => next_state <= Idle; end case; end process; end AD1;
12 bit binary to 7 segment display
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.numeric_std.all; entity BCD12SEVSEG is
Port ( u_data:in std_logic_vector(7 downto 0);d_in : in STD_LOGIC_VECTOR (11 downto 0);clk,done: in std_logic;
d_o : out STD_LOGIC_VECTOR (10 downto 0),control:out std_logic);
end BCD12SEVSEG;
architecture Behavioral of BCD12SEVSEG is
signal temp: std_logic_vector(11 downto 0):="000000000000";
signal temp1: std_logic_vector(15 downto 0):="0000000000000000";
signal shcntr: integer:=0;
signal i1,i2,i3,i4: std_logic_vector(3 downto 0); signal state: integer range 0 to 5;
shared variable d_out1,d_out2,d_out3,d_out4: std_logic_vector(10 downto 0);
shared variable c:std_logic_vector(1 downto 0):="00";
shared variable cld: integer:=0; signal clk_t:std_logic;
shared variable clkt: std_logic:='0'; begin
-- process begin
wait until rising_edge(clk);
case state is when 0 => if(done='1') then temp<=d_in; shcntr<=0; temp1<=(others =>'0'); state<=1; end if; when 1 => if shcntr/=12 then
temp1<=temp1(14 downto 0) & temp(11); temp<=temp(10 downto 0) & '0';
shcntr<=shcntr+1; state<=2;
end if;
when 2=> if shcntr<12 then
state<=3;
elsif temp1(7 downto 4)>="0101" then state<=4;
elsif temp1(11 downto 8) >="0101" then state<=5; else state<=1; end if; else state<=0; end if;
when 3=> temp1(3 downto 0)<=temp1(3 downto 0)+"0011";
if temp1(7 downto 4)>="0101" then
temp1(7 downto 4)<=temp1(7 downto 4)+"0011"; state<=1;
elsif temp1(11 downto 8) >="0101" then temp1(11 downto 8) <=temp1(11 downto 8) +"0011";
state<=1; else state<=1; end if;
when 4=> temp1(7 downto 4)<=temp1(7 downto 4)+"0011";
if temp1(11 downto 8) >="0101" then temp1(11 downto 8) <=temp1(11 downto 8) +"0011";
state<=1;
elsif temp1(3 downto 0)>="0101" then
temp1(3 downto 0)<=temp1(3 downto 0)+"0011"; state<=1;
else state<=1; end if;
when 5=> temp1(11 downto 8) <=temp1(11 downto 8) +"0011";
if temp1(3 downto 0)>="0101" then
temp1(3 downto 0)<=temp1(3 downto 0)+"0011"; state<=1;
elsif temp1(7 downto 4)>="0101" then
temp1(7 downto 4)<=temp1(7 downto 4)+"0011"; state<=1; else state<=1; end if; process(u_data,temp1) begin
if(udata>temp(11 downto 4)) then control<='1'; else control<='0'; end if; end process; end case; end process; process(shcntr,clk) begin if shcntr=12 then
if clk'event and clk='1' then i1<=temp1(3 downto 0); i2<=temp1(7 downto 4); i3<=temp1(11 downto 8); i4<=temp1(15 downto 12); end if; end if; end process; process(i1,clk) begin case i1 is when "0000"=> d_out1:="11100000001"; when "0001"=> d_out1:="11101001111"; when "0010"=> d_out1:="11100010010"; when "0011"=> d_out1:="11100000110"; when "0100"=> d_out1:="11101001100"; when "0101"=> d_out1:="11100100100"; when "0111"=> d_out1:="11100001111"; when "1000"=> d_out1:="11100000000"; when "1001"=> d_out1:="11100000100"; when others => d_out1:="11100110000"; end case; end process; process(i2,clk) begin case i2 is when "0000"=> d_out2:="11010000001"; when "0001"=> d_out2:="11011001111"; when "0010"=> d_out2:="11010010010"; when "0011"=> d_out2:="11010000110"; when "0100"=> d_out2:="11011001100"; when "0101"=> d_out2:="11010100100"; when "0111"=> d_out2:="11010001111"; when "1000"=> d_out2:="11010000000";
when "1001"=> d_out2:="11010000100"; when others => d_out2:="11010110000"; end case; end process; process(i3,clk) begin case i3 is when "0000"=> d_out3:="10110000001"; when "0001"=> d_out3:="10111001111"; when "0010"=> d_out3:="10110010010"; when "0011"=> d_out3:="10110000110"; when "0100"=> d_out3:="10111001100"; when "0101"=> d_out3:="10110100100"; when "0111"=> d_out3:="10110001111"; when "1000"=> d_out3:="10110000000"; when "1001"=> d_out3:="10110000100"; when others => d_out3:="10110110000"; end case; end process; process(i4,clk) begin case i4 is when "0000"=> d_out4:="01110000001"; when "0001"=> d_out4:="01111001111"; when "0010"=> d_out4:="01110010010"; when "0011"=> d_out4:="01110000110"; when "0100"=> d_out4:="01111001100"; when "0101"=> d_out4:="01110100100"; when "0111"=> d_out4:="01110001111"; when "1000"=> d_out4:="01110000000"; when "1001"=> d_out4:="01110000100"; when others => d_out4:="01110110000"; end case; end process; --- process(clk) begin if(rising_edge(clk)) then cld:=cld+1; if (cld=50000) then clkt:=not clkt; cld:=0; end if; end if; clk_t<=clkt; end process; --- process(clk_t) begin if (rising_edge(clk_t)) then if( c="00") then d_o<=d_out1; c:=c+1; elsif (c="01") then d_o<=d_out2; c:=c+1; elsif (c="10") then d_o<=d_out3; c:=c+1; elsif (c="11") then d_o<=d_out4; c:="00"; else null; end if; else null; end if; end process; end Behavioral;
Top Module to interconnect two modules
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port ( clk_i,sdata,start,rst : in
STD_LOGIC;u_data:in std_logic_vector(7 downto 0); ncs,sclk,control : out STD_LOGIC;
d1_out : out STD_LOGIC_VECTOR (10 downto 0));
end top;
architecture Behavioral of top is
component AD1 is Port(CLK : in std_logic; RST : in std_logic; SDATA1 : in std_logic; SCLK : out std_logic; nCS : out std_logic;
DATA1 : out std_logic_vector(11 downto 0); START : in std_logic;
DONE : out std_logic );
component BCD12SEVSEG is
Port ( u_data:in std_logic_vector(7 downto 0);d_in : in STD_LOGIC_VECTOR (11 downto 0);clk,done: in std_logic;
d_o : out STD_LOGIC_VECTOR (10 downto 0); control:out std_logic);
end component BCD12SEVSEG;
signal data:std_logic_vector(11 downto 0); signal done:std_logic;
begin
ad: AD1 port
map(clk=>clk_i,RST=>rst,SDATA1=>sdata,SCLK=>scl k,nCS=>ncs,DATA1=>data,START=>start,DONE=>do ne); bcd: BCD12SEVSEG port map(u_data=>u_data,d_in=>data,clk=>clk_i,done=> done,d_o=>d1_out, control=>control); end Behavioral;
Applications and related modifications:
This can be applied to many industrial application
as well as in some home appliances also.
Reference:
[1] Nexys 2 reference manual [2] AD7476 datasheet
[3] Pmod AD1 reference sheet [4] LM 35 datasheet
