Compliant Probe Substrates for Testing High Pin-Count Chip Scale Packages

Compliant Probe Substrates for Testing High Pin-Count Chip Scale Packages

School of Electrical and Computer Engineering

Microelectronics Research Center, Georgia Institute of Technology 791 Atlantic Drive NW, Atlanta, Georgia

Phone: (404) 894-9913, Fax: (404) 894-0462, E-mail: [email protected]

Abstract

The ultra high I/O density Sea of Leads (SoL) chip-scale package [1] has the potential to revolutionize testability of a gigascale system-on-a-chip (SoC). With this wafer-level packaging technology, testing and burn-in can be migrated to the wafer-level. The parallel nature of wafer-level testing and burn-in - facilitated by SoL - can drive down the cost [2] of obtaining a packaged known good die. The extremely high I/O density of the SoL package – typically 12,000 I/O / cm2, provides access to internal nodes on a chip. Greater node access enables partitioning of the device-under-test (DUT) into smaller units while maintaining the ability to control and observe them. In turn, smaller units for testing equates to reduced test vector sets and shorter test times – a much sought after objective. A compliant probe technology has been developed to contact the SoL package. It provides a high-density, low-parasitic, and reliable interface between the package and automated test equipment (ATE) during testing. The compliant probes when used jointly with SoL offer a novel approach to efficiently testing a future SoC.

I. Introduction

Lowering the cost of manufacturing a known good die is the key driver for developing new and improved methods for testing semiconductor devices. Conventional tail-end-of-line processing calls for the individual packaging, test, and burn-in of singulated dice. This process can be very time consuming, redundant, and hence very expensive. Extending the use of wafer-level processing to the tail-end-of-line has the potential to reduce not only cost but also time to market. Figure 1 illustrates a tail-end-of-line process flow where packaging, burn-in and test are performed at the wafer-level. When the wafer is finally diced, the result is a packaged known good die.

Figure 1: Flow of tail-end-of-line using wafer-level batch processing.

The two main components required to successfully transfer wafer-level processing to tail-end-of-line are a wafer-level package and compatible parallel burn-in and test methods.

A novel high-density compliant probe technology is presented in this paper. The probes can be batch fabricated and used in various probe card configurations to provide a reliable and high-speed interface between high pin-count packages on the one side and the ATE on the other. All probe card samples shown here were designed and fabricated to simultaneously contact multiple die sites on a SoL wafer-level package having 103I/O / cm2.

A brief background of the SoL technology is provided in Section II. Section III discusses how SoL enhances testability. The requirements for a probe substrate compatible with high pin-count packages are discussed in Section IV. The fabrication process of the compliant probes along with experimental results is illustrated in Section V. The application space of the compliant probes is not restricted to particular probe cards for contacting only wafer-level packages. With slight design modifications, they can be utilized in different scenarios to interface various devices-under-test. Some interesting configurations for contacting single and multiple packages (including wafer-level packages) are presented in Section VI. Conclusions, acknowledgments, and references follow in subsequent sections.

II. Ultra High I/O Density Package: Sea of Leads (SoL) SoL (Figure 2) is an ultra high input/output (I/O) compliant wafer-level package. The current generation of the SoL package consists of >104 x-y-z compliant leads per cm2 and shows promise of meeting high current (>350 A) and high I/O bandwidth requirements as far ahead as the 35nm technology node [1].

SoL package fabrication immediately follows after the conclusion of back-end-of-line processing. The high-I/O density package is fabricated using three monolithic masking steps. The lead (I/O) density is maximized by designing various lead lengths as a function of the necessary in-plane compliance, which increases linearly from the center. The orientation of the leads is also designed to match the local directions of expansion of the silicon substrate. Two different lead lengths (53µm leads on a 80 x 80µm square lattice and 106µm leads on a 80 x 160µm rectangular lattice) totaling 12,000 leads per cm2are distributed across each 1-cm2die [1]. The large number of available I/O, and the wafer-level nature of the SoL package provide a unique opportunity to make wafer-level test and burn-in a reality.

End of Back End WAFER-LEVEL PACKAGE WAFER

BURN-IN Full TEST

Mark and Mark Cure Dice Known Good Package Ball Inspection Ready for Board Attach

Figure 2: SEM image of one quadrant (~3,000 leads) in the

fabricated SoL 12k leads per cm2package [1].

III. SoL Enhances Testability

Two key aspects of testing an integrated circuit are controllability and observability [3]. One needs to be able to control what (test) signals are entering the system and to observe the response to those stimuli. Today, only a small number of the I/O’s on a package are devoted to testing. Test vectors are generated from complex algorithms and are applied using test application methods, such as Boundary Scan and Built-in-Self-Test [2,3]. Test designers have to ensure not only that the targeted faults have been activated but also that the effects of those faults are propagated to at least one of the few observable outputs.

The use of SoL as a packaging technology will allow designers to devote a large number of I/O’s to testing, perhaps even more in number than the total I/O’s on some of today’s packages. The high I/O density of the SoL package allows for physical partitioning of a SoC into individual cores. Each core can then be pseudoexhaustively tested, individually or in parallel. Breaking up the DUT into smaller units will reduce the volume of generated test patterns, while still maintaining high test fault coverage.

SoL enables the opportunity to perform massively parallel test and burn-in. As the dice are still in wafer form after packaging, it becomes possible to test multiple packaged dice at once. With multi-die site testing, the test time per wafer is reduced as the mechanical stepping probe head now requires fewer steps to cover an entire wafer. Shorter test time per wafer translates to reduced test costs. Multi-die site testing is the first step towards wafer-level test and burn-in.

However, the benefits this high-density, high-bandwidth, and low-parasitic wafer-level package provides for testing can only be truly realized with use of a compatible probe substrate to interface the DUT with external test equipment. The requirements of such a probe substrate are discussed next. IV. Requirements for a High-Density Probe Substrate

Ultra-high density packages like SoL can enhance the testability of SoCs by laying the basis for a divide-and-conquer [2] approach, but there needs to be a way to probe the

package I/O’s during the test. The requirements of such a probe substrate can be divided into three levels: (i) at the contact level, (ii) at the substrate level, and (iii) at the system level (Table I).

(i) At the Contact Level:

a. Sufficient contact force: When trying to contact a large number of package I/O’s at once, the contact force exerted by the probes should be just enough to make good electrical contact, while causing little or no damage to the probed solder bumps or metal pads on the DUT.

b. Low contact resistance: When two dissimilar materials are brought in contact with each other, their interaction causes an increase in the resistance. To minimize signal degradation, it is important that the design of the probes and the materials selected are such as to have the lowest contact resistance possible. c. Re-usability: In order to minimize production-testing

costs, it is mandatory that the selected probe technology be able to repeatedly make reliable contact with thousands of devices-under-test before replacement of the probe substrate becomes necessary. d. High density: As discussed in the previous section, high-density packages like SoL provide access to previously unreachable nodes on the chip. A compatible probe technology will need to keep pace with higher I/O densities, and smaller I/O pitches to be able to control and observe signals during testing. In the case of SoL, I/O pitch is in the 60-80µm range. e. Vertical compliance: Transverse compliance is a must

to account for the non-planarity of the DUT and/or the probe substrate when they are brought into contact with each other. This compliance can either be built into the package or into the probe substrate or both. Spring-loaded probes have traditionally served this purpose well, but with shrinking I/O pitches, a new approach is warranted.

(ii) At the Substrate Level:

a. High-density interconnects for signal redistribution: The probe substrate can be likened to a printed wiring board (PWB). Hence, high-density interconnects are needed to supply power, ground, control signals, and test vectors from the ATE to the DUT.

b. Pin-count reduction: ATE costs scale linearly with signal count and so it is not expected that the ATE pin count will keep up with increasing package I/O count. Therefore, during test, the probe substrate ought to serve as an interface adapter between the high I/O DUT on one side and ATE of much lower I/O count on the other. The mismatch calls for some pin-count reduction techniques to be implemented in the probe substrate. These techniques could include the use of common power and ground planes, and combination of other common signals within the probe substrate. c. Matched coefficient of thermal expansion (CTE)

between the substrate and the DUT: Testing multiple dice at once, or using the probe substrates for

test-during-burn-in (at elevated temperatures) can cause the probe substrate and the DUT to heat up and expand at different rates. This could potentially cause a break in the electrical contact between a package I/O and its respective probe. To overcome this, either the probe substrate needs to be made of a material with a CTE close to that of the DUT substrate or some lateral compliance needs to be built into the probe or the package I/O.

(iii) At the System Level

a. Multi-die site contact: Testing devices in parallel can greatly reduce device production costs. A wafer-level package like SoL enables parallel testing of multiple dice as the devices are still in the wafer form after packaging. Hence, the probe substrate should be able to contact multiple dice at once. The ideal situation would be when each and every die on the wafer can be tested in parallel – a full wafer-level test.

b. Efficient thermal management: While it would be cost-efficient to test as many devices in parallel as possible, there needs to be a way to effectively remove the heat generated by powering-on multiple dice on a wafer. Thermal management is an important facet of any system that hopes to achieve multi-die site or wafer-level testing.

Table I: A comprehensive list of requirements for high-density

probe substrates.

Contact Level Substrate level System level

♦Sufficient Contact Force ♦Low Contact Resistance ♦Re-usability ♦High Density ♦Vertical Compliance ♦ High-density Interconnect for signal redistribution

♦ Fan-out and Pin-count reduction ♦ Matched CTE between probe substrate and DUT ♦Efficient Thermal Management ♦Multi-die site contact→ WAFER-LEVEL

V. Compliant Probes: Design and Fabrication

The requirements of the probe substrate at the contact level are perhaps the most important. A novel contact probe structure has been conceived, designed, and fabricated to fulfill these requirements.

The design of the compliant probes is a modification of the leads from the compliant wafer-level package [4]. They are designed to provide compliance in the x, y, and z direction. An SEM image of a single compliant probe is shown in Figure 3. The structure consists of an ‘S’- shaped lead connected to the substrate through a via on one end and terminated by a circle at the other. On top of the circle lie four prism-shaped contacts where the target solder bump would sit. The “S”-shaped lead rests on a compliant polymer and has been shown to provide compliance along all three axes [4].

Figure 3: SEM image of a single compliant probe consisting of an

‘S’-shaped lead, and four prism-shaped metal probe tips. Thousands of probes like this one can be fabricated simultaneously on the probe substrate.

The vertical compliance can be further increased by fabricating embedded air gaps under the leads [1]. The amount of compliance is then dependant on the geometry of the air gaps. In one particular case, as much as 35µm of displacement has been reported for a 15mN applied force [1].

Compliance along the x-y axes compensates for any CTE mismatch between the probe substrate and the DUT. Compliance along the z-axis ensures that a stable low-resistance contact can be achieved between the probes and the bumps on the package. When a compliant package, such as SoL, is to be contacted, the probes provide further flexibility for better contact. On the other hand, the probes provide all the requisite compliance while contacting a non-compliant package. The four prism-shaped contacts are designed to make pressure contact around the edges of the target solder bump (Figure 4). This prevents damage to the top side of the solder bump, which is the final point of attachment to the PWB. The distance between the probe contacts and their height can be varied to contact solder bumps of different sizes. The probe shown in Figure 3 was specifically designed to contact a solder bump 50µm tall and wide.

The fabrication process of the compliant probes is based on that of the compliant wafer-level package [4]. A schematic of the process flow is shown in Figure 5. The fabrication assumes that the probe card has metal pads to which the probes are to be connnected (Figure 5 (a)). The first step in the process is to spin coat a compliant interposer on the substrate (Figure 5(b)). BFGoodrich’s Avatrel 2000P photodefinable polymer, which has a low tensile modulus of 0.5 Gpa and a CTE of 50 ppm, was used. The Avatrel 2000P is a polynorbornene type polymer. It has a low electrical dielectric constant of 2.6 which causes minimal signal degradation due to minimal parasitic capacitance.

After curing the polymer, a thin layer of aluminum (Al) is sputtered to serve as an etch mask. The via pattern is defined using the first masking step, and etched using a reactive ion etcher (Figure 5(c)). This exposes the metal pads beneath the

polymer. The Al etch mask is then removed, and a layer of titanium/gold/titanium (Ti/Au/Ti) is deposited. The Ti/Au/Ti layer is the seed layer for electroplating of the ‘S’-shaped leads. The bottom Ti layer provides strong adhesion between the Au lead and the polymer beneath. A layer of negative photoresist about 10-12 µm thick is deposited on the seed layer, and the in-plane x-y-z compliant leads are monolithically patterned in the photoresist across the substrate. Hence, all the leads on the probe substrate can be fabricated in one single step – whether they are to contact one single die, multiple die sites, or an entire wafer. The top Ti layer is etched away to reveal the Au seed layer. Au leads are then electroplated on the exposed seed layer to a thickness of about 10 µm (Figure 5(d)). Once electroplating is complete, the photoresist and the seed layer are removed. A new seed layer of Ti/Au/Ti is deposited on the substrate followed by a layer of negative photoresist about 15µm thick. The thickness of the photoresist can be varied depending upon the required probe contact height. A third and final masking step is used to define the small prism-shaped bumps on the edge of each probe lead (Figure 5(e)). Once again, all of these contacts are fabricated in a batch process. The top Ti layer is etched away, and a similar electroplating process is used to form the probe contacts. Au is very conductive and does not oxidize, which makes it a good choice for the contact tips. However, a harder metal with comparable conductivity will be able to withstand a larger number of probe touchdowns. Nickel and copper are being investigated as suitable alternatives. After plating to the required thickness, the photoresist and the seed layer are removed to leave behind the complete array of compliant probes. Figures 6 and 7 show SEM images of compliant probes fabricated in an area array configuration.

Figure 4: Schematic showing prism-shaped probe tips making

contact with a solder bump. The tips are designed to contact the target solder bump at four locations. The separation between the probe tips and their heights can be adjusted depending on the size of the solder bump to be probed.

Figure 5: Fabrication process of compliant probes. (a) Probe

substrate with metal pads. (b) Spin on compliant polymer. (c) Mask #1: Etch vias to expose the metal pads underneath. (d) Mask #2: Electroplate compliant leads onto exposed seed layer. (e) Mask #3: Electroplate probe contacts on tips of exposed compliant probes.

Figure 6: SEM image of an area array of compliant probe tips. Each

of these would interface with solder bumps on the package laid out in a similar area array configuration.

(b) Polynorbornene

Metal pads

(a)

Plated gold leads

(d) (c) vias

Plated gold contacts

(e)

Solder Bump

Figure 7: An up-close SEM image of four prism-shaped metal

contacts which make up a single compliant probe tip.

VI. Probe Card Configurations

The compliant probes and modifications thereof can be easily adapted for use in different probe card configurations. The schematic of a simple probe substrate, designed to meet the requirements discussed in Section IV, is shown in Figure 8. The substrate consists of a multi-layer structure where high-density interconnects are used for signal redistribution. Signals from one side of the substrate to the other are propagated along an array of through-substrate vias. The multi-layer substrate also adjusts for the pin-count mismatch between the number of probes contacting the package and the smaller number of pins on the tester being used. It does this by combining power, ground, and common control signals.

Figure 8: Schematic of proposed multi-layer compliant probe

substrate.

Unfortunately, the reduction factor achieved by simple signal recombination and the use of power/ground planes is quite modest. Such strategies might reduce the number of ATE connections to perhaps one half that on the wafer surface. In some cases, this is still a very large number of contacts, given that each die site could have hundreds or even thousands of connections on its surface.

Ideally, simultaneous connection to all die sites would be desired to permit parallel testing. Connecting hundreds of thousands of signals to an ATE is well beyond what is feasible today. Furthermore, even if this practical problem could be solved, the cost of such an ATE would be prohibitive. A typical ATE today costs on the order of several thousand

dollars per channel. It is required that the number of signals between the ATE and probe substrate be significantly reduced. The use of built-in self test (BIST) and the compliant probe substrate could achieve such signal count reduction. If all chips are designed to be completely self-testable, then only a simple (usually serial) communications bus is necessary to allow the external test equipment to initiate the self test and to capture the final result (pass/fail response or more detailed diagnostic data).

One bus for such purposes is defined by the IEEE 1149.1 standard (sometimes called “boundary scan”). The standard requires just four signals, TMS (Test Mode Select), TCK (Test Clock), TDI (Test Data Input), and TDO (Test Data Output). These four signals define an interface to what is known as the Test Access Port (TAP). A logic controller and some dedicated registers are also needed to handle the 1149.1 standard instructions and data communications. The device inputs and outputs are enhanced to permit the substitution of I/O data with data bits received through the TAP during testing – hence the term “boundary scan”. Optional features of the 1149.1 standard permit control of the BIST structures within the chip.

In principle, using the 4-wire 1149.1 test port standard together with complete BIST, each chip on the wafer would only require four I/O signals, power connections, and perhaps higher-speed clocks for at-speed testing. This would reduce the total number of connections to the ATE to the order of several hundred, which is easily accomplished with present technology.

However, there are many cases where complete BIST is not implemented within the chip design. More often, partial BIST is implemented and the number of ATE signals needed for thorough testing remains high. In these cases, a local “test support processor” (TSP) [5,6,7] could be mounted to the compliant probe substrate as illustrated in Figure 9. The TSP provides local generation of test stimuli and capture/analysis of chip output responses. It is a customized IC or module, designed specifically to support testing a particular device type. In effect, the TSP provides some of the BIST logic off the chip while keeping it in close proximity to the device I/O structures. This creates a tight testing environment, and may even represent a more accurate emulation of the system environment that such high-density chips are likely to encounter. Resistive and/or capacitive loads can also be incorporated into the TSP for such purposes. In this way, at-speed functional test of high-performance ICs can be conducted at the wafer-level. Arrays of TSPs as illustrated in Figure 9 would provide for parallel functional test.

Figure 9: Use of Test Support Processors for parallel at-speed

functional testing. Multiple TSPs are mounted on a compliant probe substrate for multi-die site testing.

Compliant Probes Interface with ATE Multi-layered probe substrate

VII. Conclusions

The use of SoL not only extends wafer-level batch processing to the tail-end-of-line phase of the manufacturing cycle but also enhances the testability of a future SoC by allowing increased access to previously unreachable nodes on the die. The fabrication of compliant wafer-level package leads has been engineered for use as high-density compliant probes. Probe substrates fitted with these high-density, batch fabricated compliant probes facilitate massively parallel test and are a first step towards achieving full wafer contact and test capabilities.

VIII. Acknowledgments

This work was sponsored by the Interconnect Focus Center (IFC) and funded in part by MARCO under contract B-12-M00 and DARPA under grant B-12-D00.

IX. References

1. Bakir, M. S. et al, “Sea of Leads Ultra-High-Density Compliant Wafer-Level Packaging Technology,” Proc 52ndElectronics and Components Technology Conference, May 2002.

2. The International Technology Roadmap for Semiconductors, SIA, 2001 version.

3. Bushnell, M. L. et al, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Kluwer Academic Publishers (Boston, 2000).

4. Patel, C. S., “Compliant Wafer-Level Package (CWLP),” Ph.D. Dissertation, Georgia Institute of Technology, May 2001.

5. Keezer, D. C. et al, “Electrical Test Strategies for a Wafer-Level Batch Packaging Technology,” Proc 51stElectronics and Components Technology Conference, pp 1019-1023, May 2001.

6. Keezer, D.C., et al, “Test Support Processors for Enhanced Testability of High Performance Circuits,” Proc. Intl. Test Conf., pp 801-809, Oct. 1999.

7. Zhou, Q., “Test Support Processors for Enhanced Testability of High Performance Circuits,” Ph.D. Dissertation, Georgia Institute of Technology, May 2001.