## Course Material for Inverter

### Chapter 5, 2nd ed.

**P = primair, I = Illustratie, O = overslaan**

**P 5.1 Introduction ** **180 **

**P 5.2 ** **The Static CMOS inverter - intuitive ** **181 – 184 **
**P 1.3.2 ** **Functionality and Robustness ** **18 – 27 **
**P 5.3 Evaluating the Robustness ... ** **184 – 191 **

**I 5.3.3 ** **Robustness Revisited ** **191 – 193 **

**P 1.3.3 ** **Performance ** **27 – 30 **

**I 5.4 ** **Performance of the CMOS inverter ** **193 – 213 **
**P 1.3.4 ** **Power and Energy Consumption ** **30 – 31 **

**I 5.5 ** **Power, Energy, and Energy-Delay ** **213 – 223 **
**O 5.5.2 ** **Static Consumption ** **223 – 225 **

**O 5.5.3 ** **Putting it All Together 225 – 227 **
**O 5.5.4 Analyzing Power Consumption using **

## SPICE

### 227 – 229. O 5.6 Perspective: Technology scaling… 229 – 231

## The CMOS Inverter - Outline

**First Glance**

**Digital Gate Characterization**

**Static Behavior (Robustness)**

**VTC **

**Switching Threshold**

**Noise Margins**

**Dynamic Behavior (Performance)**

**Capacitances**

**Delay**

**Power**

The CMOS Inverter:

A First Glance

**VDD**

**Vin**

_{V}**out**

**C**

_{L}CMOS Inverters (1)

**Polysilicon**

**In**

**Out****Metal1**

**VDD**

**GND****PMOS**

**NMOS**

**1.2**µ

**m**

**= 2**λ

CMOS Inverter Operation Principle

**1**

**0**

**0**

**1**

**V**

_{OH}**= V**

_{DD}**V**

_{OL}**= 0**

**§ 5.2**

Digital Gate Fundamental

Parameters

**Functionality**

**Reliability, Robustness**

**Area**

**Performance**

**Speed (delay)**

**Power Consumption**

**Energy**

The Ideal Inverter

V

_{in}g = -

∞

V

_{out}**R**∞

_{i }=**Ro = 0**

## Static CMOS Properties

### Basic inverter belongs to class of static

**circuits:** **output always connected to either **
**V _{DD}**

**or V**

_{SS}.**Not ideal but:**

**Rail to rail** **voltage swing**

**Ratio less** **design**

**Low output impedance**

**Extremely high input impedance**

**No static power** **dissipation**

**Good noise properties/margins**

**Exercise:** **prioritize the list above**

**V**_{in}* g = -*∞

## Voltage Transfer Characteristic (VTC)

Load Line (Ckt Theory)

**2.5V**

**0V**

**V**

_{GS}**R**

**A**

**B**

**Exercise:**

### The blue load line A corresponds to R = The orange load line B corresponds to R = With load line A and VGS = 1V, Vout = Draw a graph Vout(Vin) for load line A and B

**12.5k**Ω
**25k**Ω
**approx 1.6 V**
**0**
**0.5**
**1.0**
**1.5**
**2.0**
**2.5**
**0.5** **1.0** _{1.5}_{2.0}_{2.5}**V _{GS}**

**= 1.0V**

**V**

_{GS}**= 1.5V**

**V**

_{GS}**= 2.0V**

**V**

_{GS}**= 2.5V**

**V**

_{DS}**[V]**

**I**_{D}**[10-4**

_{A]}**V**

_{in}**Vout**

## PMOS Load Lines

**V**

_{DSp}**I**

_{Dp}**V**

_{GSp}=-5**V**

_{GSp}=-2**Kirchoff:**

**V**

_{in}**= V**

_{DD}**+ V**

_{GSp}**I**

_{Dn}**= - I**

_{Dp}**V**

_{out}**= V**

_{DD}**+ V**

_{DSp}**V**

_{out}**I**

_{Dn}**V =0**

**in**

**in**

**V =3**

**V**

_{out}**= V**

_{DD}**+ V**

_{DSp}### Goal: Combine IDn and IDp in one graph

**V _{in}**

**Vout**

**V**

_{DD}**V**

_{in}**= V**

_{DD}**+ V**

_{GSp}**V**

_{DSp}**I**

_{Dn}**V**

_{in}=0**V**

_{in}=3**Example: V**

_{DD}=5V**-+**

**V**

_{GSp}**+**

**-V**

_{DSp}**I**

_{Dp}**I**

_{Dn}## CMOS Inverter Load Characteristics

**In,p**

**Vin= 5**

**Vin= 4**

**Vin= 3**

**Vin= 0**

**Vin= 1**

**Vin= 2**

**NMOS**

**PMOS**

**V**

**in= 1**

**Vin= 2**

**Vin= 3**

**Vin= 4**

**Vin= 4**

**Vin= 5**

**Vin= 2**

**Vin= 3**

**V**

_{out}**Vin= 0**

**Vin= 1**

CMOS Inverter VTC

**V**

_{out}**V**

_{in}**1**

**2**

**3**

**4**

**5**

**12**

**3**

**4**

**5**

**I**

_{n,p}**V**

_{in}= 5**V**

_{in}= 4**V**

_{in}= 3**Vin= 0**

**V**

_{in}= 1**V**

_{in}= 2**NMOS**

**PMOS**

**V**

_{in}= 0**V**

_{in}= 1**V**

_{in}= 2**V**

_{in}= 3**V**

_{in}= 4**V**

_{in}= 4**V**

_{in}= 5**V**

_{in}= 2**V**

_{in}= 3**V**

_{out}NMOS Operating

Conditions

**V**

_{out}**= V**

_{in}**- V**↑

_{Tn}**V**

_{out}**V**

_{dd}**V**→

_{dd}**V**

_{in}**V**

_{Tn}**- V**

_{Tp}**V**

_{Tp}**1**

NMOS

**1**

**V**

_{in}**= V**

_{GS}**< V**⇒

_{Tn}**off**

**2**

**2**

**V**

_{out}**> V**

_{in}**- V**

_{Tn}**V**

_{DS}**> V**

_{GS}**- V**

_{Tn}**V**⇒

_{GD }< V_{Tn}**saturation**

**3**

**3**

**V**

_{out}**< V**

_{in}**- V**⇒

_{Tn}**resistive**

### Need to know for proper dimensioning, analysis of noise margin, etc.

## PMOS Operating

Conditions

**V**

_{out}**= V**

_{in}**- V**

_{Tp}**V**↑

_{dd}- |V_{Tp}|**V**

_{out}**V**

_{dd}**V**→

_{dd}**V**

_{in}**- V**

_{Tp}**V**

_{Tp}**4**

PMOS

**4**

**V**

_{in}**> V**

_{DD}**+ V**⇒

_{Tp}**off**

**5**

**5**

**V**

_{out}**< V**

_{in}**- V**⇒

_{Tp}**saturation**

**6**

**6**

**V**

_{out}**> V**

_{in}**- V**⇒

_{Tp}**resistive**

Exercise:

check

results for PMOS

### Need to know for proper dimensioning, analysis of noise margin, etc.

## Operating Conditions

**V**

_{out}**= V**

_{in}**- V**

_{Tp}**V**

_{out}**= V**

_{in}**- V**

_{Tn}**V**↑

_{dd}- |V_{Tp}|**V**

_{out}**V**

_{dd}**V**→

_{dd}**V**

_{in}**V**

_{Tn}**- V**

_{Tp}**V**

_{Tp}**1**

**NMOS 1 off**

**2 saturation**

**3 resistive**

**PMOS 4 off**

**5 saturation**

**6 resistive**

**2**

**3**

**4**

**5**

**6**

**Vout**

**V**

_{in}**1**

**2**

**3**

**4**

**5**

**1**

**23**

**45**

**NMOS lin**

**PMOS off**

**NMOS sat**

**PMOS sat**

**NMOS off**

**PMOS lin**

**NMOS sat**

**PMOS lin**

**NMOS lin**

**PMOS sat**

Inverter Static Behavior

Regeneration

Noise margins

Delay metrics

The Realistic Inverter

V

_{in}g = -

∞

V

_{out}**R**∞

_{i }=**Ro = 0**

**0**

**0.5**

**1.0**

**1.5**

**2.0**

**2.5**

**0.5**

**1.0**

_{1.5}

_{2.0}

_{2.5}**V**

_{IN}**[V]**

**V**

_{out}**[V]**

**Ideal Inverter**

**Realistic Inverter**

The Regenerative Property

### A chain of inverters

**The regenerative property**

**Regenerative **
**Property:** **ability to **
**regenerate (repair) **
**a weak signal in a **
**chain of gates**
**Ex. 1.4**

## The Regenerative Property (2)

### (a) A chain of inverters.

**v _{0}, v_{2}, ...**

**v**

_{1}, v_{3}, ...**v**

_{1}, v_{3}, ...**v**

_{0}, v_{2}, ...**(b) Regenerative gate**

**f(v)**

**finv(v)**

**finv(v)**

**f(v)**

**(c) Non-regenerative gate**

**v**

_{0}**v**

_{1}**v**

_{2}**v**

_{3}**v**

_{4}**v**

_{5}**v**

_{6}**...**

## The regenerative Property (3)

### Exercise: what is the output voltage of a chain of 4

**inverters with a piece-wise linear VTC passing through (0, **
**10), (4,8), (6,2) and (10,0) [Volt], as the result of an input **
**voltage of 5.5 [Volt].**

## Inverter Switching Treshold

Not the device threshold

Point of V

_{in}= V

_{out}**V**

_{out}**V**

_{in}

**V**_{m}**

**= f(R**_{onn}**, R**_{onp}**)****Try to set W**

_{n}, L_{n}, W_{p}, L_{p}**so that VTC is symmetric**

**as this will improve noise**

**margins**

**Symmetrical VTC **⇒ **V _{m}** ≈

**½ V**⇒

_{DD }**W**≈

_{p}/W_{n}Simulated Gate Switching Threshold

**In practice: choose somewhat smaller value of W _{p}/W_{n}**

**Why? **

### See Figure 5.7

3.5

**Save area with only slight asymmetry**

**Electrical Design Rule**

**W**_{p}

≈

**

**2.5 W**_{n}

**Assumes L**_{p}**

**= L**_{n}**Should be applied**

**consistently**

**W**

_{p}**/ W**

_{n}**V**

**M**

**(V)**

## Inverter Switching Threshold

Analytical Derivation

**V _{M}**

**is V**

_{in}**such that V**

_{in}**= V**

_{out} **V _{DS }= V_{GS}** ⇔

**V**

_{GD}**= 0**⇒

**saturation**

**Assume V _{DSAT}**

**< V**

_{M}**- V**

_{T }**(velocity saturation)**

**Ignore channel length modulation**

**V _{M}**

**follows from**

**I _{DSATn}(V_{M}) = - I_{DSATp}(V_{M}) **

Inverter Switching Threshold

Analytical Derivation (ctd)(

**V**

**V**

**V**

**/****2**

)

**kV***=*

**I**_{D}

_{DSAT}*−*

_{GS}*−*

_{T}

_{DSAT}*⇔*

**I**_{DSATn}**(V**_{M}**) = - I**_{DSATp}**(V**_{M}**)**(

(

)

)

**2**

**2**

**/**

**V**

**V**

**V**

**V**

**V**

**/**

**V**

**V**

**V**

**V**

**k**

**k**

**DSATp**

**Tp**

**DD**

**M**

**DSAT**

**DSATn**

**Tn**

**M**

**DSAT**

**n**

**p**

**P***− − − − − − =*

**n**(

)

(

**2**

)

**2**

**/**

**V**

**V**

**V**

**V**

**V**

**k**

**/**

**V**

**V**

**V**

**V**

**k**

**)**

**L**

**/**

**W**

**(**

**)**

**L**

**/**

**W**

**(**

**DSATp**

**Tp**

**DD**

**M**

**DSAT**

**'**

**p**

**DSATn**

**Tn**

**M**

**DSAT**

**'**

**n**

**n**

**p**

**P***− − − − − = ⇒*

**n**(

*−*

**V***−*

**V**

**V**

**/****2**

)

=

**V**

**k**_{n}

_{DSAT}

_{M}

_{Tn}

_{DSATn}

**n**(

**V**

**V**

**V**

**V**

**/****2**

)

**V**

**k**_{p}

_{DSAT}

_{M}

_{DD}

_{Tp}

_{DSATp}*− − − − ⇔*

**P**

**k**

**L**

**W***=*

**k****

**'****See Example 5.1:**

**(W/L)**_{p}**= 3.5 (W/L)**_{n}**for typical conditions and V**_{M}**= ½ V**_{DD}

Gate Switching Threshold

w/o Velocity Saturation

0.1 0.3 1.0 3.2 10.0
1.0
2.0
3.0
4.0
**kp/kn**
**V** **M**
**n****p****Tn****Tp****DD****k****k****r****with****r****)****V****V****V****(****r****V***_{M}* = −

_{+}+ = −

**1**

**Exercise (Problem 5.1):**

### derive VM for

**long-channel approximation **
**as shown below**

**Long channel approximation**

## Noise in Digital Integrated Circuits

*V _{DD}*

*v*(

*t*)

*i*(*t*)

(a) Inductive coupling (b) Capacitive coupling **(**c) Power and ground
noise

**Study behavior of static CMOS Gates with noisy **
**signals**

Noise Margins

**V _{OL }= Output Low Voltage**

**V _{IL}**

**= Input Low Voltage**

### VOH, VIH = …

## Noise Margins

**NM _{H }= V_{OH}**

**- V**

_{IH}**= High Noise Margin**

Noise Margin for Realistic Gates

Noise Margin Calculation

(

)

**g**

**V**

**g**

**V**

**V**

**V***−*

**V**_{IH}*= −*

_{IL}*−*

**OH***= −*

**OL**

**DD**

**g**

**V**

**V***=*

**V**_{IH}*−*

_{M}

**M**

**g**

**V**

**V**

**V***=*

**V**_{IL}*+*

_{M}*−*

**DD**

**M**

**IH**

**DD**

**H**

**V**

**V***= −*

**NM***=*

**NM**_{L}

**V**_{IL}**Piece-wise linear**

**approximation of**

**VTC**

**g = gain factor**

**(slope of VTC)**

**We know how**

**to compute V**_{M}**Next:**

**how to**

**compute g**

**§**

**5.3.2**

Noise Margin Calculation (2)

(

*−*

_{in}*−*

_{Tn}

_{DSATn})(

+

_{n}

_{out})

+

**DSAT**

**n****V**

**V**

**V**

**V**

**/**

**V**

**k**

**n****2**

**1**λ

(

*−*

_{in}*−*

_{DD}*−*

_{Tp}

_{DSATp}**2**

)(

**1**+

_{p}*−*

_{out}

_{p}

_{DD})

=**0**

**DSAT**

**p****V**

**V**

**V**

**V**

**V**

**/**

**V**

**V**

**k***λ λ*

**P**(

_{M}

_{T}

_{DSATp})(

_{n}

_{p})

**V**

**V**

**in**

**out**

**/**

**V**

**V**

**V**

**r**

**dV**

**dV**

**g**

**M***− − λ − λ + ≈ = =*

**in****2**

**1**

**Mostly determined by technology**

**See example 5.2**

**Exercise:** **verify calculation**

**Exercise:** **explain why we add channel length **
**modulation to the I**_{D}**expressions (we did not do **
**this to determine V**_{M}**)**

**Approximate g as the slope in V**_{out}**vs. V**_{in}**at V**_{in}**= V**_{M}

**DSATn****n****DSATp****p****V****k****V****k*** r* =

## Dynamic Behavior (Performance)

Capacitances

Delay

**But: we take much simpler model for **
**capacitances compared to book.**

**See the syllabus.**

**§ 5.4.1 of book is only illustration.**

CMOS Inverters

**Polysilicon**

**In**

**Out****Metal1**

**VDD**

**GND****PMOS**

**NMOS**

**1.2**µ

**m**

**=2**λ

**What causes the **

### delay?

**What is ****R**_{on }**?**

**Where are the **

**capacitances?**

**Which **

**capacitances **
**determine ****T**_{p}**?**

## Delay Definitions

**§ 1.3.3**

(

**pHL**

**pLH**)

**p**

**t**

**t***= +*

**t****2**

**1**

**t**

**pHL**

**t****pLH**

**t**

**t**

**V**_{in}

**V**_{out}**50%**

**50%**

**t**_{r}**10%**

**90%**

**t**_{f}

**t**

**pHL**

**t****pLH**

**t**

**t**

**V**_{in}

**V**_{out}**50%**

**50%**

**t**_{r}**10%**

**90%**

**t**_{f}

**t**_{p}**:**

**property of gate**

**t**_{r}

**, t**_{f}**: property of signal**

CMOS Inverter Rise/Fall Delay

**Goal: determine t _{f}, t_{r}**

**and t**

_{p} **First: compute relevant capacitances**

**Second: determine equivalent R _{on}**

**Third: compute RC delay (**τ**) and scale result**

**Assume:** **ideal source, step input**

**t**_{f}

**0**

=

Modeling

**t**_{f}**0**=

**t****G**

**D**

**S**

**R**

_{on}**C**

_{G}**C**

_{S}**C**

_{D}**t=0**

**0**=

**t**

**t**_{f}**M**

_{1}**M**

_{2}**M**

_{3}**M**

_{4}**D**

**S**

**G**

Modeling (2)

**0**=

**t**

**t**_{f}

**+**

**-V**_{s}

**R**

**t=0**

**C****R = R**

_{on1}**C = C**

_{D1}**+ C**

_{D2}**+ C**

_{G3}**+ C**

_{G4}**V**

_{S}**= 0**

**0**=

**t**

**t**_{f}**M**

_{1}**M**

_{2}**M**

_{3}**M**

_{4}

**t**_{f}Modeling (3)

**t**_{f}**0**=

**t**

**+**

**-V**_{s}

**R**

**t=0**

**C**

**t**_{f} **Delay can be modeled using RC circuit**

**First order simplified model**

**R is (linearized) on-resistance of active transistor**

**C is sum of (linearized) C’s that are switched**

**Typically, C _{G}**

**of driven gate, C**

_{D}**of driving gate**

**Plus relevant interconnect C**

**Might need to include interconnect R in model **

**V _{s}**

**is final voltage of delay node (initial voltage determined**

**by previous state)**

( )

**(**

**0)/**τ

**0**

**(**

**))**

**(**

**)**

**(**

**)**

**(**

_{c}

_{c}

_{c}

**t**

**t**

**c**

**t**

**v**

**v**

**t**

**v**

**e***= ∞ + − ∞ − −*

**v**

**+**

**-V**_{s}

**R**

**t=0**

**C**

**v****C****+**

**-+**

**v****R**

**-0.5V**_{s}

**V**_{s}**2RC**

**4RC**

**6RC**

**8RC**

**v**_{C}

**t****0**

**0.5V**_{s}

**V**_{s}**2RC**

**4RC**

**6RC**

**8RC**

**v**_{C}

**t****0**

**)**

**e**

**(**

**V**

**v**

**RC**

**t**

**s***− − =*

**c****1**

**c**

**s**

**c**

_{V}

_{v}

**dt**

**dv***= −*

**RC**## RC Delay Review (1)

**)****e****(****V****v**_{t}_{/}**s****c**_{=} _{1}_{−} − τ

**Response can be normalized** **with respect to **

τ

**=RC**### and VS = vC(t =

∞

**)**

**)**

**e**

**(**

**V**

**v**

**RC**

**t**

**s***− − =*

**c****1**

**8**τ

**0.5**

**1.0**

**2**τ

**4**τ

**6**τ

**s**

**c**

**V**

**v****0**

**t****Each **τ**-step gives 63%**

**of remaining swing**
**0.95**
**0.98 0.99**
**0.63**
**0.86**
**t** **=0.69**τ
**Example: (1**− * e*−

**2)**=

**0**

**.****86**

**2.3**

τ

**0–90%**

**2.2**

τ

**10%–90%**

**1.0**

τ

**0–63%**

**0.69**

τ

**0–50%**

**time**

**swing**

## RC Delay Review (2)

**???**

Inverter Propagation Delay Summary

**out**C

C

_{W}C

_{in}

**L**C

**L**

**eqp**

**pLH**

**R**

**C***=*

**t****0.69**

**L**

**eqn**

**pHL**

**R**

**C***=*

**t****0.69**

(

**pHL**

**pLH**)

**p**

**t**

**t***= +*

**t****2**

**1**

**Propagation time**

**R**_{eq}Propagation Delay w. Wire Resistance

**)**

**5**

**.**

**0**

**(**

**69**

**.**

**0**

_{eqn}

_{out}

_{w}

**PHL**

**R**

**C**

**C***= +*

**t**

**R**_{eq}

**out**

**C**

**C****W**

**C**_{in}

**W**

**R****)**

**5**

**.**

**0**

**)(**

**(**

**69**

**.**

**0**

*+*

**R**_{eqn}

**R**_{W}*+*

**C**_{w}*+*

**C**_{in}Equivalent R

_{on }

(R

_{eq}

)

**I**

_{D}**V**

_{DD}**(a) Schematic**=

**eq**

**R**(

)

(

)

**2**

**+**

**1**

**2**

**+**

**+**

**1**

**2**

**1**

**DD**

**DSAT**

**DD**

**DD**

**DSAT**

**DD**

**V**

**I**

**V**

**V**

**I***λ λ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ≈*

**V**

_{DD}

**DSAT**

**DD**

_{V}

**6**

**5**

**-1**

**I**

**V**

**4**

**3**_{λ}

Impact of Rise Time on Delay

**tpH**

**L**

**(n**

**s**

**e**

**c**

**)**

**0.35**

**0.3**

**0.25**

**0.2**

**0.15**

**t**

_{rise}(nsec)**1**

**0.8**

**0.6**

**0.4**

**0.2**

**0**

**Empirical from**

### the first edition of book

## Delay as a function of V

_{DD}

**0.8**

**1**

**1.2 1.4 1.6 1.8**

**2**

**2.2 2.4**

**1**

**1.5**

**2**

**2.5**

**3**

**3.5**

**4**

**4.5**

**5**

**5.5**

**V**

_{DD}**(V)**

**t**

**p****(Normalized)**

**Fg.5.17**

CMOS Inverter Propagation Delay

**V**

_{DD}**V**

_{out}**V**

_{in}= V_{DD}**CL**

**I**

_{av}**)**

**4**

**3**

**1**

**(**

**2**

**2**

**DD**

**DSAT**

**DD**

**L**

**av**

**swing**

**L**

**pHL**

**V**

**I**

**V**

**C**

**I**

**V**

**C***λ + ≈ =*

**T**### Exercise (Problem 5.4): Derive the expression above

**Alternative current-based **
**estimate for T**_{p, }**assuming **
**velocity saturation**

## Ring Oscillator

**T= 2 x T**_{p}**x N **

⇔

**T**_{p}

**= T/2N**### Exercise: explain the factor 2 in the expression above Frequently used to obtain Tp by measurement (or simulation)

**N:** **number of inverters**
**T _{p}:**

**propagation delay**

**T:**

**period of oscillation**

**v**

_{0}**v1**

**v2**

**v3**

**v4**

**v5**

**v0**

**v1**

**§ 1.3.3**

## Fan-in and Fan-out

**N**

**M**

**(a) Fan-out N**

**(b) Fan-in M****§ 1.3.2**

Power (§ 5.5)

Dynamic Power

Static Power

CMOS Power Dissipation

**Power dissipation is a very important** **circuit **
**characteristic**

**CMOS has relatively low static dissipation**

**Power dissipation was the reason that CMOS **
**technology won over bipolar and NMOS **

### technology for digital IC’s

**(Extremely) high clock frequencies increase **
**dynamic dissipation**

**Low V _{T}**

**increase leakage**

**Advanced IC design is a continuous struggle to **
**contain the power requirements!**

## Power Density

### Estimate

**Furnace: 2000 Watt, r=10cm **Î **P **≈ **6Watt/cm2**
**Processor chip: 100 Watt, 3cm2 **Î ** _{P }**≈

_{33Watt/cm}2**Power-aware design, design for low power, is **
**blossoming subfield of VLSI Design**

## Where Does Power Go in CMOS

**Dynamic Power Consumption**

### Charging and discharging capacitors

**Short Circuit Currents**

**Short circuit path between supply rails during **
**switching**

**Leakage**

**Leaking diodes and transistors**

## Dynamic Power

### Dynamic Power

**E**_{i}**= energy of switching event i **

**(to first order) independent of switching speed**

**depends on process, layout **

**Power = Energy/Time **
∑
=
**i****i****E****T****P****1**
**E**_{i}**= Power-Delay-Product P-D **

**important quality measure**

**Energy-Delay-Product E-D**

## Low-to-High Transition Energy

**C**

### v0(t) vDD

**i(t)**

**Equivalent circuit for **
**low-to-high transition**
**E**_{C }**- Energy stored on C**
∫
= ∞
**0**
**0****dt****iv****E**_{C}

v

_{0}=

v

_{0}(

t

)

**dt**

**dv**

**C**

**t**

**i***=*

**i****(**

**)**=

**0**∫ = ∞

**0**

**0**

**0**

**dt**

**dt**

**dv***∫ =*

**Cv**

**V****DD****Cv**

_{0}

**dv**

_{0}

**DD**

**V**

**Cv**

_{0}2**1**=

**1**

**2**

**DD***=*

**CV**## Low-to-High Transition Energy

**C**

**v**

_{0}(t)**v**

_{DD}**i(t)**

**DD**

**V**### E Energy delivered by supply

( )

**t**

**V**

**dt**

**i**

**E**_{V}

_{DD}*∫ ∞ =*

**DD****0**∫ =

**V****DD**

_{DD}

**dt**

**dt**

**dv**

**CV****0**

**0**

**2**

**DD***=*

**CV****2**

**2**

**2**

**1**

**DD**

**c**

**DD**

**V**

**CV**

**E**

**CV**

**E***= =*

**DD**## Low-to-High Transition Energy

**C**

**v**

_{0}(t)**v**

_{DD}**i(t)**

**diss**### E Energy dissipated in transistor

(

**V**

**v**)

**dt**

**i***∫*

**E**_{diss}*∞ − =*

_{DD}**0**

**0**∫ ∫ ∞ ∞ − =

**0**

**0**

**0**

**dt**

**iv**

**dt**

**iV**_{DD}

**c**

**V**

**E**

**E***− =*

**DD**## High-to-Low Transition Energy

Equivalent circuit

**C**

**i**

### Exercise: Show that the energy that is dissipated in the transistor upon discharging C from VDD to 0 equals Ediss = ½CVDD2

## CMOS Dynamic Power Dissipation

**time**

**s**

**transition**

**#**

**transition**

**Energy**

**Time**

**Energy***= = ×*

**Power**

**f***× =*

**CV**_{DD}**2**

**Independent of transistor on-resistances**

**Can only reduce C, V**_{DD}**or f to reduce power**

**In this formula, f accounts for switching activity****(not necessarily a simple regular waveform)**

Summary

**First Glance**

**Digital Gate Characterization (§ 1.3)**

**Static Behavior (Robustness) (§ 5.3)**

**VTC **

**Switching Threshold**

**Noise Margins**

**Dynamic Behavior (Performance) (§ 5.4)**

**Capacitances**

**Delay**

**Power (§ 5.5)**