Getting started with Nuvoton NUC140 32-bit ARM cortex-M0 Microcontroller.pdf

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7/7/2016

Getting started with Nuvoton NUC140 32-bit ARM cortex-M0 Microcontroller

This blog presents articles on using KEIL and getting started with Nuvoton's NUC140 series 32 bit ARM cortex-M0

Microcontrollers. All these articles are based on Nuvoton's NUC140 EVM board. These articles are aimed at

helping/tutoring and sharing technical articles on programming the 32 bit microcontroller from Nuvoton. Please share

your comments and suggestions, if any (politely). The idea of this blog is learn from sharing knowledge so everyone can

benefit.

Getting started with Nuvoton

NUC140 32-bit ARM cortex-M0

Microcontroller

Wednesday, July 30, 2014 Wednesday, July 30, 2014

Know your chip on NUC140 EVM board

The highlights of the NUC140 chip on the learning board: The highlights of the NUC140 chip on the learning board:

1. Maximum supported CPU frequency via PLL is 50Mhz. 2. Maximum supported CPU frequency via external crystal is 24Mhz

3. Has inbuilt RTC with crystal of value 32.768Khz soldered to the learning board. 4. It can also run out of internal oscillator value of 22.1184Mhz.

5. Know your NUC140 series on your Learning board (EVM) of Nuvoton. The CPU name is NUC140VE3AN*.

NUC series in Nuvoton means it is a 32 bit microcontroller series. 1 in letter 140 means: It has 1 core only i.e. Cortex M0. 4 in letter 140 means: It belongs to the connectivity range. 0 in letter 140 currently does not hold any specific meaning. V in VE3AN means: LQFP100 package

E in VE3AN means: 128KB APROM size 3 in VE3AN means: 16KB RAM size

A in VE3AN is reserved for future feature additions/revisions

N in VE3AN means: temperature range supported by chip is: -40C to +85C. The chip is based on ARM v6-M architecture.

8. It has 128KB for Program FLASH, 16KB for SRAM, 4KB Data flash and 4KB of LDROM (bootloader) and 76 IOs.

9. The page erase size of the dataflash is 512 bytes. 10. It has an inbuilt 12 bit resolution SAR ADC.

11. It has an inbuilt temperature sensor with an accuracy of +/-1 degree. 12. For the automotive line, it has support for BOSCH CAN 2.0 A/B and LIN support. 13. It has 4-32bit timers, 3-UARTs, 4-SPI channels, 2-I2C channels, 1-2.0v full-speed USB. 14.It has 8-16bit PWM channels and 2-Analog Comparators and 1-12S/AC97.

*There are other versions of NUC140 also available as per this ordering mechanism:

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7/7/2016

Getting started with Nuvoton NUC140 32-bit ARM cortex-M0 Microcontroller

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Labels:32-bit ARM CortexM0,NUC140

Location: Ahmedabad, Gujarat, India

The nested vectored interrupt controller (NVIC) supports tail-chaining and late-arrival to assist in developing true real time embedded applications.

Tail chaining

Tail chaining is a method where the ISR, when it has executed and is about to return back to t he main method and is in the process of restoring the state of the registers, if during that period another ISR occurs then the overhead of restoring and saving of the state is reduced by directly allowing the NVIC to jump from one ISR to the other and there by saving time in ISR overheads.

Late-arrival

Late-arrivalis a method where when one ISR is about to get executed (but not started), if another higher priority ISR fires then the NVIC allows the higher priority ISR to execute first there by eliminating any delay to allow the most highest priority ISR to execute.

It is very im

It is very im portant to understportant to understand the and the variety of clock options provided by the variety of clock options provided by the controcontrollelle r r which clocks the various peripherals. It is hence important to understand the clock which clocks the various peripherals. It is hence important to understand the clock options t

options to calculao calcula te the te the clock sclock signal ignal timings.timings. NU

NUC140 HC140 H ardwardw are chip ordeare chip orde ring options as ring options as provided by Nuvotonprovided by Nuvoton

The CLOCK CONTROLLER of this chip:

Recommend this on Google

Monday, March 31, 2014 Monday, March 31, 2014

Embedded World's - Hello World - Toggling the GPIO.

Coding conventions

Coding conventions followed followed in CMSIS:in CMSIS:

1. All t he da ta ty pes use d in CMSIS is base d out of stdint .h file. Data st ruc ture s for c or e registers are defined in the CMSIS header core_cm0.h file.

2.The core registers, peripheral registers and the CPU instructions follow capital naming co nve ntion. Eg: NVI C->ISER[0], GPIOA->ISRC,

3.Peripheral access functions and interrupts use camel casing convention. Eg: DrvGPIO_Open().

4.CMSIS allows C++ like comme nting method (eg: // this is used for comme nting.)

Finally, we are there on the

Finally, we are there on the main subject main subject : Getting started!: Getting started! So let us atte mpt to wr ite our first exa mple for to ggling GPIO (Embedde d world's "HELLO World" using Keil. I t shou ld be st raigh t forwa rd po rt for IA R and othe r to ol c hains, I guess

though I cannot co mment on that much since I have not had an experience using them f or this controller.

Understanding the NU-LB-NUC140 board for the LED experiment: Understanding the NU-LB-NUC140 board for the LED experiment:

The chip used on this EVM board is NUC140VE3CN. This board is powered by an external 12MHz crystal as well as 32.768Khz c rystal for RTC applications. In this experiment we will att empt our first "Hello World" program by lighting up the LED for sometime and switching it off and continue doing that. The LEDs on this EVM board are connected on GPIO-PortC on pins -12,13,14 & 15. These LEDs are connected in SINK mode. Hence to turn on a LED you must place a ZERO on the GPIO pin and to switch off you must place a ONE.

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Getting started with Nuvoton NUC140 32-bit ARM cortex-M0 Microcontroller

NUC140 has 80 general purpose IOs.

80 IOs are arranged in GPIOA, GPIOB, GPIOC, GPIOD, GPIOE. On reset all IO pins stay in Quasi-Bidirectional mode. IOs as outputs c an support s ource/sink capability. First Step: Creating your project in

First Step: Creating your project in KEKEIL:IL:

1.Open KEIL -> New uVision Project -> <Select your custom folder> <select t he chip as NUC140VE3CN.

2.If asked for adding the startup file, please add to the project.

3.For simplicity, click on "File Extensions" icon in KEIL and create two sub folders apart from source files folder. Name them as "Library" and "CMSIS" files. Move the files "startup_NUC1xx.s" to "CMSIS" folder. Open the "File Extensions" folder and add "startup_NUC1xx.c" and "core_cm0.c" files into the "CMSIS" folder.

1.The "core_cm0.c" file is found in the location <systemInstalledDrive>:\Nuvoton\BSP Library\NUC100SeriesBSP_CMSIS_v1.05.003\CMSIS\CM0\CoreSupport. 2.The "startup_NUC1xx.c" file is found in the location:

<systemInstalledDrive>:\Nuvoton\BSP

Library\NUC100SeriesBSP_CMSIS_v1.05.003\CMSIS\CM0\DeviceSupport\Nuvoton\ NUC1xx

4. Add a main_gpio.c file to the "Source Files" folder. This is where your main() function will reside and do all the necessary work.

5. As we studied in the earlier sections of CMSIS article, we will be using the library provided Nuvoton to program the GPIOs via the nuvoton library wrapper for easy portability rather than directly fiddling with the hardware registers. (Though it is perfectly fine if you wish to directly fiddle around the hardware registers like you do for the conventional 8-bit microcontrollers. I am using the Nuvoton library wrapper approach.

6.Since in this example we are going to set the GPIOs, we will first include the GPIO library wrapper provided by Nuvoton by the name "DrvGPIO.c". This file is found in the location: <systemInstalledDrive>:\Nuvoton\BSP

Library\NUC100SeriesBSP_CMSIS_v1.05.003\NuvotonPlatform_Keil\Src\Driver\ 7.Since the clock control is handled by the file "DrvSYS.c". This file should also be included

similar to t he "DrvGPIO.c".

8.It is important to let Keil's project settings know where your include library and core_cm0 headers files reside. Hence add the include paths by clicking on options for the project settings >> C/C++ >> Include Paths and give the following paths in the following order:

./ ../../../CMSIS/CM0/CoreSupport ../../../CMSIS/CM0/DeviceSupport/Nuvoton/NUC1xx ../../../Include ../../../Include/Driver ../../../Include/NUC1xx-LB_002

9.Then select in options for project settings >> Linker and add "map

--first='startup_NUC1xx.o(RESET)' --datacompressor=off --info=inline --entry Reset_Handler" to Misc controls. Also untick "Use Memory Layout from target Dialog". (refer:

http://www.keil.com/support/man/docs/uv4/uv4_dg_adsld.htm)

10.One more setting to go, under Users, set "Run User Programs After build/rebuild" 1.Under Run1: Tick Run1 checkbox and argument as: fromelf bin ".\obj\@L.axf"

--output ".\ obj\@L.bin"

2.Under Run2: Tick Run2 checkbox and argument as: fromelf text -c ".\obj\@L.axf" --output ".\obj\@L.txt"

11.Create a folder as obj in the working directory and select this folder for your output dump in Keil's project settings.

12.Now let us get to the action.

To set up the chip, first you need to select the clock input to your chip. In this case it could you either internal oscillator or external crystal or PLL clock as per these configs:

E_SYS_CHIP_CLKSRC

Enumeration_identifier Value Description

E_SYS_XTL12M 0 Select External 12M Crystal

E_SYS_XTL32K 1 Select External 32K Crystal

E_SYS_OSC22M 2 Select Internal 22M Oscillator

E_SYS_OSC10K 3 Select Internal 10K Oscillator

E_SYS_PLL 4 Select PLL clock

Here is the main program: Here is the main program:

#include "NUC1xx.h" #include "Driver\DrvSYS.h" #include "Driver\DrvGPIO.h" void delay_loop(void) { uint32_t i,j; for(i=0;i<10;i++) { for(j=0;j<60000;j++); }

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Getting started with Nuvoton NUC140 32-bit ARM cortex-M0 Microcontroller

} int main(void) {

//First set the clock input to the processor. //The choices are internal clock or external crystal. /* Unlock the protected registers */

UNLOCKREG();

//We will use the internal 22.1184Mhz

DrvSYS_SetOscCtrl(E_SYS_OSC22M,1);

//wait till the clock is stable

while (DrvSYS_GetChipClockSourceStatus(E_SYS_OSC22M) != 1);

/* HCLK clock source. 0: ext ernal 12MHz; 7:internal 22MHz RC oscillator */

DrvSYS_SelectHCLKSource(7);

/*lock the protected registers */

LOCKREG();

/* HCLK clock frequency = HCLK clock source / (HCLK_N + 1) */ /* Max divisor value: 0b1111 and min value: 0b0000 */

DrvSYS_SetClockDivider(E_SYS_HCLK_DIV, 0);

//Configure GPIO - GPC- pin 12 as output port pin. LEDS are connected on 12, 13, 14, 15.

DrvGPIO_Open(E_GPC, 12, E_IO_OUTPUT); while(1) { DrvGPIO_SetBit(E_GPC,12); delay_loop(); DrvGPIO_ClrBit(E_GPC,12); delay_loop(); } }

Compile, build and burn the hex file using Nuvoton's ICP programming tool and see the led blinking. You can burn either the .hex file or the .bin file on the EVM board and check your program.

Slight Tweaks for replacing the delay_loop()

Slight Tweaks for replacing the delay_loop() :Exploring SysExploring System Tick tem Tick - a 24bit - a 24bit Timer Timer available on ARM CortexM0.

available on ARM CortexM0.

SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counte r with a flexib le contro l mechanism. It compr ises of SY ST_CVR, SYST_RVR and SY ST_CSR registe rs.

SYST_CVR is the Current V alue Register while SY ST_RVR is the Reload Value Register.

SYST_CSR is the Systick timer control and status register.

Systick uses either the same CORE_CPU clock or any of the external clock. To use the CORE_CPU clock, the value of bit named CLKSRC in SYST_CSR should be "ONE".

If CLKSRC in SYST_CSR is "ZERO" then ba sed on STCLK_S in CLKSEL0 re giste r decides the exter nal clock speed to be used for SYSTIC K timer.

To replace the abov e delay_loop() , we made a new fun ction: void systemDelay(void) //1 sec delay if running out of 12Mhz. {

//Considering 1tick = 12Mhz so for 1 sec, reload value = 12000000.

SysTick->LOAD = 12000000; //Reload value in register for SysTick for 1 sec delay SysTick->VAL = (0x000000); //default value of SysTick Current value register.

//Switch on sysTick timer.

//Sys tem Clock source is (optional) external reference clock SysTick->CTRL = (1<<SysTick_CTRL_ENABLE_Pos); /* Waiting for down-count to zero . 16th bit in SYST_CSR */ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0); }

One more important point to remember: One more important point to remember:

You cannot have systick timer source using a different clock source as compared to the main system clock even though it is configurable. Meaning, if your CPU clock is out of external crystal then you cannot select your systick to be coming out internal oscillator at the same time, when I experimented on this board. (I thought it should be possible!). Same way, if you ran the CPU over internal oscillator then trying to run the systick timer clock to be running out of external crystal does not work.

I decided to use pre-processor directive for this reason as shown below. This code should be part of the protected register write along with setting the CPU clock.

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Getting started with Nuvoton NUC140 32-bit ARM cortex-M0 Microcontroller

CMSIS files for Nuvoton's NUC 140

Contents of the CMSIS file structure: Contents of the CMSIS file structure:

core_cm0.h :contains cortex-M0's global declarations & definitions as well as static function definitions.

core_cm0.c : contains cortex-M0's global definitions.

<device.h> [in this case: NUC 1x x.h] : Top level dev ice specific header file containing device specific bit definitions and structure/union definitions. This file includes core_cm0.h and system_NUC1xx.h files. This file should be included while wr iting app lica tio n co de.

syste m_<device >.h [in this case system_NUC 1x x.h] :This file contains device specifi c declarations.

system_< device>.c [in this case system_NU C1xx.c ] : This file contains device specific definitions like SystemCoreClockUpdate() and systemInit() calls.

Exploring the NUC1xx.h file : Exploring the NUC1xx.h file :

In this fil e, the parameter _MP U Present 0 indicates there is no memo ry prot ect ion unit while the other parame ter __NVI C_PRIO_BITS 2 informs the user that there can be maximum 2 priority bits to set.

The __Vendor_SysTickConfig defined parameter has the default setting as 0. When this mac ro is set to 1 , the Sys TickCo nfig() func tio n in the co re_c m0 .h is

excluded. If it is set to 1 then in that case file <device>.h [here NUC1xx.h] must contain a v endor [Nuvoto n] specific implementati on of this fu nction.

Compiler support built

Compiler support built into CMSIS:into CMSIS:Currentl y three main compilers are supported by CMSIS namely, armgcc from ARM REAL view, icc arm from IA R EWARM and gcc from GNU compiler collection. All the functi ons in the core peripheral access layer are reentrant and can be called from different interrupt service routines. The exception handers are given a suffix __Handler while the ex ternal interr upt handlers are given a suffix __IRQ Handler.

What is CMSIS?

CMSIS is an acrony m for

C

Cortex

Microcontroller

M

S

oftware

II

nterface

S

tandard.

CMSIS

CMSIS is an abstract layer that supports dev elopers and vendors in creating reusable software co mponents for ARM C ortex -M based systems. This layer is useable for Cortex-M0,M0+, M1 M3/M4 layers as well.

A brief glance into Cortex-M0,M0+, M1, M3 and M4 architectures: A brief glance into Cortex-M0,M0+, M1, M3 and M4 architectures:

Cortex-M0:

Cortex-M0:The ARM Cortex™-M0 processor is the smallest ARM processor available. The exceptionally small silicon area, low power and minimal code footprint of the processor enables developers to achieve 32-bit performance at

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Getting started with Nuvoton NUC140 32-bit ARM cortex-M0 Microcontroller

an 8-bit price point.

Supports 3-stage pipeline, thumb2, hardware-single-cycle (32x32) multip ly hardware.

Supports 1 NMI and 32 physical interrupts.

Has only 56 instructions and has 'C-friendly' architecture. Cortex-M0+:

Cortex-M0+:The ARM Cortex™-M0+ processor is an adaption of Cortex-M0 but with mo re im pro ve d per form ance and re duc ed ene rgy foot print .

Supports 2-stage pipeline, thumb2, hardware-single-cycle(32x32) multip ly hardware.

Cortex-M1:

Cortex-M1: The ARM Cortex™-M1 processor is the first ARM processor designed specifically for implementation in FPGAs.

Supports 3-stage pipeline, thumb2 and big & little endian configuration.

Cortex-M3:

Cortex-M3:The ARM Cortex™-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applicati ons, specifically deve loped to enable partners to develop high-performance low-cost platforms for a broad range of devices including mi croco ntrollers, automotive body systems, indus trial control systems and wireless networking and sensors.

The Cortex-M3 NVIC is highly configurable at design time to deliver up to 240 system interrupts with indi vidual priorities, dynamic reprioritizati on and integrated sy stem clock.

Supports 1 NMI and 240 physical interrupts w ith 8 to 256 level priorities.

Supports hardware div ide, singl e c ycle-multiply and saturated math support.

Cortex-M4:

Cortex-M4:The ARM Cortex™-M 4 processor is the lates t embedded processor by ARM spec ifical ly dev elo ped to addr ess digita l signal co ntro l marke ts that

demand an efficient, easy-to-use blend of control and signal processing capabilities.

Supports 3-stage pipeline with branch prediction and thumb2. Supports hardware-divide, 8/16 bit SIMD arithmetic. Supports single precision floating point unit.

Supports Memory protection unit and deterministic operations.

Cont

Continuing further on inuing further on CMSIS:CMSIS:

In order to reduce cost and software complexity and the fact that there are too rapid changes on the technology front, CMSIS provides a uniform hardware abstraction layer that governs the way we write and debug software by ensuring software re-useability.

CMSIS structure consists of three layers: 1.Core peripheral Access Layer (CPAL) 2.Middleware Access Layer (MAL) 3.Device peripheral Access Layer (DPAL)

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Getting started with Nuvoton NUC140 32-bit ARM cortex-M0 Microcontroller

Posted byRohitat2:27 PM No comments:

Labels:CMSIS,Know ing CMSIS

Functionality of each CMSIS layer:

Core Perip

Core Perip heral Accheral Acc ess Layer:ess Layer:This layer is prov ided by A RM.The lowest level defines addresses, and access methods for common c omponents and fun ctionality that ex ists in every Cortex-M s ystem. Ac cess to core registers, N VIC, debug subsystem is p rov ided by this layer.

Middleware Access Layer:

Middleware Access Layer:This layer is defined by ARM, but is also adapted by silicon vendors for their respective devices.The Middleware Access Layer defines a common API for accessing peripherals.

Device Peripheral Access Layer:

Device Peripheral Access Layer:This layer is provided by the silicon vendor and contains the hardware regi ster addresses and other device specific access functions.

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