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Interactive Voice Response System With Microcontroller (IVRS) Aim:
To implement the (IVRS) Interactive Voice Response System using a microcontroller under the VB platform.
Description:
In This Project Some Predefined audio chunks are stored in the PC. When we call to the IVRS mobile number and when the call is established, we can now here the welcome voice and few options by hearing which we can select the appropriate option by pressing the corresponding key. Hence DTMF tones will be transferred to calling mobile to the called mobile and to the PC via serial communication. A front end VB software comes into picture now, which will analyze the corresponding tone received and plays back the respective prerecorded audio message through loud speaker. In this manner the voice response system does its operation of responding to the selected options
So by using IVRS TECHNOLOGY in college, the parents can know their children‘s details like attendance, marks etc
Visual basic is one of the good user interface platform and easier to understand and simple to Implement in nature. Visual Basic is a programming language that is designed especially for windows programming. First user has to develop the required code in VB. Then interface it with AT89S52 microcontroller which again programmed to control the devices or any electrical appliances. This is an interesting project which uses AT89S52 microcontroller as its brain.
This project uses regulated 5V, 500mA power supply. Unregulated 12V DC is used for relay.7805 three terminal voltage regulator is used for voltage regulation.
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Bridge type full wave rectifier is used to rectify the ac output of secondary of 230/12V step down transformer.
Block diagram:
Software’s used: Hardware’s used:
1) Keil. 1) AT89S52.
2) Proteus. 2) D.T.M.F Module.
3) Top win 3) Speaker. 4) Power supply. 5) P.C 6) Max 232
MOBILE
AT89S52
MOBILE
POWER SUPPLY MAX 232 D.T.M.F MODULE P.C SPEAKER3 SCHEMATIC DIAGRAM:
4 EMBEDDED SYSTEMS
Introduction:
An embedded system is a system which is going to do a predefined specified task is the embedded system and is even defined as combination of both software and hardware. A general-purpose definition of embedded systems is that they are devices used to control, monitor or assist the operation of equipment, machinery or plant. "Embedded" reflects the fact that they are an integral part of the system. At the other extreme a general-purpose computer may be used to control the operation of a large complex processing plant, and its presence will be obvious.
All embedded systems are including computers or microprocessors. Some of these computers are however very simple systems as compared with a personal computer. The very simplest embedded systems are capable of performing only a single function or set of functions to meet a single predetermined purpose. In more complex systems an application program that enables the embedded system to be used for a particular purpose in a specific application determines the functioning of the embedded system. The ability to have programs means that the same embedded system can be used for a variety of different purposes. In some cases a microprocessor may be designed in such a way that application software for a particular purpose can be added to the basic software in a second process, after which it is not possible to make further changes. The applications software on such processors is sometimes referred to as firmware.
The simplest devices consist of a single microprocessor (often called a "chip‖), which may itself be packaged with other chips in a hybrid system or Application Specific Integrated Circuit (ASIC). Its input comes from a detector or sensor and its output goes to a switch or activator which (for example) may start or stop the
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operation of a machine or, by operating a valve, may control the flow of fuel to an engine.
As the embedded system is the combination of both software and hardware
Figure: Block diagram of Embedded System
Software deals with the languages like ALP, C, and VB etc., and Hardware deals with Processors, Peripherals, and Memory.
Memory: It is used to store data or address.
Peripherals: These are the external devices connected Processor: It is an IC which is used to perform some task Applications of embedded systems
Manufacturing and process control Construction industry
Transport
Buildings and premises Domestic service Communications Software Hardware o ALP o C o VB Etc., o Processor o Peripherals o memory Embedded System
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Office systems and mobile equipment Banking, finance and commercial
Medical diagnostics, monitoring and life support Testing, monitoring and diagnostic systems
Processors are classified into four types like: Micro Processor (µp)
Micro controller (µc)
Digital Signal Processor (DSP)
Application Specific Integrated Circuits (ASIC) Micro Processor (µp):
A silicon chip that contains a CPU. In the world of personal computers, the terms microprocessor and CPU are used interchangeably. At the heart of all personal computers and most workstations sits a microprocessor. Microprocessors also control the logic of almost all digital devices, from clock radios to fuel-injection systems for automobiles.
Three basic characteristics differentiate microprocessors:
Instruction set: The set of instructions that the microprocessor can execute. Bandwidth : The number of bits processed in a single instruction.
Clock speed : Given in megahertz (MHz), the clock speed determines how many instructions per second the processor can execute.
In both cases, the higher the value, the more powerful the CPU. For example, a 32-bit microprocessor that runs at 50MHz is more powerful than a 16-32-bit microprocessor that runs at 25MHz. In addition to bandwidth and clock speed, microprocessors are classified as being either RISC (reduced instruction set computer) or CISC (complex instruction set computer).
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A microprocessor has three basic elements, as shown above. The ALU performs all arithmetic computations, such as addition, subtraction and logic operations (AND, OR, etc). It is controlled by the Control Unit and receives its data from the Register Array. The Register Array is a set of registers used for storing data. These registers can be accessed by the ALU very quickly. Some registers have specific functions - we will deal with these later. The Control Unit controls the entire process. It provides the timing and a control signal for getting data into and out of the registers and the ALU and it synchronizes the execution of instructions (we will deal with instruction execution at a later date).
Three Basic Elements of a Microprocessor Micro Controller (µc):
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications.
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Figure: Block Diagram of Micro Controller (µc) Digital Signal Processors (DSPs):
Digital Signal Processors is one which performs scientific and mathematical operation. Digital Signal Processor chips - specialized microprocessors with architectures designed specifically for the types of operations required in digital signal processing. Like a general-purpose microprocessor, a DSP is a programmable device, with its own native instruction code. DSP chips are capable of carrying out millions of floating point operations per second, and like their better-known general-purpose cousins, faster and more powerful versions are continually being introduced. DSPs can also be embedded within complex "system-on-chip" devices, often containing both analog and digital circuitry.
Application Specific Integrated Circuit (ASIC)
ASIC is a combination of digital and analog circuits packed into an IC to achieve the desired control/computation function
Timer, Counter, serial communication ROM, ADC, DAC, Timers, USART, Oscillators
Etc.,
ALU
CU
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CPU cores for computation and control
Peripherals to control timing critical functions Memories to store data and program
Analog circuits to provide clocks and interface to the real world which is analog in nature
I/Os to connect to external components like LEDs, memories, monitors etc.
Computer Instruction Set
There are two different types of computer instruction set there are: 1. RISC (Reduced Instruction Set Computer) and
2. CISC (Complex Instruction Set computer) Reduced Instruction Set Computer (RISC)
A RISC (reduced instruction set computer) is a microprocessor that is designed to perform a smaller number of types of computer instruction so that it can operate at a higher speed (perform more million instructions per second, or millions of instructions per second). Since each instruction type that a computer must perform requires additional transistors and circuitry, a larger list or set of computer instructions tends to make the microprocessor more complicated and slower in operation.
Besides performance improvement, some advantages of RISC and related design improvements are:
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A new microprocessor can be developed and tested more quickly if one of its aims is to be less complicated.
Operating system and application programmers who use the microprocessor's instructions will find it easier to develop code with a smaller instruction set.
The simplicity of RISC allows more freedom to choose how to use the space on a microprocessor.
Higher-level language compilers produce more efficient code than formerly because they have always tended to use the smaller set of instructions to be found in a RISC computer.
RISC characteristics
Simpleinstructionset:
In a RISC machine, the instruction set contains simple, basic instructions, from which more complex instructions can be composed.
Samelengthinstructions.
Each instruction is the same length, so that it may be fetched in a single operation. 1machine-cycleinstructions.
Most instructions complete in one machine cycle, which allows the processor to handle several instructions at the same time. This pipelining is a key technique used to speed up RISC machines.
Complex Instruction Set Computer (CISC)
CISC, which stands for Complex Instruction Set Computer, is a philosophy for designing chips that are easy to program and which make efficient use of memory. Each instruction in a CISC instruction set might perform a series of operations inside the processor. This reduces the number of instructions required to implement
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a given program, and allows the programmer to learn a small but flexible set of instructions.
TheadvantagesofCISC
At the time of their initial development, CISC machines used available technologies to optimize computer performance.
Microprogramming is as easy as assembly language to implement, and much less expensive than hardwiring a control unit.
The ease of micro-coding new instructions allowed designers to make CISC machines upwardly compatible: a new computer could run the same programs as earlier computers because the new computer would contain a superset of the instructions of the earlier computers.
As each instruction became more capable, fewer instructions could be used to implement a given task. This made more efficient use of the relatively slow main memory.
Because micro program instruction sets can be written to match the constructs of high-level languages, the compiler does not have to be as complicated.
ThedisadvantagesofCISC
Still, designers soon realized that the CISC philosophy had its own problems, including:
Earlier generations of a processor family generally were contained as a subset in every new version --- so instruction set & chip hardware become more complex with each generation of computers.
So that as many instructions as possible could be stored in memory with the least possible wasted space, individual instructions could be of almost any
length---12
this means that different instructions will take different amounts of clock time to execute, slowing down the overall performance of the machine.
Many specialized instructions aren't used frequently enough to justify their existence --- approximately 20% of the available instructions are used in a typical program.
CISC instructions typically set the condition codes as a side effect of the instruction. Not only does setting the condition codes take time, but programmers have to remember to examine the condition code bits before a subsequent instruction changes them.
Memory Architecture
There two different type‘s memory architectures there are: Harvard Architecture
Von-Neumann Architecture Harvard Architecture
Computers have separate memory areas for program instructions and data. There are two or more internal data buses, which allow simultaneous access to both instructions and data. The CPU fetches program instructions on the program memory bus.
The Harvard architecture is a computer architecture with physically separate
storage and signal pathways for instructions and data. The term originated from the
Harvard Mark I relay-based computer, which stored instructions on punched tape
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limited data storage, entirely contained within the central processing unit, and provided no access to the instruction storage as data. Programs needed to be loaded by an operator, the processor could not boot itself.
Figure: Harvard Architecture
Modern uses of the Harvard architecture:
The principal advantage of the pure Harvard architecture - simultaneous access to more than one memory system - has been reduced by modified Harvard processors using modern CPU cache systems. Relatively pure Harvard architecture machines are used mostly in applications where tradeoffs, such as the cost and power savings from omitting caches, outweigh the programming penalties from having distinct code and data address spaces.
Digital signal processors (DSPs) generally execute small, highly-optimized audio or video processing algorithms. They avoid caches because their behavior must be extremely reproducible. The difficulties of coping with multiple address spaces are of secondary concern to speed of execution. As a result, some DSPs have multiple data memories in distinct address spaces to facilitate SIMD and VLIW
processing. Texas Instruments TMS320 C55x processors, as one example, have multiple parallel data busses (two write, three read) and one instruction bus.
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Microcontrollers are characterized by having small amounts of program (flash memory) and data (SRAM) memory, with no cache, and take advantage of the Harvard architecture to speed processing by concurrent instruction and data access. The separate storage means the program and data memories can have different bit depths, for example using 16-bit wide instructions and 8-bit wide data. They also mean that instruction pre-fetch can be performed in parallel with other activities. Examples include, the AVR by Atmel Corp, the PIC by Microchip Technology, Inc.
and the ARM Cortex-M3 processor (not all ARM chips have Harvard architecture). Even in these cases, it is common to have special instructions to access program memory as data for read-only tables, or for reprogramming.
Von-Neumann Architecture
A computer has a single, common memory space in which both program instructions and data are stored. There is a single internal data bus that fetches both instructions and data. They cannot be performed at the same time
The von Neumann architecture is a design model for a stored-program digital computer that uses a central processing unit (CPU) and a single separate storage structure ("memory") to hold both instructions and data. It is named after the mathematician and early computer scientist John von Neumann. Such computers implement a universal Turing machine and have a sequential architecture.
A stored-program digital computer is one that keeps its programmed instructions, as well as its data, in read-write, random-access memory (RAM). Stored-program computers were advancement over the program-controlled computers of the 1940s, such as the Colossus and the ENIAC, which were programmed by setting switches
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and inserting patch leads to route data and to control signals between various functional units. In the vast majority of modern computers, the same memory is used for both data and program instructions. The mechanisms for transferring the data and instructions between the CPU and memory are, however, considerably more complex than the original von Neumann architecture.
The terms "von Neumann architecture" and "stored-program computer" are generally used interchangeably, and that usage is followed in this article.
Figure: Schematic of the Von-Neumann Architecture.
Basic Difference between Harvard and Von-Neumann Architecture
The primary difference between Harvard architecture and the Von Neumann architecture is in the Von Neumann architecture data and programs are stored in the same memory and managed by the same information handling system.
Whereas the Harvard architecture stores data and programs in separate memory devices and they are handled by different subsystems.
In a computer using the Von-Neumann architecture without cache; the central processing unit (CPU) can either be reading and instruction or writing/reading data to/from the memory. Both of these operations cannot occur simultaneously as the data and instructions use the same system bus.
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In a computer using the Harvard architecture the CPU can both read an instruction and access data memory at the same time without cache. This means that a computer with Harvard architecture can potentially be faster for a given circuit complexity because data access and instruction fetches do not contend for use of a single memory pathway.
Today, the vast majority of computers are designed and built using the Von Neumann architecture template primarily because of the dynamic capabilities and efficiencies gained in designing, implementing, operating one memory system as opposed to two. Von Neumann architecture may be somewhat slower than the contrasting Harvard Architecture for certain specific tasks, but it is much more flexible and allows for many concepts unavailable to Harvard architecture such as self programming, word processing and so on.
Harvard architectures are typically only used in either specialized systems or for very specific uses. It is used in specialized digital signal processing (DSP), typically for video and audio processing products. It is also used in many small microcontrollers used in electronics applications such as Advanced RISK Machine (ARM) based products for many vendors.
17 THE MICROCONTROLLER:
A microcontroller is a general purpose device, but that is meant to read data, perform limited calculations on that data and control its environment based on those calculations. The prime use of a microcontroller is to control the operation of a machine using a fixed program that is stored in ROM and that does not change over the lifetime of the system.
The microcontroller design uses a much more limited set of single and double byte instructions that are used to move data and code from internal memory to the ALU. The microcontroller is concerned with getting data from and to its own pins; the architecture and instruction set are optimized to handle data in bit and byte size.
The AT89C51 is a low-power, high-performance CMOS 8-bit microcontroller with 4k bytes of Flash Programmable and erasable read only memory (EROM). The device is manufactured using Atmel‘s high-density nonvolatile memory technology and is functionally compatible with the industry-standard 80C51 microcontroller instruction set and pin out. By combining versatile 8-bit CPU with Flash on a monolithic chip, the Atmel‘s AT89c51 is a powerful microcomputer, which provides a high flexible and cost- effective solution to many embedded control applications.
18 AT89C51 MICROCONTROLLER
FEATURES
80C51 based architecture
4-Kbytes of on-chip Reprogrammable Flash Memory 128 x 8 RAM
Two 16-bit Timer/Counters Full duplex serial channel Boolean processor
Four 8-bit I/O ports, 32 I/O lines Memory addressing capability
– 64K ROM and 64K RAM Power save modes:
– Idle and power-down Six interrupt sources
Most instructions execute in 0.3 us CMOS and TTL compatible
Maximum speed: 40 MHz @ Vcc = 5V Industrial temperature available
Packages available: – 40-pin DIP
– 44-pin PLCC – 44-pin PQFP
19 Pin configuration:
20 AT89C51 Block Diagram
21 PIN DESCRIPTION: VCC Supply voltage GND Ground Port 0
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.
Port 0 can also be configured to be the multiplexed low order address/data bus during access to external program and data memory. In this mode, P 0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
22 Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The port 1output buffers can sink/source four TTL inputs. When 1s are written to port 1 pins, they are pulled high by the internal pull-ups can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (1) because of the internal pull-ups.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The port 2 output buffers can sink/source four TTL inputs. When 1s are written to port 2 pins, they are pulled high by the internal pull-ups can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and during access to DPTR. In this application Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit data address (MOVX@R1), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
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Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The port 3 output buffers can sink/source four TTL inputs. When 1s are written to port 3 pins, they are pulled high by the internal pull-ups can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the internal pull-ups.
Port 3 also receives some control signals for Flash Programming and verification.
Port
pin
Alternate Functions
P3.0 RXD(serial input port) P3.1 TXD(serial input port)
P3.2 INT0(external interrupt 0) P3.3 INT1(external interrupt 1) P3.4 T0(timer 0 external input) P3.5 T1(timer 1 external input)
P3.6 WR(external data memory write strobe)
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strobe)
RST
Rest input A on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG:
Address Latch Enable is an output pulse for latching the low byte of the address during access to external memory. This pin is also the program pulse input (PROG) during Flash programming.
In normal operation ALE is emitted at a constant rate of 1/16 the oscillator frequency and may be used for external timing or clocking purpose. Note, however, that one ALE pulse is skipped during each access to external Data memory.
_____
PSEN
Program Store Enable is the read strobe to external program memory when the AT89c51 is executing code from external program memory PSEN is activated
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twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
__
EA /VPP
External Access Enable (EA) must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000h up to FFFFH. Note, however, that if lock bit 1 is programmed EA will be internally latched on reset. EA should be strapped to Vcc for internal program executions. This pin also receives the 12-volt programming enable voltage (Vpp) during Flash programming when 12-volt programming is selected.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL 2
Output from the inverting oscillator amplifier.
OPERATING DESCRIPTION
26 • Memory Map and Registers
• Timer/Counters
• Interrupt System
MEMORY MAP AND REGISTERS
Memory
The AT89C51 has separate address spaces for program and data memory. The program and data memory can be up to 64K bytes long. The lower 4K program memory can reside on-chip. The AT89C51 has 128 bytes of on-chip RAM.
The lower 128 bytes can be accessed either by direct addressing or by indirect addressing. The lower 128 bytes of RAM can be divided into 3 segments as listed below
1. Register Banks 0-3: locations 00H through 1FH (32 bytes). The device after reset defaults to register bank 0. To use the other register banks, the user must select them in software. Each register bank contains eight 1-byte registers R0-R7. Reset
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initializes the stack point to location 07H, and is incremented once to start from 08H, which is the first register of the second register bank.
2. Bit Addressable Area: 16 bytes have been assigned for this segment 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0-7FH). Each of the 16 bytes in this segment can also be addressed as a byte.
3. Scratch Pad Area: 30H-7FH are available to the user as data RAM. However, if the data pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction.
28 SPECIAL FUNCTION REGISTERS:
The Special Function Registers (SFR's) are located in upper 128 Bytes direct addressing area. The SFR Memory Map in shows that.
Not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses in general return random data, and write accesses have no effect. User software should not write 1s to these unimplemented locations, since they may be used in future microcontrollers to invoke new features. In that case, the reset or inactive values of the new bits will always be 0, and their active values will be 1.
The functions of the SFR‘s are outlined in the following sections.
Accumulator (ACC)
ACC is the Accumulator register. The mnemonics for Accumulator-specific instructions, however, refer to the Accumulator simply as A.
B Register (B)
The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register.
Program Status Word (PSW)
The PSW register contains program status information. Stack Pointer (SP)
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The Stack Pointer Register is eight bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H.
Data Pointer (DPTR)
The Data Pointer consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Serial Data Buffer (SBUF)
The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer, where it is held for serial transmission. (Moving a byte to SBUF initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer. Timer Registers
Register pairs (TH0, TL0) and (TH1, TL1) are the 16-bit Counter registers for Timer/Counters 0 and 1, respectively.
Control Registers
Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON contain control and status bits for the interrupt system, the Timer/Counters, and the serial port.
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The IS89C51 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. All two can be configured to operate either as Timers or event counters. As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
As a Counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 and T1. The external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next
cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but it should be held for at least one full machine cycle to ensure that a given level is sampled at least once before it changes.
In addition to the Timer or Counter functions, Timer 0 and Timer 1 have four operating modes: 13-bit timer, 16-bit timer, 8-bit auto-reload, split timer.
31 12D OSCILLATOR FREQUENCY TR TLX THX TFX SFR’S USED IN TIMERS
The special function registers used in timers are,
TMOD Register
TCON Register
Timer(T0) & timer(T1) Registers
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TMOD is dedicated solely to the two timers (T0 & T1).
The timer mode SFR is used to configure the mode of operation of each of the two timers. Using this SFR your program may configure each timer to be a 16-bit timer, or 13 bit timer, 8-bit auto reload timer, or two separate timers. Additionally you may configure the timers to only count when an external pin is activated or to count ―events‖ that are indicated on an external pin.
It can consider as two duplicate 4-bit registers, each of which controls the action of one of the timers.
(ii) TCON Register:
The timer control SFR is used to configure and modify the way in which the 8051‘s two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in TCON SFR.
These bits are used to configure the way in which the external interrupt flags are activated, which are set when an external interrupt occurs.
33 (iii) TIMER 0 (T0):
TO (Timer 0 low/high, address 8A/8C h)
These two SFR‘s taken together represent timer 0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value.
T H0 T L0
(iv) TIMER 1 (T1):
T1 (Timer 1 Low/High, address 8B/ 8D h)
These two SFR‘s, taken together, represent timer 1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is Configurable is how and when they increment in value.
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The Timer or Counter function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timer/Counters, but Mode 3 is different.
The four modes are described in the following sections.
Mode 0:
Both Timers in Mode 0 are 8-bit Counters with a divide-by-32 pre scalar. Figure 8 shows the Mode 0 operation as it applies to Timer 1. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TF1. The counted input is enabled to the Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. Setting GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a control bit in the Special Function Register TCON. Gate is in TMOD.
The 13-bit register consists of all eight bits of TH1 and the lower five bits of TL1. The upper three bits of TL1 are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers.
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Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0 and INT0 replace the corresponding Timer 1 signals. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Mode 1
Mode 1 is the same as Mode 0, except that the Timer register is run with all 16 bits. The clock is applied to the combined high and low timer registers (TL1/TH1). As clock pulses are received, the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to-0000H overflow flag. The timer continues to count. The overflow flag is the TF1 bit in TCON that is read or written by software
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 10. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves the TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0.
Mode 3
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 11. TL0 uses the Timer 0 control
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bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt.
Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89C51 can appear to have three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt.
INTERRUPT SYSTEM
An interrupt is an external or internal event that suspends the operation of micro controller to inform it that a device needs its service. In interrupt method, whenever any device needs its service, the device notifies the micro controller by sending it an interrupt signal. Upon receiving an interrupt signal, the micro controller interrupts whatever it is doing and serves the device. The program associated with interrupt is called as interrupt service subroutine (ISR).Main advantage with interrupts is that the micro controller can serve many devices.
Baud Rate
The baud rate in Mode 0 is fixed as shown in the following equation. Mode 0 Baud Rate = Oscillator Frequency /12 the baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON. If SMOD = 0 the baud rate is 1/64 of the oscillator frequency. If SMOD = 1, the baud rate is 1/32 of the oscillator frequency.
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Mode 2 Baud Rate = 2SMODx (Oscillator Frequency)/64.
In the IS89C51, the Timer 1 overflow rate determines the baud rates in Modes 1 and 3.
NUMBER OF INTERRUPTS IN 89C51:
There are basically five interrupts available to the user. Reset is also considered as an interrupt. There are two interrupts for timer, two interrupts for external hardware interrupt and one interrupt for serial communication.
Memory location Interrupt name 0000H Reset
0003H External interrupt 0 000BH Timer interrupt 0 0013H External interrupt 1 001BH Timer interrupt 1 0023H Serial COM interrupt
Lower the vector, higher the priority. The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in TCON. When the service routine is vectored, hardware clears the flag that generated an external interrupt only if the interrupt was transition-activated.
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If the interrupt was level-activated, then the external requesting source (rather than the on-chip hardware) controls the request flag.
The Timer 0 and Timer 1 Interrupts are generated by TF0and TF1, which are set by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode 3).When a timer interrupt is generated, the on-chip hardware clears the flag that is generated.
The Serial Port Interrupt is generated by the logical OR of RI and TI. The service routine normally must determine whether RI or TI generated the interrupt, and the bit must be cleared in software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated and pending interrupts can be canceled in software.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE (interrupt enable) at address 0A8H. There is a global enable/disable bit that is cleared to disable all interrupts or to set the interrupts.
IE (Interrupt enable register): Steps in enabling an interrupt:
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Bit D7 of the IE register must be set to high to allow the rest of register to take effect. If EA=1, interrupts are enabled and will be responded to if their corresponding bits in IE are high. If EA=0, no interrupt will be responded to even if the associated bit in the IE register is high.
Description of each bit in IE register:
D7 bit: Disables all interrupts. If EA =0, no interrupt is acknowledged, if EA=1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
D6 bit: Reserved.
D5 bit: Enables or disables timer 2 over flow interrupt (in 8052). D4 bit: Enables or disables serial port interrupt.
D3 bit: Enables or disables timer 1 over flow interrupt. D2 bit: Enables or disables external interrupt 1.
D1 bit: Enables or disables timer 0 over flow interrupt. D0 bit: Enables or disables external interrupt 0.
40 Interrupt priority in 89C51:
There is one more SRF to assign priority to the interrupts which is named as interrupt priority (IP). User has given the provision to assign priority to one interrupt. Writing one to that particular bit in the IP register fulfils the task of assigning the priority.
Description of each bit in IP register:
D7 bit: Reserved. D6 bit: Reserved.
D5 bit: Timer 2 interrupt priority bit (in 8052). D4 bit: Serial port interrupt priority bit.
D3 bit: Timer 1 interrupt priority bit. D2 bit: External interrupt 1 priority bit. D1 bit: Timer 0 interrupt priority bit. D0 bit: External interrupt 0 priority bit.
Power Supply: Block diagram:
41 Figure: Power Supply
Circuitdiagram:
Description: Transformer:
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A transformer is a device that transfers electrical energy from one circuit to another through inductively coupled conductors—the transformer's coils. A varying current in the first or primary winding creates a varying magnetic flux in the transformer's core, and thus a varying magnetic field through the secondary winding. This varying magnetic field induces a varying electromotive force (EMF) or "voltage" in the secondary winding. This effect is called mutual induction.
Figure: Transformer Symbol
(or)
Transformer is a device that converts the one form energy to another form of energy like a transducer.
43 Basic Principle :
A transformer makes use of Faraday's law and the ferromagnetic properties of an iron core to efficiently raise or lower AC voltages. It of course cannot increase power so that if the voltage is raised, the current is proportionally lowered and vice versa.
44 Transformer Working:
A transformer consists of two coils (often called 'windings') linked by an iron core, as shown in figure below. There is no electrical connection between the coils, instead they are linked by a magnetic field created in the core.
Figure: Basic Transformer
Transformers are used to convert electricity from one voltage to another with minimal loss of power. They only work with AC (alternating current) because they require a changing magnetic field to be created in their core. Transformers can increase voltage (step-up) as well as reduce voltage (step-down).
Alternating current flowing in the primary (input) coil creates a continually changing magnetic field in the iron core. This field also passes through the secondary (output) coil and the changing strength of the magnetic field induces an
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alternating voltage in the secondary coil. If the secondary coil is connected to a load the induced voltage will make an induced current flow. The correct term for the induced voltage is 'induced electromotive force' which is usually abbreviated to induced e.m.f.
The iron core is laminated to prevent 'eddy currents' flowing in the core. These are currents produced by the alternating magnetic field inducing a small voltage in the core, just like that induced in the secondary coil. Eddy currents waste power by needlessly heating up the core but they are reduced to a negligible amount by laminating the iron because this increases the electrical resistance of the core without affecting its magnetic properties.
Transformers have two great advantages over other methods of changing voltage: 1. They provide total electrical isolation between the input and output, so they
can be safely used to reduce the high voltage of the mains supply.
2. Almost no power is wasted in a transformer. They have a high efficiency (power out / power in) of 95% or more.
Classification of Transformer: Step-Up Transformer Step-Down Transformer Step-Down Transformer:
Step down transformers are designed to reduce electrical voltage. Their primary voltage is greater than their secondary voltage. This kind of transformer "steps down" the voltage applied to it. For instance, a step down transformer is needed to use a 110v product in a country with a 220v supply.
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Step down transformers convert electrical voltage from one level or phase configuration usually down to a lower level. They can include features for electrical isolation, power distribution, and control and instrumentation applications. Step down transformers typically rely on the principle of magnetic induction between coils to convert voltage and/or current levels.
Step down transformers are made from two or more coils of insulated wire wound around a core made of iron. When voltage is applied to one coil (frequently called the primary or input) it magnetizes the iron core, which induces a voltage in the other coil, (frequently called the secondary or output). The turn‘s ratio of the two sets of windings determines the amount of voltage transformation.
Figure: Step-Down Transformer
An example of this would be: 100 turns on the primary and 50 turns on the secondary, a ratio of 2 to 1.
Step down transformers can be considered nothing more than a voltage ratio device.
With step down transformers the voltage ratio between primary and secondary will mirror the "turn‘s ratio" (except for single phase smaller than 1 kva which have
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compensated secondary). A practical application of this 2 to 1 turn‘s ratio would be a 480 to 240 voltage step down. Note that if the input were 440 volts then the output would be 220 volts. The ratio between input and output voltage will stay constant. Transformers should not be operated at voltages higher than the nameplate rating, but may be operated at lower voltages than rated. Because of this it is possible to do some non-standard applications using standard transformers.
Single phase step down transformers 1 kva and larger may also be reverse connected to step-down or step-up voltages. (Note: single phase step up or step down transformers sized less than 1 KVA should not be reverse connected because the secondary windings have additional turns to overcome a voltage drop when the load is applied. If reverse connected, the output voltage will be less than desired.)
Step-Up Transformer:
A step up transformer has more turns of wire on the secondary coil, which makes a larger induced voltage in the secondary coil. It is called a step up transformer because the voltage output is larger than the voltage input.
Step-up transformer 110v 220v design is one whose secondary voltage is greater than its primary voltage. This kind of transformer "steps up" the voltage applied to it. For instance, a step up transformer is needed to use a 220v product in a country with a 110v supply.
A step up transformer 110v 220v converts alternating current (AC) from one voltage to another voltage. It has no moving parts and works on a magnetic induction principle; it can be designed to "step-up" or "step-down" voltage. So a step up transformer increases the voltage and a step down transformer decreases the voltage.
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The primary components for voltage transformation are the step up transformer core and coil. The insulation is placed between the turns of wire to prevent shorting to one another or to ground. This is typically comprised of Mylar, nomex, Kraft paper, varnish, or other materials. As a transformer has no moving parts, it will typically have a life expectancy between 20 and 25 years.
Figure: Step-Up Transformer Applications
Generally these Step-Up Transformers are used in industries applications only. Turns Ratio and Voltage
The ratio of the number of turns on the primary and secondary coils determines the ratio of the voltages...
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...where Vp is the primary (input) voltage, Vs is the secondary (output) voltage, Np is the number of turns on the primary coil, and Ns is the number of turns on the secondary coil.
Diodes:
Diodes allow electricity to flow in only one direction. The arrow of the circuit symbol shows the direction in which the current can flow. Diodes are the electrical version of a valve and early diodes were actually called valves.
Figure: Diode Symbol
A diode is a device which only allows current to flow through it in one direction. In this direction, the diode is said to be 'forward-biased' and the only effect on the signal is that there will be a voltage loss of around 0.7V. In the opposite direction, the diode is said to be 'reverse-biased' and no current will flow through it.
Rectifier
The purpose of a rectifier is to convert an AC waveform into a DC waveform (OR) Rectifier converts AC current or voltages into DC current or voltage. There are two
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different rectification circuits, known as 'half-wave' and 'full-wave' rectifiers. Both use components called diodes to convert AC into DC.
The Half-wave Rectifier
The half-wave rectifier is the simplest type of rectifier since it only uses one diode, as shown in figure .
Figure: Half Wave Rectifier
Figure 2 shows the AC input waveform to this circuit and the resulting output. As you can see, when the AC input is positive, the diode is forward-biased and lets the current through. When the AC input is negative, the diode is reverse-biased and the diode does not let any current through, meaning the output is 0V. Because there is a 0.7V voltage loss across the diode, the peak output voltage will be 0.7V less than Vs.
51 Figure: Half-Wave Rectification
While the output of the half-wave rectifier is DC (it is all positive), it would not be suitable as a power supply for a circuit. Firstly, the output voltage continually varies between 0V and Vs-0.7V, and secondly, for half the time there is no output at all.
The Full-wave Rectifier
The circuit in figure 3 addresses the second of these problems since at no time is the output voltage 0V. This time four diodes are arranged so that both the positive and negative parts of the AC waveform are converted to DC. The resulting waveform is shown in figure 4.
52 Figure: Full-Wave Rectifier
Figure: Full-Wave Rectification
When the AC input is positive, diodes A and B are forward-biased, while diodes C and D are reverse-biased. When the AC input is negative, the opposite is true - diodes C and D are forward-biased, while diodes A and B are reverse-biased.
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While the full-wave rectifier is an improvement on the half-wave rectifier, its output still isn't suitable as a power supply for most circuits since the output voltage still varies between 0V and Vs-1.4V. So, if you put 12V AC in, you will 10.6V DC out. Capacitor Filter
The capacitor-input filter, also called "Pi" filter due to its shape that looks like the Greek letter pi, is a type of electronic filter. Filter circuits are used to remove unwanted or undesired frequencies from a signal.
Figure: Capacitor Filter
A typical capacitor input filter consists of a filter capacitor C1, connected across the rectifier output, an inductor L, in series and another filter capacitor connected across the load.
1. The capacitor C1 offers low reactance to the AC component of the rectifier output while it offers infinite reactance to the DC component. As a result the capacitor shunts an appreciable amount of the AC component while the DC component continues its journey to the inductor L
2. The inductor L offers high reactance to the AC component but it offers almost zero reactance to the DC component. As a result the DC component flows through the inductor while the AC component is blocked.
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3. The capacitor C2 bypasses the AC component which the inductor had failed to block. As a result only the DC component appears across the load RL.
Figure: Centered Tapped Full-Wave Rectifier with a Capacitor Filter
Voltage Regulator:
A voltage regulator is an electrical regulator designed to automatically maintain a constant voltage level. It may use an electromechanical mechanism, or passive or active electronic components. Depending on the design, it may be used to regulate one or more AC or DC voltages. There are two types of regulator are they.
Positive Voltage Series (78xx) and Negative Voltage Series (79xx)
78xx:‘78‘ indicate the positive series and ‗xx‘indicates the voltage rating. Suppose 7805 produces the maximum 5V.‘05‘indicates the regulator output is 5V.
79xx:‘78‘ indicate the negative series and ‗xx‘indicates the voltage rating. Suppose 7905 produces the maximum -5V.‘05‘indicates the regulator output is -5V.
55 These regulators consists the three pins there are Pin1: It is used for input pin.
Pin2: This is ground pin for regulator
Pin3: It is used for output pin. Through this pin we get the output.
Figure: Regulator
DTMF
Introduction
Dual-Tone Multi-Frequency (DTMF) signaling is a standard telecommunication system developed by Bell Laboratories. The DTMF signaling was proposed more than 30 years ago to replace slower pulse dialing. Many things have changed since this time, but DTMF has become the most popular addressing and messaging tool in telecommunications, and it does not look as though it will fade away in foreseeable future. In this system, a matrix is used to compose a signal, which consists of a lower frequency group containing four distinguished frequencies which are below 1
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KHz and a high frequency group also containing four distinguished frequencies which are above 1 KHz (figure 2). Each telephone key contains a pair of simultaneous low and high frequency tones.
To detect DTMF signals by software in the digital domain, many algorithms, including Fast Fourier Transform (FFT), Goertzel DFT, Modified Goertzel Algorithm, Non-uniform Discrete Fourier Transform (NDFT), Sub band NDFT, and Adaptive Frequency Estimation are proposed. The Modified Goertzel Algorithm is one of the most accurate and computing-efficient technologies for limited frequency detection. In DTMF tone detection cases, the Goertzel Algorithm only transforms 8 frequencies instead of perform on an entire spectrum like FFT. This saves a lot computational resources, which is critical for lower-power processors. Its non-complexity is easy to adapt into small MCU and DSP.
We are using M8870 ic. The M-8870 is a full DTMF Receiver that integrates both band split filter and decoder functions into a single 18-pin DIP or SOIC package. Manufactured using CMOS process technology, the M-8870 offers low power
1 2 3 A 4 5 6 B 7 8 9 C * 0 # D 697 Hz 770 Hz 852 Hz 941Hz 1209 Hz 1336 Hz 1744 Hz 1633 Hz Figure 2. DTMF matrix High frequency group
Lo w fr eq u en cy g ro u p
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consumption (35 mW max) and precise data handling. Its filter section uses switched capacitor technology for both the high and low group filters and for dial tone rejection. Its decoder uses digital counting techniques to detect and decode all 16 DTMF tone pairs into a 4-bit code. External component count is minimized by provision of an on-chip differential input amplifier, clock generator, and latched tri-state interface bus. Minimal external components required include a low-cost 3.579545 MHz color burst crystal, a timing resistor, and a timing capacitor. The M-8870-02 provides a ―power-down‖ option which, when enabled, drops consumption to less than 0.5 mW. The M-8870-02 can also inhibit the decoding of fourth column digits.
MT8870 (INTEGRATED DTMF RECEIVER)
The MT8870D/MT8870D-1 monolithic DTMF receiver offers small size, low power consumption and high performance. It is a complete DTMF (Dual Tone Multiple Frequency) receiver integrating both the band split filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone pairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface.
Features:
58 • Low power consumption
• Internal gain setting amplifier • Adjustable guard time
• Central office quality • Power-down mode • Inhibit mode
• Backward compatible with MT8870C/MT8870C-1
59 Pin Description:
1. IN+ Non-Inverting Op-Amp (Input).
2. IN- Inverting Op-Amp (Input).
3. GS Gain Select. Gives access to output of front end differential amplifier for
Connection of feedback resistor
4. Vref Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at
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5. INH Inhibit (Input). Logic high inhibits the detection of tones representing
Characters A, B, C and D. This pin input is internally pulled down.
6. PWDN Power down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down.
7. OSC1 Clock (Input).
8. OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit.
9. VSS Ground (Input) 0.V typical.
10. TOE Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled up internally.
Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance.
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15. StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt.
16. ESt Early Steering (Output). Presents logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
17. St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at St Causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt free the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St.
18. VDD Positive power supply (Input). +5V typical.
NC No Connection.
62 Filter Section:
Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor band pass filters, the bandwidths of which correspond to the low and high group frequencies. The filter output is followed by a single order switched capacitor filter section which smoothes the signals Prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals.
Decoder Section:
Digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. When the detector recognizes the presence of two valid tones the ―Early Steering‖ (ESt) output will go
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to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.
Steering Circuit:
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.
Crystal Oscillator:
The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal
Differential Input Configuration:
The input arrangement of the MT8870D/MT8870D-1 provides a differential-input operational amplifier as well as a bias source (VRef) which is used to bias the inputs
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at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. The op-amp connected for unity gain and Vref biasing the input at 1/2VDD.
Power-down Mode:
Logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby mode. It stops the oscillator and the functions of the filters.
Inhibit Mode:
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones.
Applications:
Receiver system for British telecom spec por 1151 Paging systems
Repeater systems/mobile radio Credit card systems
Remote control Personal computers
65 SERIAL COMMUNICATION
THEORY:
In order to connect micro controller to a modem or a pc to modem a serial port is used. Serial is a very common protocol for device communication that is standard on almost every PC. Most computers include two RS-232 based serial ports. Serial is also a common communication protocol that is used by
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many devices for instrumentation; numerous GPIB-compatible devices also come with an RS-232 port. Furthermore, serial communication can be used for data acquisition in conjunction with a remote sampling device.
The concept of serial communication is simple. The serial port sends and receives bytes of information one bit at a time. Although this is slower than parallel communication, which allows the transmission of an entire byte at once, it is simpler and can be used over longer distances. For example, the IEEE 488 specifications for parallel communication state that the cabling between equipment can be no more than 20 meters total, with no more than 2 meters between any two devices. Serial, however, can extend as much as 1200 meters.
Typically, serial is used to transmit ASCII data. Communication is completed using 3 transmission lines: (1) Ground, (2) Transmit, and (3) Receive. Since serial is asynchronous, the port is able to transmit data on one line while receiving data on another. Other lines are available for handshaking, but are not required. The important serial characteristics are baud rate, data bits, stop bits, and parity. For two ports to communicate, these parameters must match.
Baud rate: It is a speed measurement for communication. It indicates the number of bit transfers per second. For example, 300 baud is 300 bits per second. When a clock cycle is referred it means the baud rate. For example, if the protocol calls for a 4800 baud rate, then the clock is running at 4800Hz. This means that the serial port is sampling the data line at 4800Hz. Common baud rates for telephone lines are 14400, 28800, and 33600. Baud rates greater than these are possible, but these rates reduce the distance by which devices can be separated. These high baud rates are
