PRODUCT OVERVIEW
3D PLUS offers a family of space qualified DDR3 Synchronous Dynamic RAM (SDRAM) memory modules, with densities up to 48 Gbit; data bus widths of 16bits, 48 bits and 72 bits; and operating at frequencies up to 667 MHz
3D PLUS’s DDR3 products are a perfect fit for systems requiring best in class, high performance memories; offering high speed bandwidth solutions that are qualified and characterized for use in the extreme environments present in most space applications.
Those memories are typically well suited to gain all benefits from space grade microprocessors, DSPs and/or FPGAs.
3D PLUS’s DDR3 memory modules are part of a DDR3 ecosystem, providing fully space qualified memory subsystem solution.
KEY BENEFITS
3D PLUS’s DDR3 Ecosystem includes:
An optimized design including
decoupling capacitors and termination resistors (for x72 and x 48 bit bus wide)
A wide range of DDR3 memories to handle high speed computing data requirements
A DDR3 Termination Regulator to efficiently provide stable VTT to DDR3 components
DDR3 RIMC (Radiation Intelligent Memory Controller) IP that allows enhanced mitigation and protection against SEU/SEFI.
KEY FEATURES PERFORMANCES
JEDEC JESD79-3F compliant
Organization: 256M x 64 bits (+ 8 bits ECC)
Including decoupling and termination
Max Clock rate available: 667 MHz
Max Transfer Rate 1333 MT/s
Up to 200 MHz in DLL off mode
VDD/VDDQ= 1.35 V, backward compatible 1.5 V
Programmable #CAS latency (CL)
Programmable Additive Latency
Programmable Burst Length 4 and 8
Programmable Burst Sequence: Sequential or Interleaved
Burst Length switch on the fly
Auto Self Refresh
TDQS (Termination Data Strobe) supported
Dynamic On-die Termination (ODT)
Write Leveling
Available temperature range: 0°C to +70°C, -40°C to +85°C , -40°C to +105°C
Qualified for Space Applications
SPACE QUALIFICATION
Qualified with 3D PLUS ESA certification per ESCC 2566001
Up to NASA Level 1
Long Term Availability and High Reliability
Radiation Hardened Designed for High End Space computing applications
Flight heritage: 3D PLUS expertise in space memories for more than 20 years(*)
*From SRAM, SDRAM to DDR1/2/3
RADIATION TOLERANCE
TID > 75 krad
SEL immune up to LET > 67 MeV.cm2/mg
SEU mitigation thanks to RIMC DDR3.
TABLE OF CONTENTS
PRODUCT OVERVIEW... 1
KEY BENEFITS... 1
KEY FEATURES ... 1
PERFORMANCES ... 1
SPACE QUALIFICATION ... 1
RADIATION TOLERANCE ... 1
1. DOCUMENTS ... 5
1.1 APPLICABLE DOCUMENTS... 5
1.2 REFERENCE DOCUMENTS ... 5
1.3 ACRONYMS ... 5
2. GENERAL DESCRIPTION ... 6
2.1 INTRODUCTION ... 6
2.2 TYPE VARIANTS ... 7
2.3 RADIATION PERFORMANCES... 8
3. FUNCTIONAL DESCRIPTION... 8
3.1 SIMPLIFIED STATE DIAGRAM ... 9
4. BALLOUT... 10
4.1 BALL ASSIGNMENTS... 10
4.2 INPUT/OUTPUT DESCRIPTION... 11
5. COMMANDS ... 12
5.1 COMMAND TRUTH TABLE ... 13
5.2 CKE TRUTH TABLE ... 15
6. ODT ... 16
7. ELECTRICAL CHARACTERISTICS ... 17
7.1 ABSOLUTE MAXIMUM RATINGS ... 17
7.2 RECOMMENDED DC OPERATING CONDITIONS... 17
7.3 OPERATING TEMPERATURE RANGE ... 18
7.4 MODULE CAPACITANCE... 18
7.5 CURRENT SPECIFICATION LIMITS ... 19
7.1 AC AND DC MEASUREMENTS LEVELS... 20
7.2 AC TIMINGS PARAMETERS ... 20
8. ORDERING INFORMATION... 22
8.1 PACKAGING... 23
8.1 HANDLING AND ASSEMBLY RECOMMENDATIONS... 23
8.1.1 Packing... 23
8.1.2 Handling ... 24
8.1.3 Storage... 24
8.1.4 Board Assembly ... 24
8.1.5 Electrostatic Discharge Sensitivity ... 24
9. REVISION HISTORY ... 25
10. 3D PLUS SALES OFFICES... 25
TABLES
Table 1: Component type variants... 7
Table 2: DDR3 module radiation data without RIMC DDR3... 8
Table 3: DDR3 module radiation data with RIMC DDR3... 8
Table 4: Ball description ... 12
Table 5: Commands list ... 12
Table 6: Command truth table ... 14
Table 7: CKE truth table ... 15
Table 8: Absolute maximum ratings ... 17
Table 9: DC operating conditions ... 17
Table 10: Temperature range ... 18
Table 11: Pin capacitances ... 18
Table 12: IDDlimits for module 3D3D16G72WB2723 ... 19
Table 13: 3D3D16G72WB2723 AC characteristics... 20
Table 14: Speed bins... 20
Table 15: Revision history ... 25
FIGURES
Figure 1: Functional block diagram ... 6
Figure 2: Decoupling capacitors and termination resistors embedded in the module ... 7
Figure 3: Simplified state diagram ... 9
Figure 4: Ball assignments ... 10
Figure 5: Functional representation of ODT ... 16
Figure 6: Ordering information... 22
Figure 7: 3D3D16G72WB2723 mechanical drawing... 23
Figure 8: 3D3D16G72WB2723 marking... 24
1. DOCUMENTS
1.1 APPLICABLE DOCUMENTS
[AD1] 3DPA-7410: Detail Specification 16 Gbit DDR3 SDRAM P/N: 3D3D16G72WB2723 [AD2] 3300-8283: Automatic Assembly Recommendations – BGA modules
[AD3] 3000-1253: Pinout P/N : 3D3D16G72WB2723 [AD4] 3250-0060: Footprint
[AD5] 3200-3547: Step file
1.2 REFERENCE DOCUMENTS
[RD1] 3315-0118: 3DIPMC0744 & 3D PLUS SDRAM modules Generic Report (under NDA) [RD2] 3616-0055: Decoupling Capacitor Application Note, applicable for P/N:3D3D16G72WB2723 [RD3] 3300-9311: DDR3 Modules Unused Pins, x16 bit basic device.
[RD4] JESD79-3F: JEDEC DDR3 SDRAM Standard, July 2012
1.3 ACRONYMS
DDR Double Data Rate RAM Random Access Memory
ECC Error Correcting Code SDRAM Synchronous Dynamic RAM
ESA European Space Agency SEE Single Event Effect
ESD ElectroStatic Discharge SEFI Single Event Functional Interrupt
FPGA Field Programmable Gate Array SEL Single Event Latch up
GND Ground SET Single Event Transient
HBM Human Body Model SEU Single Event Upset
I/O Input/Output TID Total Ionizing Dose
P/N Part Number
2. GENERAL DESCRIPTION 2.1 INTRODUCTION
The 3D3D16G72WB2723 is a highly integrated module operating as a DDR3 SDRAM 72bits SO-DIMM in a BGA package. It is intended for use as main memory in space embedded systems.
It offers a memory density of 16 Gb with 8 bits ECC on a 72 bits data bus in a single rank of 256 Mb x (64 bits + 8 bits) high speed memory array. This high speed memory array is based on 5 dies achieving high speed double-data-rate transfer rates of up to 1333 MTs for general applications. The memory module operates with a single power supply: 1.35 V (backward compatible 1.5V).
All the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a RAS# and CAS# multiplexing style.
3D3D16G72WB2723 memory is ideal for high density memory applications that require high speed transfer and compatibility with space processors, DSP or FPGAs. It is well suited for any high reliable and high performance space application, under harsh and radiation environment.
3D PLUS’s DDR3 memory modules are part of a complete DDR3 ecosystem, providing a fully space-qualified memory subsystem solution. This ecosystem includes also:
DDR3 Termination Regulator is designed for use with this memory module to ensure signal integrity and electrical performances.
DDR3 Radiation Intelligent Memory Controller (RIMC) IP core provides SEU enhanced protection and mitigation when implemented in the end user application as the memory controller.
Figure 1: Functional block diagram
Notes:
1. A[0:15], BA[0:2], RESET#, CAS#, RAS#, WE#, ODT0, CKE0, S0#, CK0, CK0#, VREFDQ, VREFCA, GND, VSS are common to all five embedded devices.
2. On the 5thembedded device, the upper byte lane (CB[0:7]), is associated with DM8, DQS8, DQS8#. The lower byte lane is unused and DM9, DQS9, DQS9# must be terminated correctly. Please refer to [RD3] for more details.
The design of the memory module is optimized and includes decoupling capacitors and termination resistors as described in Figure 2 below.
Figure 2: Decoupling capacitors and termination resistors embedded in the module Note: For each embedded device, ZQ pin is pulled down through a 240 Ω resistor.
2.2 TYPE VARIANTS
Variants of the module specified herein, are given in Table 1.
Variant – Part Number Operating
Temperature Range Grade Package Balls Material
3D3D16G72WB2723 CN 0°C to +70°C Commercial BGA 199 balls Sn10Pb90
3D3D16G72WB2723 IB -40°C to +85°C Industrial BGA 199 balls Sn10Pb90
3D3D16G72WB2723 IS -40°C to +85°C Space BGA 199 balls Sn10Pb90
3D3D16G72WB2723 SS -40°C to +105°C Space BGA 199 balls Sn10Pb90
Table 1: Component type variants
Note:
These variants are suitable for automatic reflow assembly process.
Module assembly on board must follow reflow guidelines as defined in:http://www.3d-plus.com/technical-documentation.php
2.3 RADIATION PERFORMANCES
The following generic radiation tolerance data are available at 3D PLUS:
Parameter Description
Total Dose Radiation (TID) > 75 krad(Si)
Single Event Latchup (SEL) > 67 MeV.cm²/mg
Single Event Upset (SEU) Threshold LET > 0.4 MeV.cm2/mg Saturated Xsection: 1.05 10-11cm2/bit Single Event Functional Interrupt (SEFI) Threshold LET <0.4 MeV.cm2/mg
Saturated Xsection: 6.18-6cm2/device Table 2: DDR3 module radiation data without RIMC DDR3
Parameter Description
Total Dose Radiation (TID) > 75 krad(Si) Single Event Latchup (SEL) > 67 MeV.cm²/mg
SEU/SERE/SECE Mitigation achieved by 3DIPMC0744 embedded
ECC
SEFI Immune under 3DIPMC0744 protection
(LET Th > 60 MeV.cm²/mg) Table 3: DDR3 module radiation data with RIMC DDR3
3D PLUS offers the Radiation Intelligent Memory Controller (RIMC) IP IDDR3, 3D PLUS part number 3DIPMC0744, in order to provide enhanced protection against radiation effects such as SEU/SEFI.
This added value, besides proposing a high performing and flexible controller, mitigates 3D PLUS DDR3 SEU, allowing designer to get rid of such constraints, and permits him to focus on his application.
3. FUNCTIONAL DESCRIPTION
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured as 8-bank DDR3 SDRAM devices. DDR3 architecture is essentially an 8n-Bit prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and, CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input/output signals.
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command and address buses have been routed in a fly-by topology, where each clock, control, command and address pin on each DRAM is connected to a single trace. Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR3.
3.1 SIMPLIFIED STATE DIAGRAM
Figure 3: Simplified state diagram
For power-up initialization sequence, reset initialization sequence and Mode Registers (programming and definition), please refer to [RD4].
4. BALLOUT
4.1 BALL ASSIGNMENTS
1 2 3 4 5 6 7 8 9 10 11 12 13
A GND DQ39 DQ37 DQ33 DQ35 DM4 DQ40 DQ42 DQ46 DQS5# DQS5 GND
B VTT VTT VDD GND VDD GND DM7 DQ59 DQ57 DQ61 DQ44 DQS6 DQ36
C VTT VTT DQ52 DQ54 DQ50 DQ48 VDD GND VDD DQ63 DQ55 DQS6# DQ38
D VTT VTT DQ13 DQ15 DQ9 DM1 DQS1 DQS1# DQ12 DQ14 DQ53 DQS4 DQS4#
E VTT VTT DQ11 NC DQ10 DQ49 GND DQ34
F GND VDD GND VDD DQ8 DQ51 VDD DQ32
G VDD GND GND NC GND DM6 DM5 GND
H NC GND DQ2 DQ0 DM0 GND DQ56 DQ47
J NC VDD DQ6 DQS0 DQ1 VDD DQS7# DQS7
K NC GND DQ4 DQS0# DQ3 CK0 DQ60 DQ45
L ODT0 RAS# VREFDQ VREFDQ DQ7 CK0# DQ62 DQ41
M S0# CAS# GND A10 DQ5 GND DQ58 DQ43
N BA0 WE# VDD A15/RFU GND VDD CB3 DQ26
P A3 BA2 GND A12 VREFCA VREFCA CB5 DQ30
R A5 A0 VDD A1 NC VDD CB7 DQ28
T A7 A2 GND A11 NC GND DQS3 DQS3#
U GND A9 RESET# A14 A8 A6 A4 BA1 CKE0 DM2 DM8 DQ24 CB1
V NC A13 NC DQ20 DQ22 DQ16 VDD GND NC DQS2 DQS2# DQ19 DQ17
W VDD GND DQS9 NC DQ18 DM3 DQ25 DQ27 DQ29 DQ31 DQS8# DQ23 DQ21
Y VDD GND DQS9# DM9 GND VDD CB0 CB2 CB6 CB4 DQS8 VDD GND
Figure 4: Ball assignments
4.2 INPUT/OUTPUT DESCRIPTION
SYMBOL TYPE FUNCTION
CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#.
CKE0 Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK#, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE are disabled during Self-Refresh.
S0# Input
Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for external Rank selection on systems with multiple Ranks. CS# is considered part of the command code.
ODT0 Input
On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS#, and DM signal. The ODT pin will be ignored if MR1 and MR2 are programmed to disable RTT.
RAS#
CAS#
WE#
Input Command input: RAS#, CAS#, and WE# define the command and/or address being entered.
DM[0 :8] Input
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. The function of DM is enabled by Mode Register A11 setting in MR1.
BA[0 :2] Input
Bank Address Inputs: BA0 – BA2 define to which bank an Active, Read, Write, or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle
A[0 :14] Input
Address inputs: Provide the row address for Active commands and the column address for Read/ Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC# have additional functions; see below).
The address inputs also provide the op-code during Mode Register Set commands.
A10 / AP Input
Auto precharge: A10 is sampled during READ and WRITE commands to determine whether auto precharge should be performed to the accessed bank after a READ or WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank addresses.
A12 / BC# Input
Burst Chop: A12/BC# is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH: no burst chop; LOW: burst chopped).
See command truth table for details.
A15/RFU Input Reserved for Future Use
RESET# Input
Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD.
DQ[0 :63]
CB[0 :7]
Input /
Output Data input/output: Bidirectional data bus.
DQS[0:8], DQS[0:8]#
Input / Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS is paired with differential signals DQS#
to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.
SYMBOL TYPE FUNCTION
VDD Supply Power Supply and DQ Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage
GND Supply Ground and DQ Ground
VREFCA Supply Reference voltage for command, and address pins.
VREFDQ Supply Reference voltage for DQ[0:63] and CB[0:7]
VTT Supply Termination voltage
NC Unconnected pins
Table 4: Ball description
Note:
1. Input only pins (BA0-BA2, A0-A15, RAS#, CAS#, WE#, CS#, CKE, ODT and RESET#) do not supply termination.
2. DM9, DQS9, DQS9# are not used.
5. COMMANDS
Below is the table of the commands list. For any command description and operation, please refer to [RD4].
Table 5: Commands list
COMMAND DESCRIPTION COMMAND DESCRIPTION
ACT Activate PDE Enter power-down
PRE Precharge PDX Exit power-down
PREA Precharge all SRE Self refresh entry
REF Refresh, fine granularity refresh SRX Self refresh exit
READ RD, RDS4, RDS8 MPR Multipurpose register
READ A RDA, RDAS4, RDAS8 MRS Mode register set
WRITE WR, WRS4, WRS8 ZQCL ZQ calibration long
WRITE A WRA, WRAS4, WRAS8 ZQCS ZQ calibration short
RESET Start reset procedure
5.1 COMMAND TRUTH TABLE
Function
Symbol
CKE
CS# RAS# CAS# WE# BA0-BA2 A12/BC A13,A11 A10/AP A0–A9 Notes
Previous Current Cycle
Mode Register Set MRS H H L L L L BA OP Code
Refresh REF H H L L L H V V V V V
Self Refresh Entry SRE H L L L L H V V V V V 7, 9,
12
Self Refresh Exit SRX L H
H X X X X X X X X
7, 8, 9, 10
L H H H V V V V V
Single Bank
Precharge PRE H H L L H L BA V V L V
Precharge all Banks PREA H H L L H L V V V H V
Bank ACTIVATE ACT H H L Row Adress (RA) BA Row Adress (RA)
Write (Fixed BL8 or
BC4) WR H H L H L L BA V V L CA
Write (BC4, on the
Fly) WRS4 H H L H L L BA L V L CA
Write (BL8, on the
Fly) WRS8 H H L H L L BA H V L CA
Write with Auto Precharge (Fixed
BL8 or BC4)
WRA H H L H L L BA V V H CA
Write with Auto Precharge (BC4, on
the Fly)
WRAS4 H H L H L L BA L V H CA
Write with Auto Precharge (BL8, on
the Fly)
WRAS8 H H L H L L BA H V H CA
Read (Fixed BL8 or
BC4) RD H H L H L H BA V V L CA
Read (BC4, on the
Fly) RDS4 H H L H L H BA L V L CA
Read (BL8, on the
Fly) RDS8 H H L H L H BA H V L CA
Read with Auto Precharge (Fixed
BL8 or BC4)
RDA H H L H L H BA V V H CA
Read with Auto Precharge (BC4, on
the Fly)
RDAS4 H H L H L H BA L V H CA
Read with Auto Precharge (BL8, on
the Fly)
RDAS8 H H L H L H BA H V H CA
No Operation NOP H H L H H H V V V V V 10
Device Deselected DES H H H X X X X X X X X 11
Power Down Entry PDE H L
L H H H V V V V V
6, 12
H X X X X X X X X
Function
Symbol
CKE
CS# RAS# CAS# WE# BA0-BA2 A12/BC A13,A11 A10/AP A0–A9 Notes
Previous Current Cycle
Power Down Exit PDX L H
L H H H V V V V V
6, 12
H X X X X X X X X
ZQ calibration Long ZQCL H H L H H L X X X H X
ZQ calibration Short ZQCS H H L H H L X X X L X
Table 6: Command truth table
Note :
1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock.
The MSB of BA, RA and CA are device density and configuration dependent.
2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function
3. Bank Addresses (BA) determine which bank is to be operated upon. For MRS BA selects the specific Mode Register location.
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
6. The Power Down Mode does not perform any refresh operation.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
8. Self Refresh exit is asynchronous.
9. VREF(VREF_CAand VREF_DQ) must be maintained during Self-Refresh operation. VREF_DQsupply may be turned OFF and VREF_DQmay take any value between VSS and VDD during Self Refresh operation, provided that VREF_DQis valid and stable prior to CKE going back HIGH and that first Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self-Refresh.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose of the NOP is to prevent the dDR3 from registering any unwanted commands between operations. A NOP will not terminate a previous operation that is still executing, such as a burst read or write cycle.
11. The DES performs the same function as NOP.
12. Refer to the CKE Truth Table for more detail with CKE transition.
5.2 CKE TRUTH TABLE
Current state²
CKE Command (N)3
RAS#, CAS#, WE#, CS#
Action (N)3 Notes Previous Cycle1
(N-1)
Current Cycle1 (N)
Power Down
L L X Maintain Power-Down 14, 15
L H DESELECT or NOP Power-Down Exit 11, 14
Self Refresh
L L X Maintain Self Refresh 15, 16
L H DESELECT or NOP Self Refresh Exit 8, 12, 16
Bank(s) Active H L DESELECT or NOP Active Power-Down Entry 11, 13, 14
Reading H L DESELECT or NOP Power-Down Entry 11, 13, 14,
17
Writing H L DESELECT or NOP Power-Down Entry 11, 13, 14,
17
Precharging H L DESELECT or NOP Power-Down Entry 11, 13, 14,
17
Refreshing H L DESELECT or NOP Precharge Power-Down
Entry 11
All Banks Idle
H L DESELECT or NOP Precharge Power-Down
Entry
11, 13, 14, 18
H L REFRESH Self Refresh Entry 9, 13, 18
For more details with all signals See “Command truth table”. 10
Table 7: CKE truth table
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR4 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N),ODT is not included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh.
6. During any CKE transition (registration of CKE H->L or CKE L->H), the CKE level must be maintained until 1nCK prior to tCKEmin being satisfied (at which time CKE may transition again).
7. DESELECT and NOP are defined in the Command Truth Table.
8. On Self-Refresh Exit DESELECT commands must be issued on every clock edge occurring during the tXSperiod. Read or ODT commands may be issued only after tXSDLLis satisfied.
9. Self-Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power-Down Entry and Exit are DESELECT only.
12. Valid commands for Self-Refresh Exit are DESELECT only except for Max Power Saving exit. NOP is allowed for these 2 modes.
13. Self-Refresh cannot be entered during Read or Write operations.
14. The Power-Down does not perform any refresh operations.
15. “X” means “don’t care“(including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins.
16. VREF(VREF_CAand VREF_DQ) must be maintained during Self-Refresh operation. VREF_DQsupply may be turned OFF and VREF_DQ
may take any value between VSS and VDD during Self Refresh operation, provided that VREF_DQis valid and stable prior to CKE going back HIGH and that first Write operation or first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self-Refresh.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered, otherwise Active Power-Down is entered.
18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, etc.)
6. ODT
ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination resistance for each DQ, DQS, DQS#, DM, TDQS and TDQS# (when enabled via A11=1 in MR1) via the ODT control pin.
The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. More details about ODT control modes and ODT timing modes can be found in [RD4], specifically:
• The ODT control modes,
• The ODT synchronous mode,
• The dynamic ODT feature,
• The ODT asynchronous mode,
• The transitions between ODT synchronous and asynchronous.
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown in Figure below.
Figure 5: Functional representation of ODT
This switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The value of RTTis determined by the settings of mode register bits (see Mode Register).
The ODT pin will be ignored if the mode register MR1 and MR2 are programmed to disable ODT and in self refresh mode.
7. ELECTRICAL CHARACTERISTICS 7.1 ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VALUE UNIT
Voltage on VDDpin relative to GND VDD -0.4 ~ 1.975 V
Termination Voltage relative to GND VTT -0.4 ~ 1.975 V
Voltage on any pin relative to GND VIN, VOUT -0.4 ~ 1.975 V
Power Dissipation PDMAX 3 W
Storage Temperature TSTG -55 ~ +150 °C
Junction Temperature TJ -+ 125 °C
Body Temperature
(short exposure only) TBODY + 215 °C
Table 8: Absolute maximum ratings
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM.
3. Voltage on any input or I/O may not exceed voltage on VDD.
7.2 RECOMMENDED DC OPERATING CONDITIONS
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Supply voltage 1.283 1.35/1.5 1.575 V
VTT Termination voltage - 0.5 * VDD - V
VREFCA Reference voltage for ADD
and CMD inputs 0.49 * VDD - 0.51 * VDD V
VREFDQ Reference Voltage for DQ and
DM inputs 0.49 * VDD - 0.51 * VDD V
f Clock Frequency
(DLL On) 300 - 667 MHz
f Clock Frequency
(DLL Off) - - 200 MHz
RTH(J-C) Thermal Resistance Junction
to Case - - 3 °C/W
RTH(J-A) Thermal Resistance Junction
to Ambient - - 5 °C/W
Table 9: DC operating conditions
Notes:
1. VDDQand VDDare internally connected into the module. Same applies for VSSand VSSQ
2. DC bandwith is limited to 20 MHz.
3. AC peak noise on VREF may not allow VREFto deviate from VREF(DC)by more than ±1.0 % VDD.
4. In RTH(J-C)(Thermal resistance Junction to Case), Case is defined as the temperature at the module lateral sides, Junction is defined as the Junction Temperature of the top die in the stack.
5. In RTH(J-A)(Thermal resistance Junction to Ambient), Ambient is defined as the temperature at the bottom of the balls in contact with the board.
7.3 OPERATING TEMPERATURE RANGE
JEDEC 79-3F specifications require the refresh rate to double when TC(case temperature) exceeds 85°C; this also requires use of the high-temperature self-refresh option according to Extended Temperature Mode section.
Additionally, ODT resistance, IDD values, some IDD specifications and the input/output impedance must be derated when TCis < 0°C or > 85°C.
TEMPERTURE RANGE RATING
Commercial 0°C ≤ Tc ≤ 70°C
Industrial -40°C ≤ Tc ≤ 85°C
Specific -40°C ≤ Tc ≤ 105°C
Table 10: Temperature range
7.4 MODULE CAPACITANCE
For the 16 Gbit DDR3 SDRAM module 3D3D16G72WB2723 the capacitance values are specified in the table below: (Ta = 25 °C, VDD= 1.5 V):
SYMBOL PARAMETER MAX UNITS
CCK Input capacitance (CK0, CK0#, CKE0) 7 pF
CIN Input capacitance, (all other inputs) 6.5 pF
CI/O
Input /Output capacitance (DQ[0 :63], DM[0 :9], DQS[0 :7],
DQS[0 :7]#) 2.5 pF
Table 11: Pin capacitances
7.5 CURRENT SPECIFICATION LIMITS
IDDand IPPvalues are for typical operating range of voltage and temperature unless otherwise noted.
SYMBOL PARAMETER MIN MAX UNIT
IDD0
Operating current
One Bank Activate Precharge 410 mA
IDD1
Operating Current One Bank Activate Read
Precharge
520 mA
IDD2N Precharge standby current 240 mA
IDD2P0 Precharge power-down current
Slow Exit 90 mA
IDD2P1 Precharge power-down current
Fast Exit 160 mA
IDD2PQ Precharge quiet standby
current 240 mA
IDD3N Active standby current 330 mA
IDD3P Active power-down current 235 mA
IDD4R Operating current burst read 1075 mA
IDD4W Operating current burst write 1100 mA
IDD5B Burst refresh current 1000 mA
IDD6ET Self refresh current 135 mA
IDD7 Operating bank interleave read Current 1450 mA
IDD8 Reset Low Current 260 mA
ILIL Input Leakage Current Low -1 +1 µA
ILIH Input Leakage Current High -1 +1 µA
ILOL Output Leakage Current Low -1 +1 µA
ILOH Output Leakage Current High -1 +1 µA
Table 12: IDDlimits for module 3D3D16G72WB2723
7.6 AC AND DC MEASUREMENTS LEVELS
For AC and DC inputs levels for single-ended signals, AC and DC inputs levels for differential signals, slew rate definitions, cross point voltage, AC and output measurements level, please refer to chapter 8 and 9 of [RD4].
7.7 AC TIMINGS PARAMETERS
The table below describes module electrical characteristics. The limits indicated are the limits at the end of life of the part, after 75 krad irradiation.
SYMBOL PARAMETER MIN MAX UNIT
tDQSQ
DQS-DQ Skew for DQS and Related
Signals -600 +600 ps
tREF Average Periodic Refresh
Temp range: -40°C to +85 °C - 64 ms
tREF Average Periodic Refresh
Temp range: +86°C to +105 °C - 32 ms
Table 13: 3D3D16G72WB2723 AC characteristics
Table described below is applicable for the basic component embedded in the module.
CL-nRCD-nRP 11-11-11
UNITS NOTES
PARAMETER SYMBOL MIN MAX
Internal read command to first data tAA 13.75 20.00 ns
ACT to internal read or write delay
time tRCD 13.75 - ns
PRE command period tRP 13.75 - ns
ACT to ACT or REF command time tRC 48.75 ns
ACT to PRE command period tRAS 35 9 x tREFI ns
Average clock cycle CL = 5, CWL = 5 tCK(AVG) 3.000 3.300 ns 1,2,3,5
Average clock cycle CL = 6, CWL = 5 tCK(AVG) 2.500 3.300 ns 1,2,3,5
Average clock cycle CL = 7, CWL = 6 tCK(AVG) 1.875 < 2.500 ns 1,2,3,4,5 Average clock cycle CL = 8, CWL = 6 tCK(AVG) 1.875 < 2.500 ns 1,2,3,5 Average clock cycle CL = 9, CWL = 7 tCK(AVG) 1.500 < 1.875 ns 1,2,3,4,5 Average clock cycle CL = 10, CWL = 7 tCK(AVG) 1.500 < 1.875 ns 1,2,3,4,5 Average clock cycle CL = 11, CWL = 8 tCK(AVG) 1.250 < 1.500 ns 1,2,3,4,5
Supported CL settings 5-11 nCK
Supported CWL settings 5-8 nCK
Table 14: Speed bins
Notes:
1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calculated from tAA following rounding algorithm defined in Section 13.5.
3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e., 1.5ns or 1.25ns or 1.071 ns or 0.937 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. Any device speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
For all other AC parameters applicable to the basic component, please refer to [RD4], chapter 13. The corresponding speed bin is DDR3-1600.
8. ORDERING INFORMATION
The DDR3 x48 bit module is available in a variety of temperature ranges and screening levels to address a broad range of applications and customers’ requirements.
The available Quality Grades for DDR3 family are:
«-IB» Quality Grade to address Engineering Models,
«-IS» or «-SS» Quality Grade to address Flight Models.
For more details, please refer to 3D PLUS Website:https://www.3d-plus.com/quality-grades-reliability.php 3D3D16G72WB2723 X X X
Temperature range C = (0°C to +70°C)
I = (-40°C to +85°C) S = (-55°C to +125°C) Screening level
N = Commercial grade B = Industrial grade S = Space Grade Coating (option)
A = Arathane coating M = Mapsil coating
Figure 6: Ordering information
A specific Source Control Drawing (SCD#) reference [AD1] is available for the space qualified product and may be used for its procurement.
8.1 PACKAGING
Figure 7: 3D3D16G72WB2723 mechanical drawing
Note:
Dimensions are in mm.
Solder balls with Sn10Pb90Alloy Standard Metallization:
Weight of the module is 8.90 g max.
8.1 HANDLING AND ASSEMBLY RECOMMENDATIONS
Detailed recommendations concerning 3D PLUS module storage and assembly conditions are available in [AD2].
8.1.1 Packing
Modules are either packed in boxes or trays. Made in polymeric material, these boxes and trays fulfil JEDEC (EIAJ EDR 7602) requirements except about overall height. They are adaptable to 3D PLUS module form factor.
Each box is sealed with antistatic bag under vacuum with desiccant sachet.
Each module is marked as follow:
Figure 8: 3D3D16G72WB2723 marking
8.1.2 Handling
3D PLUS modules must be handled with antistatic gloves and an ESD wrist strap. The use of tools that could damage sides of components is prohibited. Refer to [AD2] for details. See section 8.1.5 herein for specific ESD rating.
8.1.3 Storage
In order to avoid degradation due to humidity, 3D PLUS recommends storing the modules in dry environments (dry sealed bags, dry cabinet).
Storage in sealed bags: The calculated shelf life for dry sealed packed components is 12 months from the pack seal date, when stored in a non-condensing atmospheric environment of < 40 °C and < 90% RH. Beyond this period, modules should be baked at 125 °C for 48 hours.
If the provided sealed bags are opened, please refer to [AD2] for bake-out instructions 8.1.4 Board Assembly
After opening the sealed bags, 3D PLUS modules must be baked for 24 hours at 125°C. The use of any adhesive tape (e.g. Kapton®) on the side of the module during assembly is prohibited. Module assembly on board must follow reflow guidelines as defined inhttp://www.3d-plus.com/technical-documentation.php It shall be noted that recommendations are different for manual assembly and automatic reflow. Module reinforcement, coating and lead tinning operations are also described in these documents.
Module cleaning after assembly must be done with isopropylic alcohol preferentially, or with de-ionized water otherwise. For other cleaning products, please consult 3D PLUS for further information.
8.1.5 Electrostatic Discharge Sensitivity
In order to avoid ESD damage and to guarantee reliable assembling of the 16 Gbit DDR3 SDRAM module, 3D PLUS methods and instructions for ESD protections or equivalent must be applied.
Human Body Model Classification (JS-001-2014) is 2000 V.
9. REVISION HISTORY
ED./REV. DATE
(MM/DD/YYYY) DESCRIPTION
1 07/07/2020 First Release Datasheet
2 11/18/2021
Change of document model
[RD4] added. Now refering to JEDEC standard JESD79-3F.
Updated Module capacitance table.
Table 15: Revision history
10. 3D PLUS SALES OFFICES
HEADQUARTERS (FRANCE) TECHNICAL CENTER (USA) DISTRIBUTOR 408, rue Hélène Boucher - ZI
78530 Buc Tel: +33 (0)1 30 83 26 50 E-mail: [email protected]
www.3d-plus.com
151 Callan Avenue - Suite #310 San Leandro, CA 94577 Tel:
(510) 824-5591 E-mail: