An Efficient Technique for Linear Interpolation using Adders

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, UGC Approved List of Recommended Journal, Volume 8, Issue 5, May 2018)

218

An Efficient Technique for Linear Interpolation using Adders

Froyd Aslan V F

1

, Akshay Kumar

2

, Malcolm Nicholas Andrade

3

, Pavan S Vernekar

4

, Mahesha Y

5

1,2,3,4_{Dept. of ECE, SJEC, Mangaluru} 5_{Assistant Professor, Dept. of ECE, SJEC, Mangaluru}

Abstract

—

The simplest form to reconstruct a set of data by sampling can be done using interpolation. Interpolation is nothing but prediction of missing data in order to complete a sequence. The conventional method of linear interpolation uses the multiplier based linear interpolation (MBLI), where multiplier and divider are power- and area-hungry operators. In this paper an efficient method of interpolation using the adders are proposed to emulate the behaviour of a conventional linear interpolation. By comparing the conventional and proposed method we obtain the result that adder based approach utilizes approximately 8 times less area and power respectively.

Keywords— Interpolation; Multiplier based Linear Interpolation (MBLI); Adder based Linear Interpolation (ABLI); Low area and power;

I. INTRODUCTION

Information existing in the natural world are often transmitted and received as arbitrary continuous signals. These arbitrary signals are periodically sampled for further digital signal processing (DSP) to achieve better performance (e.g., noise cancellation, or sharpness) or to accomplish specific functions (e.g., image scaling, and audio processing). Interpolation is one of the most fundamental operations of DSP for reconstructing original signals from a set of sampled data for further processing (e.g., re-sizing an image, or smoothing audio data, compression and decompression of signals).

Interpolation is a mathematical procedure for supplying intermediate terms in a given series of terms. Interpolation is the process of introducing new values into the original data. It is also known as up-scaling or resolution enhancement. An effective interpolation method does not include any complex structure or image. There many kind of interpolations based on the size and complexity of the equations and variables such as linear interpolation, Piecewise constant interpolation, Nearest neighbour interpolation, Spline interpolation, Polynomial interpolation.

The linear interpolation provides better quality than the nearest neighbour interpolation. As the order goes on increasing the computational complexity also increases. Linear interpolation is used to acquire data at specific points with selective sampling mechanism. Linear interpolation reduces the number of multiplications with a slight increase in the number of additions.

There are different algorithms for linear interpolation. least error integral linear interpolation where the recurrence formula is used for the calculation [1], multiplier based linear interpolation is the most common method used for linear interpolation, rounding-up and rounding-down integral linear interpolation instead of exact points it rounds up the interpolation point to the smallest near value, double-step line algorithm improves the Bresenham's algorithm, horizontal run-length line algorithm deals with the pixel values of an image[1], Linear interpolation algorithm using pattern weight uses the nearest interpolated values whereas in conventional method it considers the nearest pixel or point values [2] etc. In all the algorithms the common problem is either multiplier or divider is used which consumes more area and power when compared to the other components.

Most of the algorithms uses multipliers and dividers which consumes more area and power. In this paper an power and area efficient method for linear interpolation is proposed but at the cost of accuracy in the final output which can be tolerated in the digital signal processing applications.

II. MULTIPLIER BASED LINEAR INTERPOLATION

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[image:2.612.60.299.144.329.2]

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Fig 1. The basic concept of conventional multiplier-based linear

interpolation (MBLI).[3]

The MBLI is implemented by shifting the interpolation function h(t) to the position at which the peak value is aligned with the position of the data to be interpolated[4]. The formula for Yk cab be simplified as one of the expressions:

yk = x1 + ( x2 - x1 ) * ( d1/d), (1)

or

yk = x1 + ( x1 - x2 ) * ( d2/d) (2)

[image:2.612.328.558.431.700.2]

Where d, d1 and d2 represent the position distance between x1 and x2.

Fig 2. Block diagram for conventional MBLI.[3]

The hardware implementation of (1) is shown in the Fig. 2, requiring one subtractor, one signed divider, one signed multiplier, and an signed adder.

III. ADDER BASED LINEAR INTERPOLATION

Since the conventional MBLI uses more area and power an area and power efficient adder based linear interpolation technique is proposed. Many digital signal processing applications can tolerate small distortion. The proposed method also contains a small distortion or error in the final value which can be tolerated in the DSP applications.

If the values of d, d1 , and d2 in (1) and (2) are approximated to a value of two to the power of k, the complex division and multiplication in (1) and (2) can be substituted by the simple subtraction and shift operation. The formula for Yk using ABLI is shown below,

yk = x1 + ( x2 - x1 ) >> { ATPKd - ATPKd1 } (3)

or

yk = x1 + ( x1 - x2 ) >> { ATPKd - ATPKd2 } (4)

The 8-bit numerical example shown in Fig. 3 demonstrates the design concept of proposed ABLI, where six steps are annotated.

[image:2.612.49.284.516.711.2]

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In the first step the two distances d1 and d2 are compared and the nearest distance to the yk is selected. In the step two xdiff is calculated. In the step three the ATPK’s of total distance and the nearest distance to the yk are calculated. The difference of two ATPK’s are calculated in the step four. In step five the xdiff is arithmetically right shifted times equal to the ATPK difference. In the final step this result is added with the x1 to get the missing value yk.

IV. HARDWARE IMPLEMENTATION OF ADDER BASED

LINEAR INTERPOLATION

Hardware implementation of the proposed ABLI is described in this section, where the ATPK estimator is designed to search for the most significant one bit (MSOB) and second significant one bit (SSOB) is first introduced.

The main operation in the proposed ABLI are the approximations of d1, d2 and d to the approximations of the values to the power of K, i.e., 2K.. An ATPK estimator is designed so that the multiplier/divider of the conventional MBLI can be simplified to shift and adder/subtractor operators in the ABLI.

The main component of the ABLI is ATPK estimator. The ATPK estimator can be further partitioned into two parts, ATPK locator and a simple binary encoder. Where ATPK locator identifies the MSOB and SSOB for the given inputs and binary encoder encodes this value. Taking 13(4’b1101) as an example, the ATPK locator outputs 5’b10000. Then the output of the encoder will be 4.

The equation for the ATPK locator is shown in Fig. 4,

[image:3.612.324.564.143.354.2]

Fig 4. Equations of ATPK locator.[3]

Fig 5. Circuit implementation of 4 -bit ATPK Estimator.[3]

The hardware implementation of ABSI is shown in the Fig. 6, where x1 and x2 are inputs,whereas d, d1 and d2 are input distances. The system flow will be similar to the steps explained in the example.

Fig 6. Block diagram of linear interpolation using ABLI.

[image:3.612.323.563.424.703.2]

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V.HARDWARE IMPLEMENTATION OF THE PROPOSED

ADDER BASED LINEAR INTERPOLATION

[image:4.612.324.563.148.376.2]

The proposed method of ABLI contains the same components except the ATPK estimator. In the proposed method the ATPK estimator is synthesised using the simple priority encoder. The truth table of the priority encoder is shown in Table I. In this method complexity in finding the MSOB and SSOB is less compared to the ATPK estimator using the combinational logic. Comparing the ATPK estimator using combinational logic and ATPK estimator using priority encoder, the area and power consumption of ATPK estimator using combinational logic is more compared to other.

Table I

Priority encoder truth table

INPUTS OUTPUTS

D1 D2 D3 D4 D5 D6 D7 Y3 Y2 Y1

1 0 0 0 0 0 0 0 0 1

X 1 0 0 0 0 0 0 1 0

X X 1 0 0 0 0 0 1 1

X X X 1 0 0 0 1 0 0

X X X X 1 0 0 1 0 1

X X X X X 1 0 1 1 0

X X X X X X 1 1 1 1

The circuit implementation of the proposed ABLI is shown in the Fig 7,

Fig 7. Circuit implementation of the proposed ABLI.

VI. SIMULATION RESULTS

[image:4.612.49.290.326.544.2]

The above system was synthesized using the verilog code. And the codes are simulated in the cadence ncsim software and results are listed in the Table II.

Table II

Comparison of specified and accomplished parameters

Para meter

Interpolato

r -

Convention al method

Interpolator

- ATPK

Estimator

Interpolator -

ATPK using

Priority encoder

Area (um2)

8848.21 1483 1129

Delay (ps)

61931 6974 6178

Power (nW)

1746200.00 0

[image:4.612.318.571.490.624.2]

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The above result shows that linear interpolator with ATPK estimator using priority encoder uses approximately 8 times less area and power compared to the conventional linear interpolation. The accuracy of the system will be with an error of approximately ∓0.5%.

VII. CONCLUSION

An efficient technique for linear interpolation using adders was proposed to reduce the hardware complexity of conventional multiplier based linear interpolation while maintaining the interpolation quality. The simulations demonstrate that the proposed ABSI using the ATPK estimator using the priority encoder consumes less area and power when compared with the conventional method.

Acknowledgment

The authors would like to thank St. Joseph Engineering College of Mangaluru for providing cadence tools used in this work.

REFERENCES

[1] “An integral linear interpolation approach to the design of incremental line algorithms”, Chengfu Yao, Jon G. Rokne, Department of Computer Science, The University of Calgary, Calgary, Alberta, Canada, T2N 1N4 Received 28 June 1997; received in revised form 12 May 1998

[2] “A New Adaptive Linear Interpolation Algorithm Using Pattern Weight Based on Inverse Gradient”, Joohyeok Kim* and Jechang

Jeong, Division of Electronics and Computer Engineering, Hanyang University, Haengdang-dong, Seongdong-gu, South Korea *kjh76363@hanyang.ac.kr

[3] “An area and power efficient adder-based stepwise linear interpolation for digital signal processing”, Chung-Hsun Huang; Chao-Yang Chang IEEE Transactions on Consumer Electronics Year: 2016, Volume: 62, Issue: 1 Pages: 69 - 75

[4] “Why Linear Interpolation?”, Andrzej Pownuk, Vladik Kreinovich, University of Texas at El Paso, ampownuk@utep.edu, vladik@utep.edu, Technical Report: UTEP-CS-17-20, To appear in Mathematical Structures and Modeling, 2017, Vol. 43.