929494 Micromemory 7405 Add on Memory System Nov77 pdf

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MICROMEMORY 7405

ADD-ON MEMORY SYSTEM

11

lnformation contained in this Technical Manual is disclosed in confidence and may not be dupli-cated in full or in part by any person without prior written approval ot~the Memory Products Division. Its sole purpose is to provide the user with adequately detailed documentation so as to efficiently install, operate. maintain, and order spare parts for the equipment supplied. The use of this document tor all other purposes is specif· featly prohibited." ..

ELECTRONIC MEMORIES & MAGNETICS CORPORATION

12621 Chadron Avenue. Hawthorne. California 90250 I Telephone: {213) 644-9881

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This manual contains

informatic~~

_

r~q~ired

to install

1

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operate, and maintain the MICROMEMORY

74~5

Add-on

Memory System

1

part number 929494

1

manufactured by

Electronic Memories and Magnetics Corporation,

Hawthorne, California.

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This 7405 Memory System is self-contained

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with memory

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!-:-:~:-:--·

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power supply and interface electronics_ for complete

...

~pmpatibility

with PDP-:11 Computer Systems. manufactured. _____

.

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by Digital Equipment Corporation,

~aynard,

Massachusetts.

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1-1.

GENERAL

10

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11

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1-~·

The MICROMEMORY

7405

Memory System consists of an Electronic Memories

12

_{I standard. chassis containing one to four}

_32K

_x

_16*

_{MICROMEMORY 3000QD ·cards,}

13

I

14

1

l

a

~ower

Supply and a special UNIBUS-adaptable Interface Card.

Switches on

f~

I.

f

the Interface Card can be set to designate the Memory System for operation

17 f

~within

an address block recognizable by the Computer.

18

I

!

! ·, ;· ic1 ~:.: l ~~:.: l'.' ;?·;_:;.l. 1_ ? -?1 c2

19 ; ! 1-3.

The Memory System is modularly organized in

32K

sub-blocks with each

I • .. ·~. . . . . ., . . . . . . ·~ .!..., • . . . . r

2 0

I

Memory Card constituting one._ sub-block. · Thus, the System can be populated

2" I I . .

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iii.COrrespOilciiiiii

illCTenifl~tS·:--·Tiibie

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ii1dicates system VeTsiOi15 based On

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nuniber of Memory Cards and,

-~,~;ic:~~j~;;;~ f~~i~e

1-1

illustrates Card

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and Power Supply locations.

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27 t

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1-4.

POWER

SUPPLY ·1

?8

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2

₉

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1-?.

The Power Supply is capable of supplying all necessary de operating

30

I

1 1

vo~tages

for a full-populated Memory Module.

The Power Supply also provides.

31

I 115

·vac t'o the cooling fans located within the Memory Module.

For detailed

32

33

I

de~c-ription

of Power Suppi'y see Technical Manual TM929219.

34

I

I .

35 36

37

38 39 40

41

42

43

44

45 46 47

48

~9

~1

52

I 1-6.

MEMORY CARDS

I

I \·!id th for l

~111

Page

I

I 1-7 . ..,

-~Each

.Memory Card

.i.~

.a .complete

32K x

16 (or

18)

memory subsystem on 'a

I I .J.J ~ l.;. - - · ··"·-- •• .;; • - ... - • ..• • - ... 1. • .1. ._ . . .

I

single printed wiring board, including semiconductor memory array and support.

·:

el~ctronics.

'Refer to Technical Manual

TM929162

for description of the Memory

1

card. -

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I 1-S.

INTERFACE CARD

I

.

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1-9. The Interface Card is a buffer/controller unit installed between the

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PDP-11 UNIBUS and

th~ M~mory

Cards that constitute the Memory System.

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L::~;n::e~b ~o:~ w~en

parity

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~~9r~1pl._1_N_o_._( ... E_'..,_1c_!r_~_Paqc) Pn})J.ico tion No. Par.agraph No. (Ocld Paqe)

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1J10. CAPACITY ·.~' i.1·:.;t Linc of 'J'<~'~t: ot- 'I'~1ble Ti.tJ e

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;~·~ :::.:.-.·..:·=-· :~-::.:.= -.:.-:::-:.::.-:-.::..:-:: ;.-::::::-::.-:;-·.;:.-:~-:,~-=--;.;-~:.~ .;.~.~-..::-~-:::::;· ~.--. .-;.-:-_-:::.:-:.-:::.:-:::;;.:-;..~--~..:.:=-= -:::-:.=:..-=---=--::::-;::;-;::::--

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1--11. The Interface Card can pTovidc buffering and control for up to 124K :

4

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1 "· ·:·; .. -.:~~..:.::::-:. ·:.-::;::~-~; :.. =.:..~·,: . . - · ;~. ~· _.:.:.: ·~.:=...:..-~:-~.-... .c..·.: • .-:.-: ~ ... ; .... ··• · -.. - ·;-. • •. •. _:-;; .. ·.·.- . ·-:--... ;.;.-. ~-=· -:;~--=:.;--..;,-:.:::.::-:: :-::-.. ::;;:::.~=::~·~-=;.:::-.:=-~.:;.;.;.:-::;. •

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ltbit words ;(including two p:_rity_ ~its)__:>~~~~-48K 9-bit bytes, depending on

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o~erating mode.

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1~12.

MODES OF OPERATION

9

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10 1-1.3. The Interface Card can accommodate the Memory System for operation 11

12 13

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iri the following modes:

f

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ACCESS TIME

Read/Restore Word,

Clear/Write Word,

Exchange Word (Read/Modify/Write)

Read/Rest9re Either Byte.,

.,

.Cl ear/Write Other Bytes

·'-'-""-"-• :.

--

... :.. _ ... _ ,,. ' . ··~ \.'. ...

V~=tical IlJustration

!-.. 1-.15.--·-Access and cycle times are as follows:

--·----·-¥

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l-'16. SYSTEM OPTION

t

Access Time

Acc.ess· 'Time with parity - ·':ion

Cycle Time

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1-17. The Memory System can optionally include pTovisions for checking and

sto:r.:_~.~~- t~? pal:'i ty _bi ts_ ... W~en this option is included, each MemoTy Card must

. J _,

include two extTa bit storage capacity.

_{i ... - - .. -· ·- . .. . .}

_.

Card capacity must be 32K x 18~

t

1-18. SYSTEM SPECIFICATIONS

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1-J9. A sununary of -Memory System spec1f1cat1ons

t

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is contained in Table 1-2.

f ~ J. • ;-~) ,,."\ ;~ ~ 1 .. -. -~--r·· , '. .. , . I 1 • ~ , : :_-l- -: .'. -~ • ~~ ~) r,

Fo·r details of Memory Card specifications, see Technical Manual TM92864 7. ·

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MEMORY CARD 0.

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MEMORY. CARD 1

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MEMORY CARD 2 ;;·:· ·;·'.'.: SUPPLY

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MEMORY CARD 3 t

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Figure 1-1. Memory Module Component Location

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Vertic~l

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Table

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Memory System Version Chart

·I . I t

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VERSION

f MEM~RY CAPACITY

I

Chassis

with I/O

and Power Supply

I

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12 8 K x , 18. bits . -, L

1 , , p _ a e

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:

.L"J8..L.'='·L~ ... ;.. .I.' . J . .L - d :J

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96·K·-.-·'·1·s···b"t _,

_··X ₁ _{S···~·-··->}1

~~--t,-':":..._i·on

_{-J ...}_~

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•1-r-l

.64K

x 18

bits.

-I

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Width f:).t· Ful_l Page

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CARD

LOCATION

*

A B

c

I

I M M

I

I M

.M

D

M

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T

f

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M

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32K_.~ 1_8 .bits . .1..· , uC"t,~':)t~on I M

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.u ('.\ " ... _, ... ~· ' ,_ .L. ..L ~ .I. ._. ....

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NOTE: ·1

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'1 _I

= Interface Card P/N

I _929402-002

I

:

.. M

=

Mem~ry

Card

P/N

928647-305

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11

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17

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ITEM SP.£! ion

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SPECIFICATION i :

4

Type of Memory

Random Access NMOS

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·capacity per Memory Card:

_;2;~~?_ I>.£9"S.:... .. ~~~~~-!:..

: ·1·

Without ;Parity

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1 With

Parity

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MJdes of .Operation

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f

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32,768 16-bit

Words

32,768 18-bit Words

Read/Restore

Clear/Write

Exchange Word (R/M/W)

i·;icJth f,.)r :t'~ Re-~diRestore

Either Byte,

Vertic.:l 1 I 11 ·~~~~~!/~~!.?- ~e

Other Byte

1. .

' Timing: ··--

---,.---~~·----

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...

________

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Read Cycle

He ig1~t £or FuJ.1 Page

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Cycle

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Exchange Cycle

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Landscape

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Access

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Access (with parity)

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1 L~g~.~--:.~~V:e~ls_.:_,_::,r Full Page

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v~P~fi.c~~ Il.lust2:-atio.n

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ONE

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AC Power Requirement -.-.

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Current '(amps)

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+2.5

to

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0.0

to

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volts

115

volts

±10%

8

amps

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2-1. INSTALLATION D-r:'.:)p ~';~(r'~ r1,cxt

--~-

... --.rl--...

..---10

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12-?.

CHASSIS 12

t

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12-~. Install Memory Module (Chassis) in EIA standard 19-inch rack-type

~St

I

cabinet as close as possible to the parent computer

(PDP-11).

Secure the

:: I

I .

i 6 ; . {chassis at the front panel, using four S/ 8-inch 10-32 pan-head screws. 17

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f 1

- i

18 j· j2-4. MEMORY CARD ASSEMBLIES

1 C: ! ' t

2·c;

!

I

2-~.

As required install Memory .. Card

Ass-embli~·5'.

·iin

card slots B thru E.

'),

:

,_ ... i

1 Cards

22 ! '

must be inserted with component-side down.· · lf fewer tha:n···four-·cards· .. <

2 3

l

I

are inc 1 uded in Memory

... I 1 l

L. ~ I I l

7 1

i2-6.

_{INTERFACE.CARD}

..

System, populate slots

in

alphabetic order (B thru E).

T..:J r; 1::· ::; c.:~ .~·-::; I .-Li. '..J_stra ·~ion

~I:

27 f 12-7. Preliminary Procedure

25 t

I

.

~9

I

:2-8.

Prior to installing Interface Card in slot A, this Card must be

ad-~O

₁

lju~ted

for operation within the user-assigned memory range (Memory block).

3

_~

I

lAlso,

~Tf -p~r{i:y

'opti;n is-. in'cluded, the assigned parity register address

~31:.-

₁

1 _{mu~.t 'it,-e·-;~t.-~}

_-·

_{T~ ._a-c'compi-i~h}

_{this, set switches Sl and}_S2 _{as required per}

3_,-::.-;

~~ !Tables 2-1 and

2-2.

36

I ·

i

:ridth ::er f'ul.l Page

37 · 12-9. Procedure __ . _, . .

38 1

i

1,'-:n.::.t~:><...:·.-~ .:: .!..Ll.us-,.:-.r;::;tion

39 12-10. a. Turn off computer de power.

~~

;

b.

Co~nect·UNIBUS ca~le

to any available UNIBUS slot in the computer

~~

I

42 I mainframe or extension chassis.

43 I

I

c.

Connect other end of UNIBUS cable to connectors J3 and J4 on the

44 I

45 I Interface Card. The A section of cable to J4; the B section to-. 46 : J3J (Interface Card connectors are keyed to present incorrect

!

47 I t

I

48 1 cab,le installation·.) 1

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_

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I

"

I

l t

~-[

devices, connect the adjacent peripheral device to Card

conncct~rs

52 JS· and J6 usin·g ·another UNIBUS cnblc;-otherwise-,,-goto-~ftcp-E-.

-s

3 - . . ' '. (-· _. ~·-~-·, _.;...1 ·_, _: : __ , _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___.

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f. See1

Figure 2-1 to verify connections. .

!

4

7

I

g. Install Interface Card in Memory Module slot A, component side down.

8 I

9

!

h. Plug Memory Module AC line cord into suitable AC outlet. AC line

10 I

I

power available must be 800 VA minimum ..

11

I

1

12 12-lL MEMORY VERIFICATION

13

I

,·

ltl i2-12. Verify Memory Module operation with diagnostic routing in Computer

j

1.5

i

~Reference

Manual.

15

I

i-:

₁ I

'!

1

2-13. OPERATION 18

19

I , I

20 ~ 12~1~. Except for Power. Supply AC turn-on, ·the Memory Module is operated 21

l

·automatically by_ the parent computer. See System Power Supply Technical 22

!

'.Manual TM929219 for details of Power Supply operation.

2 "2 l i

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7

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(3- l. GENERAL J)~:-on l"::IC1C' '.r.1.?>:t

I

f

---·'--'-·--·--·---

...

---...

j3-2.- This section describes opera.ting theory of the MICROMEMORY 7405 Memory

I

~ys~em.

Descriptions are.keyed to appropriate figures in this section

~d·

. jthe: Interface schematic drawing in Section V. Detailed functional descriptions

!of '.the Memory Card and Power Supply are contained in Technical Manuals TM944709 I .·

:and TM929219 respectively.

I

.

~3-3. MEMORY SYSTEM

l

'3-4 •.. -.The Memory System (Figure 3-1) consists of up to four 32K x 16 Memory

2 '} ·j '

~ I :cards and an Interface Card that adapts the System to the PDP-11 UNIBUS. The

23 i l .

24

l

isystem can optionally include provisions for parity processing.

2··' I ·

t

~ !3-5. ADDRESSING 27

i

I

!

2s 1· !3-6. It requires 16 bits to address 124K-words of memory. The PDP-11 generates

2q

I! I :

~~,

;i1

bits. Of these, Address Bit

AOO

is used as a control signal, Bits AOl thru

..:>U;

3; I ~15 are used to access a selected Memory Card, and Bits A13 thru A17 are used

~

U

:to

~e'~

ic\}he

Memoi-Y Card .

~o;._,

access . The Computer address scheme is based on

~~ 1 ~he~17-bit word; however, in the Memory System, Address Bit AOO is excluded

:::.: i I I :

,:,::.1 t '.from ."t:he Memory internal addressing scheme; but, in conjunction with control

3 6

i

I ; .i .l .. I • .:. • .;. · - ' · ..:..· •• • . . . - •. . - ...

37

l

~ignals CO and Cl control the operating mode of the Memory System. Figure 3-2

33! I : _,,:_._;_:.~: .. ··. ___ ,.: . . -.-~ ... -) . .:.

3CI

!

f

llµstrates Address Word configuration: external and internal.

1~

1

:

I

1 ··

42 I EXTERNAL 17 16 15 14 13 12 11 10

43

I

I i

44 JINTERNAL 16 15- 14 13 12 11 10 9

9

8 8

7

7 6 5.

6 5 4 4

3 3

2 2

1 1

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45 I

4 6 : 32K CARD INTERNAL- ADDRESS . I

47 I . 1

:i~

:

;;CARD SELECT' . . CONTROL

SIGNA~I

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4

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- ··- ·-·- . -· . - -··--· . .

: '

i 4

6 I !specific Cycle Initiate signal (RP) which starts a memory cycle in the selected

~-

lca~d.

The circuit can be set by switch S2 to start generating Cycle Initiate'

1

5

I I . . l 6

9

I

!signals at a certain address, ... t~~s_, ___ ~et_!i.ng ___ ~l:~ starting address of the Memory

i~

lsys

1tem. These starting addresses occur in 4K increments between O and 94208 :

12 !(internal address). The upper limit of the address block is-determined by

th~

13 '. i

1 _""/\-'. {number of Memory Cards in the System. _l _\ _• The maximum address from the Computer .. ·

1is ,126,956 (24.K). (See Table 2-1 for starting address versus switch setting.

15 16j

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I

19

!

20 \ 21

I

22 l 23!

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24 I 2:> ' ,.... i

2~

2...., I I I

281

29 3ol

311

32

33 35 36 37 38 39 40

41

42

!Note that the octal address is based on the Computer (17-bit) address.)

I !

13-9:.

MODE CONTROL ~·;3_c:th :'.:o!:'

::·-..-,:l

Fc..~ 9 e

f3_1;0. Operating mode is

d~t.:~l~:l b~ lih·~:t·~=-~2

control signals AOO, CO lan.d

·c-i-:-·-Th~~-~ -~od~s

...

;~~--d~-~·ig~;t~d

Word

Mo·d-~. ~~~«i" _-'Syt~ --~1ode-, ·-~i-th -~--;~·b-~~de

,,

:of the Word Mode being

Excha~ge

Mode. , !"od<c._ontro?, to the Memory Cards is a ;

ifu~?tion of Byte Control Level signals 1 and 2 (BCLl, BCL2). Table 3-1 indi-,

jcat

1

es control versus mode. i:

I

: 1:

I

Table 3-1. Mode Control

I

Height for MODE.,_

Vertical Illustration

::

..

or

Rl/W2

w·i~YJ:~ .L:or Full Paqe . -Wl/R2

Landscape

Illustr~tion

WORD t READ

WRITE

Cl

0 0 0 l CONTROL

co

0 0 1 x AOq 0 l

x

BYTE CONTROL

8CL1

BCL2

1 0 0 1 0 1 0 ·l I I

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I

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I

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NOTE:

~·

0

=

low; 1

=

high

~

45 • Exchange

=

Read followed by Write in Word Mode

I

46 I

47 I

'1-8 '3-1 • INTERFACE CARD DETAILS 1

1

49 I f . . .

50

~-1z:·

-The J.nterfacc · Card-1s-· essentially

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arid-~

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er~._

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Orlcl P:1<·~•' No.

---~·---

----M--\ i" \ 7 8 9 10 11 12 13 14

15

16 , ..., J.. I

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i3-14. Data and Address are conveyed to/from Memory by rccei vers/dri vers in ' \

~

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H~~~'::Addr~- Bi~~_-,;i; th;~='A17 ·c-t~~:i-;i';'";~;~:

I :

6 ·1 IA16) are processed by Memory Card Select and Starting Address Control (See:

..

I

~

I

:Fi~ure

3-3) to select a Cycle

-~nitiate

signal RPOO thru RP03.

,

lO !

13-15. Memory Card Select and

Sta~-ti,~g· .Add~~~-~--

Control

i 1 I !

12.._ -

I l3_

I I i'6. .·

13

I

;add.er

Memory Card.Select and Starting Address Logic consists of a binary

U48, a 1/8 decoder U54, switch S2(1-4) and peripheral circuitry. Switch l" ' '

1 ~

!

~2.is

set to the complement of the desired starting address. When the

start-.,.) I I

16

I

Jing address occurs, the complement added

io

it always equals 0000. The most

~~

i

~ig~ificant

bits E4, E3 are applied to the decoder, which generates RPOO to

J.~: ; ~scl ect Memory Card 0. Subsequent addresses above the starting address add· to

;~

!

~the

_

_:~itch-_set ~!1p~t-

and J>:C:a:ise on,ly the

most_~-i~~~~ic~n

..

~

_

01:1.~.P-~~. -~-~-~~._.a.r~.

- - l

22 ! '.used, RP changes in increm~?~~ .o.~ 33~--a~o_ve the .s~~arting address. (See

23

l

_!Table _2-l_{for starting address versus switch.}

set'.t~ngs.)

2 (

i

1 . . .. ·-· .. . : .:. .;,. ~ ..L. • • . - ·'- •;.._ -· •• - ••

2 ~ . ' ( · ) I

2~'

;s-17.

PARITY CONTROL Optional •' t I

27 I ' ; . I

l

28

I

0-1p.

Parity Control provides incoming data with a parity bit and checks ..

out-)o

!

!going data for correct parity. The circuit includes an address select circuit

3?

l

:that can be set by switch Sl(l-4) to activate parity when instructed by the

3 l i l - :· .. i -·.·." ..:.. . .- . . . . . ., - -·, - -~ ..

32

l , ..

~Computer~· ·.The Computer instruction is conveyed by Address Bi ts AOl thru Al 2

~~

r

,

1

_{cint~;naTA'oo 'th~~·A1i)··~p~1i'~d}

to Par_ ity Control. Low order Bits 01 thru 04'

).:.!· I , · .

3S

1 _l(i~~ernal

AOO thni A03) are compared:to switch SI settings to provide the '. 36

37

n

i2

..

,

t "T

., .

..

I I -., .'. .--'. • . - •. •" ' - • • .. . - ~

jpar~ty ·select control· for the Parity-Word Multiplexer (U24, U25) and Register

l(U

₃

~/-'l.J

₃

6): c:~r;·,a

Zll ubtru tion

I

t.

I _ i

~-19. In even~ of a parity error in a Read word, the Parity Gencrator/Che6ke~

I

!

1(Ul 7, U18) generates a parity error flag,, PB, whi"ch is sent to the Computer. J

I . - i

l1n response the Computer executes a trap t() location 114 or 116.

I

l !

(See·PDP-llj

I . . '

J

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I

rrocessor Handblook for deta:ls of Computer Operati.on.)

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... -- ... _ ... __ _.. ___ ...

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-.~--I.in e 0 f •rc:d:

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Even P.:1qc No. Center P:1q0 tro. Ocl cl P -~' <"T t; N n .

5

6

7

8

9

10 11

..

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.L-<

14

15

16

17

18

19

20

2l

22

23

24

25

26

27

28 29

30

31 32 33

34

35

(14)

:::~:.--.,

--- 'l'Exrr

w:nnn

ODD Pi\GE

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Pt1r.:11y.r·.:1ph No. (Evc~t! P._1g0) PubJic:JL:ion no. P •. 1r(·Hrraph No. {Odcl P;:-Hlf')

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40

41 42 43

44

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.Lk~_INTE~~~~~~-

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14-1. PREVENTIVE MAINTENANCE . : '.., p :-; ~-: :-:: 'l'o~\:t

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i

. ·-·

.. -

~---.:.·----~---·-·

,

14-2.

Preventive ~aintenancc consists of inspection, and cleaning as required'.

IHo~ever, only cleaning of air filter should be done periodically. Inspectio~

1~ncl

cleaning of major

com~onents

(circuit board assemblies) should be done

!only when the system MUST be shut down for corrective maintenance, and then,

i .

ionly on a circuit board that MUST be removed.

I

~

:· · :.

6 :: : ~ .-:·:::, r ... -. .,_, .:. J. :-:-> .J qe

14-3. INSPECTION AND CLEANING

I • · · · - . -. -1 -, •

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.

.~

-

-..lL,.-: l .:. .,_ ... ~s·'..:.:i..~~" t.1on

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~.~-~ystem_ A~r .. F:ilte~·-·-·u ... ,--~--- or. -·ft·---~--·----·---·--1

...

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' i : . - ~ -- - --· ' - ....•.. ,

14-5. Dependent on atmospheric dust conditions, and as periodically required,i

! in~_pect, remove, and clean sy'stem air filter as· ·follows: I

1 . : Ii

I J a. Remove System front panel. ,

j I

i

b. Hold panel with dirty side down, and tap gently to loosen ,

I _

accumulated dust particles. . J

c. Remove dust with vacuum cleaner, or by immersing in clean 1

!

water.

I

1: c i g·n •- 1 --- -.- : '· • · · p ;=i rr r·

f

• "'d~

_

~~s

__

applicable, cshake out water, dry panel and filter, and · Vei t.J-re1nstall. ·~~.~· ..L ~,~:

I J ·

r:·~

'4-~. B~s~plate.Connectors

I ·

I

Widti1 icr i·'uL. ;.'a:~iC:

14-7_ • ., Only when Memory Card MUST be removed, inspect and clean baseplate

I , .... 1 . . . .,_ . . .L- •.. ·- ·- ... . .. - _, •.•••..•••

!connectors as required:

I :

I

a. Saturate Memory Card contacts with contact cleaner.

'

l I I I I

·I

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l

f

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. I

I b. Insert Memory Card into and remove from baseplate connector. t

~

i.

WipJ

Memory Card connector clean with soft clean cloth. :

I I

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t CAUTION I

I I

I . · , I

IL Inserting anything into baseplate connector except PCB I

- - - ·could damage contact surface or change contact pressure·.-·-

··-·t ..

J

4 5 6 7 8 9

I 10

11 12 13 1'1.· ,15

16

17

18

19 20

21

22 23 24

25

26 27 28 29 30

31

32 34 3S

Sn·· -, Never insert anything but Memory Card into baseplate

j

5 5~~--:::::::::_c_oo_n_e_c_t_o_r_.··---

_{.., -} _L:

-,----··-1 _ _ _ _ _ _ _ _

l ~-: t - - - -L i I l 0. C' ! 'J' (' :-: t.

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(15)

· 1.,..~·-"'-.

· - - - -

rrEXrl' WIUPll ODD Pi\GE

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(Ocld Ccut.erline)

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Corrective

maint~nance

is

'hei11 ·u.ifed

to System troublcshoot}._ng, __

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the 1 2

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goa,·

:t".:;£

·-\~ht~h :i-~~\~

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i;~-i~~·~-:-;~-~-t --~-~-~~:· -.~i~-~~c-~:f·~;\1e~~;;~ ~~;~·:. ~h~ -··I~~-~r-f

dee '

3

4

6

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Card or the Power Supply. Defects related to data and address can be isolated

~

₉

I :

to'. the data and address paths between Computer and Memory-Card memory matrix

I

using a DEC PDP-11 diagnosti~_ .. (suc~ as _DZQf'..m) ._ However, to correlate Computer 10.

1 ~

I 1 1

ocilal readouts with Memory Card address decoding, do the following: 12J_

I

1

. a. Construct two tables in the forms illustrated in Figtire 4-1. 13

I

I.

b. For a given Computer octal readout, fill in the appropriate

1

1 ~

I

I·

spaces in Table A.

..; I l ;

16 i ! ' c. Insert binary equivalent of act.al. readout in Table A. 17

l

I

!

I d. Transfer binary equivalent to Table B according to

Memory-18 I

I

j . ..

· Card interval bit positions. .. ·' ·

1 ~~

j

·I · · · ·

2 C ;

! .

e. Refer to Memory Card Technical Manual TM929162, Section I I I

21. ; : .. )--·----.for theory of address decoding. _ .

---·---·---·--~·-···-·--··---·-···

22 :

I

·

f. Note that the decoding of Interval Address bits 15 and 16

23 I

I

i

represent RP Select: each RP selected.selects a Memory

;~

; : 1

·

Card. (See Theory, Section II I.) (Figure 4-2 illustrates

~ relationship among external Address

(A),

Address Input (AI) 2

2-: l. f

I

and Memory Address (MA) . )

I

! •

28

1

4-10. Computer designated data bits (BD) also do not correspond·exactly'to

29

I I

:

30

!

!Me~ory System interval data bits. To correlate Computer to Memory data bits 31

I :

refer_J:o Table 4-1._,_:_::_ l)CJge

~ ~

L ._

i

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"Tr, •. - ·= - -· ·• •· .,

~

.. · ,_ ··-- .i.- ; --n

- :;,

14-11_; - MEMORY CARD SELECT _ ... _,,

..., 1 I

.;) ... ! ("'! ~- i

!

3S ·

i

4-~2~"licr-N~ ~~-m-~r~ ~fd }:;~~elected

(addressed) by UNIBUS Address Bits A17 and

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f Al6 ... Table 4-2 designate's UNIBUS Address Bit configurations for selecting

~ ~

l

ea~h

1

~~;;~;~t"a;d S'i~t: •-'- "'~'

this chart, subtract the starting address of

th~·Memory System from the UNIBUS address. The resulting binary states of, 40

41

4~

43

44 45

4G.

47 48

~1~1 I

r·

["'"\

. )

-i

Address Bits Al7 and Al6 correlate to the selected card slot. _. _.

...

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\

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~~rr·-

... ,

53

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9 JO

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-_,

..;.... -~

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15

16

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18

19 2C>

21

22

23

24

25

26

27

28 29

30

31

32

33

3'1

3S

(16)

'""t"'I . .

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.. - - - . - - - 1-1/2

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r~-13.

'. INTERFACE CAHD TROUBLESIJOOTING ' '.

'~~t: ()J~

'.i.'<i1Jle 'Pi tlc

I~

1

2~ r- - :-:.:::· ... ;n .;::: ~: • :..:. -.. -:.··· ... - ... :. : : ·=-- ·:;..:.: "': ~;· .. -:· .. ~; · ... - --: . ; ... , .. _ -; ~-~· ... -: ~ .. ;.-';'::~-;;: .·:··.::::..-.:.":.-.:.::.;. -;.-=--=~-;.~.;:;.-==·=.::-::=--:-:.-:-=--:::::-=--=:::.-.;::r ···..,

I

:; 4-i4. '. Mal functions common to all

Mcmo~y

Cards' nre most likely traceable to the . ; 2

L I '. ·... ·.;-;- .. :· .... ~ '.~.:. :·:. . :·"7.:-"'.'.- •• ~ .".=.::: ::·:'.· ~-.c~:-.• -.- :· .... •.: . . .• ···:.- ; ·:.. ·.-.-:~·:-:. : ... . "'..:::..'". ::;-:.-.~-::=~···:·.:.~ .. , -.·. ·.: ··: :·.-:. ;;;·::::: ·:~·- ·.:· •. ·~:~· ::.-·...: -· I 3

5

In Te r ~ace Ca rd . All data and addr_e_s ~ ~ ~ ~:5

_

_'.l_r_e ___ r_ou t ed through this Card; thus ; 1

I

6 ;re~atcd buffers can be suspected in event of data and address failures. Simi- 4

-. I I .

~ llarly ,· the Parity circuit (when included) services all Memory Cards. .

0

I

I i i

I

l~

j4-f

5.

~ Card-sele~tion

problems ca·n .. be

isolate-~(

by

interchanging Memory Cards ..

i J_ ;continued malfunction of the apparently defec.ti ve Memory Card indicates this

t;

;ca~d

is defective. If the substituted ca:rd fails, the Interface Card is

L4

~efeciive.

!

i .

. I ; I

LS ; I ! f

LE :4-~6. MEMORY CARD MODIFICATION ₁

t_ 7

i

i ~

i_t: 4-17. · To c:.cconunodate the PDP-11 Computer System, the MICROMEMORY 3000QD Memory

c . ! .

_.; Cards are modified as follows:_ ;;: _- \: _·.c:.1 I lj_ ~:<:>::.r~. t ion

:(; l I \

1

l

i ...

:-·'.-B~f-:.:

..

Tl':.1.~~-9~.~-2_:

- - · -

or

.. .

-·~I; ~I

i( Pag

1

le

2-10.

Pl-?_O,·-~~?:S~ Ail~ ~-·,_.,_J

.. l

p~~qe

4-. L~ ... '.}1·s.:. AI14 · -; -~ ... :-1- ... -"::l.'-i' on

(,..4 "' " t.,...l. .... _. ...._ ....4. .·:- o.I . . . . ..L _._ ... •' ' -.s... "-"' ' - •

~~

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Pl-64, Was AI14

Is RDAG

I

Section

V,

Schematic 929668

l

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f

Sheet 1.

Pl-70;

Pl-64. Same as P2-i0 above Height for t:1

'.! i .. : ~)acr2

Sheet 7. -- Zone AS, Was AI 15 to 70 VerticaJ Ill~~tr~tion

RDAG to 64

or .

-sheet 8 •. Zone CB, :Was AI14 to 64

Width for Full P~ge· '

.. Is AI14 to 10·

LandscLJpe

Illustration

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r

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l~vcn Paq0 No. Center Puqe No. Odd Pt-lqc No.

6

7

8

9

10

LL

12

;· 13 14 15

16

17

18

19

20

21

22

23

24

25

26

27

28 29 30

31

32

33

34

35

(17)

···1 · . . .

• - " • · • I ' \ . '.

Table A. Octal to Binary Conversion

. ;

_{·~ .~~=}

.'..:_'

_{~ ·~}

..

_~---·

.. --- ·- ··-· ··-

_{l' .. -.}

,._,/

_{.' i.}

OCTAL READOUT

-.. ·-- -· . ·-·· -. -·.

BINARY EQUIVALENT

. -.

~-... ... -~ ...

INT ADD BITS

16 15 14 13 12 11 10 .9. 8 7 6 5 4 3 2 1

MEM CARD INT BITS

2 0 1 8 11

14

7 10 9 3 12 13 4

s

Table B. Binary Reorganization

MEM.CARD INT

BITS

BINARY

(From Table

A)

14 13 12 11 10 9 8 7 6 5 4 3 2 l

Figure 4-1. Computer Octal to Memory~Card Binary Conversion Chart

. · .. : c;~ -_

. -. . . ---· ...

·Table 4-1_. Data Bit Correlation

BUS DATA

BITS 15 14 13 12 11

10

9 8 7 6 5 4 3 2 1

"'-th/DO BITS 17 2 16 15 14 13 12 11 10 9 7 6 5 4 3 .. 8 1

PARITY

P2

Pl

-·;,...'

Table 4-2. Mem?ry Card Select Chart

UNIBUS.

*

i'

SELECTED

ADDRESS BITS

CARD SLOT

A17 A16

-0 0 B

0 1

c

1 0 D

l 1 E

AI16 AUS Note:

MEMORY INTERNAL

1.

*

1 = Low; '0 = High

ADDRESS BITS

2.**

1

=

High;

0

=

Low

: :. !. ..! : • ~·)

~ t ' I . .

0

6

0

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929494 Micromemory 7405 Add on Memory System Nov77 pdf

•

..

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~L-~i~-~~~~~~-~---T·M·9·2·s·4-94~

., .. '·

"])fl,~

MICROMEMORY 7405

ADD-ON MEMORY SYSTEM

~ ~~~---~---

·-_· ---· -_-

~;;x;

·

1~~n·~,;;-~DD Pl\Gl~

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F 0 REWORD ·-....

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s~~·;':~~=~;·itlc

--

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This manual contains

_

to install

I

operate, and maintain the MICROMEMORY

Add-on

Memory System

part number 929494

manufactured by

Electronic Memories and Magnetics Corporation,

Hawthorne, California.

l

This 7405 Memory System is self-contained

with memory

I

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s·;':=~;·itlc

r===r===--=--"ffE~( pEi;~Ri~:-rlO-N

_{I standard. chassis containing one to four}

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