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Design abstraction for autonomous adaptive hardware systems on FPGAs

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Figure

Fig. 1. Abstract representation of an adaptive hardware system showing theObserve-Decide-Act loop that is able to use external status information aswell as processed information from the hardware to reconfigure the hardwareamong a set of different modes, in the case of an FPGA by loading the relevantbitstream.
Fig. 2. An outline of the partial reconfiguration design flow, showing modulesbeing partitioned into PRRs, wrapping of modules, followed by floorplanningbased on resource requirements, then bitstream generation.
Fig. 3.The proposed model for adaptive hardware systems, showing thehardware portion containing PRRs, the PR controller, and signals for statusand control, alongside the control plane in software executing the Observe-Decide-Act loop.

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