Design Of Schmitt Trigger Based Sem Latch In Cntfet
Technology
Shefali Bharti
1,
Rajesh Mehra
21ME Student, Electronics and communication, NITTTR, Chandigarh, India 2Associate Professor, Electronics and communication, NITTTR, Chandigarh, India
ABSTRACT
In this paper, we evaluate the performance of Schmitt trigger latch using carbon nanotube field effect transistor for low power and energy efficient application. In high density nanoscale circuit soft error affects the operation of system. To deal with the issues caused by soft errors and make a tolerant circuit is really challenging. In proposed soft error masking latch, Schmitt trigger circuit along with pass transistor is designed where the hysteresis property is utilizes to mask the transient fault. The performance factors like area overhead, delay and energy consumption also being compared with existing results. Moreover experimental result shows that proposed method provides improve results than existing methods. Simulation is conducted on 16nm technology node of carbon nanotube field effect transistor. The proposed soft error masking latch has ahieved average power 149.35nW and delay of 7.89ps at VDD equal to 1V.
Key words: Carbon nanotube field effectbtransistore, Schmitt trigger, soft errors INTRODUCTION
It has been shown recently that in portable devices like mobile, laptops, tablets low power consumption to maximize the battery power is a challenge. At nanoscale the size of devices are very small which leads to less power consumption but it leads to generate soft error due to voltage variation. These voltage variation caused by the alpha particle and neutron of cosmic rays. These alpha particle and neutron produce transient pulse which affects the working of nanoscale VLSI devices in broad way.
These high density nanoscale devices also require heat sinks and fans to maintain the temperature requirement but this increase the area overhead and also affect the power consumption. The increased area overhead increasesthe cost of device.
Previously many optimization methods have evolved such as time redundancy method, triple modular redundancy delay assignment variation method. However these methods overcome many penalties in terms of area, power and delay. One more method has proposed where pass transistors are used as a low pass filter and is able to reduce the transient fault. But due to high amount of alpha particle and neutron of cosmic rays the transient pulse exceeds form the driving voltage. In that case the proposed method is not able to mask the soft error properly.
The Schmitt trigger has the property of hysteresis which helps in masking the error. Most of the methods used in reducing the transient pulse based on hardware redundancy where the error can be detected and corrected by comparing the results of different redundant circuits. So these designs have larger area coverage and which in turn increase the power consumption. In another method where capacitance is increased at the nodes to reduce the soft error. But this also results into high power consumptions and high delay.
Short channel effect occurs while scaling of components is performed. Voltage scaling is some but difficult than the component scaling but and it induce high power consumption and increased error. In nanoscale devices the scaling of device dimension is done at high level. And this leads to further heat production and require further heat sinks to cool down.
In this paper, a low cost Schmitt trigger soft error masking latch is introduced where we use pass transistor to reduce thetransient pulse magnitude and improve the performance of device. This method utilizes the feature Schmitt trigger where the hysteresis width makes an addition to reduce the magnitude of transient pulse. Here the feature size and power consumption is also reduced. At present the existing methods uses the hardware redundancy or transistor upsizing which is used to minimizing the single event upset at single node. The proposed method implement the pass transistor along with schimtt trigger overcome the single event upset in multiple nodes and improve the reliability of device.
The rest of the paper organized as follows. Section 2 is basic principle of CNTFET. Section 3 presents the existing work and there limitation. The proposed work is discussed in section 4, results is discussed in section 5. In last section the conclusion and future scope is discussed.
CNTFET
With the increase in scaling of silicon devices, a device is required which provide improvement in with high density integration circuit. Carbon nanotube is a kind of carbon structure which is made up of rolled graphite sheets and is best alternative which provide continuous improvement in the performance of electronic devices.CNTFET act as both semiconductor and metallic property on the basis of the process of rolling up the graphite sheet. The band gap of carbon nanotube inversely proportional to the diameter of tube. To achieve a bandgap of 0.6eV which is a perfect bandgap for semiconductor, carbon tube is made with 1.4nm diameter [].The pair of integer that define the conductivity of CNTFET is known as chirality vector (m,n). The CNTFET gain popularity because of its unique property such as ballistic transport of electrons where resistivity for electrons reduced to its minimum due to scattering. Also CNTFET work easily with high k materials.Carbon nanotubes are of two types such as single walled and multi walled.Single walled is made with single sheet of graphite and multi walled is made up of more than one sheet of graphite can used for different types of application.
Fig.1. (a) Carbon nanotube, (b) Carbon nanotube field effect transistor
Carbon nanotube when used to make field effect transistor is also categorized as N type CNTFET and P type CNTFET. The working of the two is similar to the MOSFET, where the electron produced by source is collected by drain. Gate controls the intensity of electron by applying bias voltage. Further the diameter of CNTFET in terms of (n,m) is obtained as: DCNT = 𝑎 𝜋 (n 2+m2+nm)1/2 (1) a= |𝑎⃗⃗⃗⃗ | = |𝑎1 ⃗⃗⃗⃗ | = 1.42 × √3 = 2.46 𝐴2 𝑜 Where 𝑎⃗⃗⃗⃗ and 𝑎1 ⃗⃗⃗⃗ are lattice vector graphene. 2
The structure of CNTFET is described as: to make a channel region an undoped semiconductor is placed under gate and doped region source and drain this allow ballistic transport of electrons through channel. The device is on and off using threshold voltage which can be calculated as:
𝑉𝑡ℎ= 𝑎𝑉𝜋 √3𝑒 𝑑𝐶𝑁𝑇
Where V𝜋 = 3.033eV is carbon π- π bond energy, e is unit electron charge and dCNTis diameter of carbon nanotube. The Threshold voltage of is inversely proportional to the diameter of CNTFET. By using the various property of CNTFET a low power and low error device can be made.
EXISTNGWORK
In literature, many methods have introduced where soft error is reduced by hardware redundancy such kind of methods suffers from large area overhead and more power consumption.There are some methods in which transistor and increase in capacitance has been utilize but in such method power penalties and delay increase. Moreover there are some methods based on node checking in C- element such as HiPeR latch and FERST latch.
In HiPeR latch, conventional node is introduced in C- elements. Duplicate nodes are used to compare output and filter the soft error. Also feedback is activated for error tolerance in hold mode. Thus error affecting the output has been
controlled by this method but the area and power consumption increased. This method is useful only in storage element with critical path.
FERST latchstands for feedback redundancy SEU tolerant latch. It is based on hardware redundancy concept. The circuit contains two inverters, three c- elements and four transmission gates. The c – element acts as filter to the soft errors. The ability to mask the error in FERST has improved but the other parameters such as area and power consumption has increased.
Moreover Schmitt trigger is used to improve the error tolerance. Pull up and pull down transistor used to reduce power consumption. Hardening of latch is done to mask the soft error. Hardening can be achieved by increase the capacitance at the node of the circuit and by upsizing the transistors. But due to this the power consumption and delay has increased. So the due to this limitation instead of increasing capacitance the critical charge at node is increased. The hysteresis of the CNTFET can be obtained by the diameter of carbon nanotube. The cascade configuration is replaced by transmission gate to make the circuit more tolerant to transient pulse. By the use of transmission gate the number of critical nodes in circuit has decreased. This result into less delay and less power consumption.But this method gives good result with in case of single event upset transient fault at single node. So it is desired to achieve soft error masking in case of multiple node transient error and to design a soft error masking circuit to reduce the error on the output.
Fig. 2. Existing Schmitt trigger based hardened latch PROPOSEDWORK AND SIMULATIONRESULT
In proposed work, a very efficient method for designing a soft error masking latch is proposed. Proposed design is consists of a pass transistor, Schmitt trigger using CNTFET. When input is applied, first pass transistor reduce the magnitude of transient pulse.The magnitude of transient pulse is redudced by 12%. Further the signal is applied to the Schmitt trigger. This Schmitt trigger reshape is noisy signal by using the threshold voltges. The lower threshold voltage is 0v and upper threshold voltage is 0.5V. This design is able to mask the soft error even if the magnitude of transient pulse is more than the magnitude of driving voltage. Objective of this paper is to design a latch i.e. a memory element using carban nanotube field effect transistors that efficiently mask the soft error by filtering the transient pulse. The hysteresis property of Schmitt trigger is utilized further to improve the result. This method is designed using 16nm technology of CNTFET. The result is compared at different frequencies one is 500MHz and other is 1GHz. Performance is evaluated on the basis of capability of masking the soft error, power consumption and delay. Simulation of this design is done on Cadance Virtuoso.
Fig: 3. Layout of CNTFET based SEM latch
Fig: 4 Proposed SEM latch
The simulation waveforms shows of proposed SEM latch shows that the soft error affects only the internal and output nodes and affected nodes cannot be recovered without next clock pulse. The output of the propsed circuit and glitch free. It is very clear from the result that the propsed SEM latch effectively filter the soft error and the mask the affected nodes of circuit.
Fig: 5 Transient reponse of propsed design
A fair comparision is made in table between the existing work and propsed work. Table 1 shows the implementation of result and its comparision in terms of ability of masking error, average power, static power, area overhead and delay. In terms area overhead the area increased is very small. As compared to existing design the number of transistors increased is two only. As for dealy the proposed SEM latch is faster than existing design. It has shorter setup time . At last the measurement of power consumption, the proposed SEM latch consume lowest power. The less switching time and the power dissipation lowers the static power consumption.
Table: 1 Performance comparision
FREQUENCE 500MHz 1 GHz
Schmitt trigger latch of [1]
Average power (uW) 294.13 565.96
Static power (pW) 10.90 10.90
Delay(ps) 13.78 13.78
PDP (aJ) 4.05 8
Proposed design Average power (uW) 149.35 246.45
Static power (pW) 05.26 06.23
Delay(ps) 07.89 8.15
PDP (aJ) 4.00 6.74
CONCLUSION
The intrinsic gain of CNTFET is vary high than CMOS, this property make it suitable for robust design. In case of single event upset, CNTFET provide better results than MOSFET. In this paper soft error masking circuit using Schmitt trigger, pass transistor based on CNTFET has proposed for masking error. The view point of designing this latch is based on evaluation from error masking capability, area overhead and delay.Propsed latch consists of 8 transistors which results into average power 149.35nW and delay of 7.89ps is achieved at driving voltage 1V. The diameter is set to achieve a suitable hysteresis width. High reliability is achieved in terms of masking the soft error.Additionalythe circuit can be optimized by adjusting the nanometric technology which will be capable ofachieving high gain. Proposed circuit have very simple structure with less number of transistors and able to achieve high reliability, less power consumption and less delay during the operation.
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Authors:
Shefali Bharti: Shefali Bharti is a M.E. scholar from National Institute of Technical Teachers Training and Research, Chandigarh India. She is having five years of industry experience. She has completed her B.Tech from Mahant Ram Institute of technology - College of Engineering and management from Himachal Pradesh in 2014. Her interest areas are Digital Signal Processing, VLSI Design, Digital Electronics, nanotechnology and Digital Communication.
Dr. Rajesh Mehra: Dr. Mehra is currently associated with Electronics and Communication Engineering Department of National Institute of Technical Teachers’ Training & Research, Chandigarh, India since 1996. He has received his Doctor of Philosophy in Engineering and Technology from Panjab University, Chandigarh, India in 2015. Dr. Mehra received his Master of Engineering from Panjab University, Chandigarh, India in 2008 and Bachelor of Technology from NIT, Jalandhar, India in 1994. Dr. Mehra has 20 years of academic and industry experience. He has more than 325 papers to his credit which are published in refereed International Journals and Conferences. Dr. Mehra has guided 75 ME thesis. He is also guiding 02 independent PhD scholars. He has also authored one book on PLC & SCADA. He has developed 06 video films in the area of VLSI Design. His research areas are Advanced Digital Signal Processing, VLSI Design, FPGA System Design, Embedded System Design, and Wireless & Mobile Communication. Dr. Mehra is member of IEEE and ISTE.