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Digital Systems & Applications
Chapter - 5, 6, 7, 8
5.Data Processing Circuits 6.Arithmetic Circuits
7. Sequential Circuits 8. Timers...
Chapter
– 5
Data Processing Circuits
Que 1: What is a multiplexer? Draw a circuit representation and truth table of 8 -to- 1
multiplexer
.
Ans. A multiplexer or MUX, also called a data selector, is a combinational circuit with more
than one input line, one output line and more than one selection line. A multiplexer selects binary information present on any one of the input lines, depending upon the logic status of the selection inputs, and routes it to the output line. If there are n selection lines, then the number
of maximum possible input lines is 2n and the multiplexer is referred to as a 2�-to-1 multiplexer
or 2� ×1 multiplexer.
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Que 2: Design a 4 -to- 1 multiplexer using logic gates and write down the truth table. Ans:
Que3: Design a 16-to-1 multiplexer using two 8-to-1 multiplexers having an active LOW ENABLE input.
Ans: A 16-to-1 multiplexer can be constructed from two 8-to-1 multiplexers having an ENABLE
input. The ENABLE input is taken as the fourth selection variable occupying the MSB position. The i uit fu tio s as follo s. Whe “ is i logi state, the upper multiplexer is enabled and the lower multiplexer is disabled. If we recall the truth table of a four-variable Boolean
function, S3 ould e fo the fi st eight e t ies a d fo the e ai i g eight e t ies.
Therefore, when S3 = 0 the final output will be any of the inputs from D0 to D7, depending upon the logic status of S2, S1 and S0. Similarly, when S3 = 1 the final output will be any of the inputs from D8 to D15, again depending upon the logic status of S2, S1 and S0. The circuit therefore implements the truth table of a 16-to-1 multiplexer.
Que4: What is a demultiplxer and design a 16-to-1 demultiplexer and write down its truth table.
Ans: A demultiplexer is a combinational logic circuit with an input line, 2n output lines and n select lines. It routes the information present on the input line to any of the output lines. The output line that gets the information present on the input line is decided by the bit status of the selection lines.
Que5: Design an octal to binary encoder and write down the truth table.
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Ans: Consider an octal-to-binary encoder. Such an encoder would have eight input lines, each
representing an octal digit, and three output lines representing the three-bit binary equivalent.
The truth table of such an encoder is given in Table In the truth table, D0 to D7 represent octal
digits 0 to 7. A, B and C represent the binary digits. The eight input lines would have 28 = 256
possible combinations. However, in the case of an octal-to-binary encoder, only eight of these 256 combinations would have any meaning. The remaining combinations of input variables are
do t a e i put o i atio s. Also, o l o e of the i put lines at a ti e is i logi state.
Truth Table of octal to binary encoder
Que6: Construct a 3-8 decoder using logic gates and write down its truth table.
Ans: A decoder is a combinational circuit that decodes the information on n input lines to a
maximum of 2n unique output lines. Figure below shows the circuit representation and logic
gate implementation of 3-to-8 decoder.
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Chapter
– 6
Arithmetic Circuits
Que:1 write down the truth table of half adder and draw a circuit diagram using logic gates.
Ans:
Que:2 Design a half adder using NAND gates.
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Ans:
Que3: Explain the working of full adder and write down the truth table.
Ans: A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a SUM and a CARRY output. The full adder circuit overcomes the limitation of the half-adder, which can be used to add two bits only. We begin with the addition of LSBs of the two numbers. We record the sum under the LSB column and take the carry, if any, forward to the next higher column bits. As a result, when we add the next adjacent higher column bits, we would be required to add three bits if there were a carry from the previous addition. We have a similar situation for the other higher column bits also until we reach the MSB. A full adder is therefore essential for the hardware implementation of an adder circuit capable of adding larger binary numbers. A half-adder can be used for addition of LSBs only.
Figure 1 shows the truth table of a full adder circuit showing all possible input combinations and corresponding outputs.
Figure (1)
Que4: Design a full adder using two half adders.
Ans:
Que5: Implement a half subtractor using logic gates and write down its truth table.
Ans:
Que6: Design a four-bit adder subtractor using four full adders and explain its working.
Ans: “u t a tio of t o i a u e s a e a o plished addi g s o ple e t of the
subtrahend to the minuend and disregarding the final carry, if any. If the MSB bit in the result of additio is a , the the esult of additio is the o e t a s e . If the M“B it is a , this
implies that the answer has a negative sign. The true mag itude i this ase is gi e s
complement of the result of addition. The control input here is referred to as the SUB input.
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Conditions
Addition
When the SUB input is in logi state, the fou its of the i a u e B B B B _ a e
passed on as such to the B inputs of the corresponding full adders. The outputs of the full adders in this case give the result of addition of the two numbers.
Subtraction
Whe the “UB i put is i logi state, fou its of o e of the u e s, B B B1 B0_ in the p ese t ase, get o ple e ted. If the sa e is also fed to the CA‘‘Y-IN of the LSB full
adder, hat e fi all a hie e is the additio of s o ple e t a d ot s o ple e t. Thus,
in the adder arrangement of Fig. e a e asi all addi g s o ple e t of B B B B _ to
(A3 A2 A1 A0_. The outputs of the full adders in this case give the result of subtraction of the
two numbers. The arrangement shown achieves A−B. The final carry (the CARRY-OUT of the
MSB full adder) is ignored if it is not displayed.
Que7: Design a 8-bit controlled inverter.
Ans: Figure below shows a controlled inverter. When INVERT is low, it transmits the 8-bit input
to the output; when INVERT is high, it transmits the l's complement. For instance, if the input number is
Chapter
– 7
Sequential Circuits
Que1: What is the difference between a combinational circuit and a sequential circuit. Give
one example of each.
Ans: Combinational logic (sometimes also referred to as time-independent logic) is a type of
digital logic which is implemented by Boolean circuits, where the output is a pure function of
the present input only.Example: Adder [1+0=1; Dependency only on present inputs i.e., 1 and
0].
Sequential logic is a type of logic circuit whose output depends not only on the present value of
its input signals but on the sequence of past inputs.Example: Counter [Previous O/P +1=Current
O/P; Dependency on present input as well as previous state].
Que2: Design a R-S Flip-Flop with Active LOW Inputs using NAND gates.
Ans: Figure below shows a NAND gate implementation of an R-S flip-flop with active LOW
inputs. The two NAND gates are cross-coupled. That is, the output of NAND 1 is fed back to one of the inputs of NAND 2, and the output of NAND 2 is fed back to one of the inputs of NAND 1. The remaining inputs of NAND 1 and NAND 2 are the S and R inputs. The outputs of NAND 1 and NAND 2 are respectively Q and Q outputs.
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Que3: What are the key differences between edge-triggered and level-triggered clocked- flip flops?
Ans: Level Triggering: In level triggering the circuit will become active when the gating or clock
pulse is on a particular level. This level is decided by the designer. We can have a negative level triggering in which the circuit is active when the clock signal is low or a positive level triggering in which the circuit is active when the clock signal is high.
Edge Triggering: In edge triggering the circuit becomes active at negative or positive edge of
the clock signal. For example, if the circuit is positive edge triggered, it will take input at exactly the time in which the clock signal goes from low to high. Similarly, input is taken at exactly the time in which the clock signal goes from high to low in negative edge triggering. But keep in mind after the input, it can be processed in all the time till the next input is taken.
Que4: Design a clocked RS flip flop with active high inputs and write down the Truth table.
Ans: In the case of a clocked R-S flip-flop, or for that matter any clocked flip-flop, the outputs
change states as per the inputs only on the occurrence of a clock pulse. The clocked flip-flop could be a level-triggered one or an edge-triggered one.
The basic flip-flop is the same as that shown in previous question. The two NAND gates at the input have been used to couple the R and S inputs to the flip-flop inputs under the control of the clock signal. When the clock signal is HIGH, the two NAND gates are enabled and the S and R inputs are passed on to flip-flop inputs with their status complemented. The outputs can now change states as per the status of R and S at the flip-flop inputs.
Que5: Distinguish between Synchronous and Asynchronous Flip-Flop Inputs.
Ans: The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous
inputs because they have effect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal transitions. Asynchronous inputs can set or reset the flip-flop regardless of the status of the lo k sig al. T pi all , the e alled p eset a d lea :
When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? We get an invalid state on the output, where Q and not-Q go to the same state, the same as our old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once.
Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or
active-lo . If the e a ti e-low, there will be an inverting bubble at that input lead on the block
symbol, just like the negative edge-trigger clock inputs.
Que6: How does JK flip flop overcome the invalid condition in R-S flip flop.
Ans: JK flip-flop is basically an SR flip flop with feedback which enables only one of its two input terminals, either SET or RESET to be active at any one time thereby eliminating the invalid condition seen previously in the SR flip flop circuit.
Case 1. When the clock is applied and J = 0, whatever the value of Q'n (0 or 1), the output of NAND gate 1 is 1. Similarly, when K = 0, whatever the value of Qn (0 or 1), the output of gate 2 is also 1. Therefore, when J = 0 and K = 0, the inputs to the basic flip-flop are S = 1 and R = 1. This condition forces the flip-flop to remain in the same state.
Case 2. When the clock is applied and J = 0 and K = 1 & the previous state of the flip-flop is reset (i.e., Qn = 0 and Q'n = 1), then S = 1 and R = 1. Since S = 1 and R = 1, the basic flip-flop does not alter the state and remains in the reset state. But if the flip-flop is in set condition (i.e., Qn = 1 & Q'n = 0), then S = 1 and R = 0. Since S = 1 and R = 0, the basic flip-flop changes its state and resets.
Case 3. When the clock is applied and J = 1 and K = 0 and the previous state of the flip-flop is reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R = 1. Since S = 0 and R = 1, the basic flip-flop changes its state and goes to the set state. But if the flip-flop is already in set condition (i.e., Qn = 1 and Q'n = 0), then S = 1 and R = 1. Since S = 1 and R = 1, the basic flip-flop does not alter its state and remains in the set state.
Case 4. When the clock is applied and J = 1 and K = 1 and the previous state of the flip-flop is reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R = 1. Since S = 0 and R = 1, the basic flip-flop changes its state and goes to the set state. But if the flip-flop is already in set condition (i.e., Qn = 1 and Q'n = 0), then S = 1 and R = 0. Since S = 1 and R = 0, the basic flip-flop changes its state and goes to the reset state. So, we find that for J = 1 and K = 1, the flip-flop toggles its state from set to reset and vice versa. Toggle means to switch to the opposite state.
Que7: Design a D flip flop using JK flip flop.
Ans: Figure below shows the circuit symbol and function table of a negative edge-triggered D
flip-flop. When the clock is active, the data bit (0 or 1) present at the D input is transferred to the output. In the D flip-flop of figure shown, the data transfer from D input to Q output occurs on the negative-going (HIGH-to-LOW) transition of the clock input. The D input can acquire new status when the clock is inactive, which is the time- period between successive HIGH-to-LOW transitions. The D flip-flop can provide a maximum delay of one clock period.
Que8: What are the Race-around conditions in J-K Flip-Flop.
Ans: JK flipflop has three inputs and two outputs. Outputs are complementary to each other.
when j = k = 0 and clk = 1; output of AND gates will be 0; when any one input of NOR gate is 0 output of NOR gate will be complement of other input, so output remains as previous output. when j =0 k =1 and clk = 1; output of AND gate connected to K will be Q and corresponding NOR gate output will be 0; which RESETs the flipflop.
when j =1 k = 0 and clk = 1; output of AND gate connected to j will be Q' and corresponding NOR gate output will be 0; which the SETs the flipflop.
when j =1 k = 1 and clk = 1; Q output will toggle as long as CLK is high. Thus the output will be unstable creating a race-around problem with this basic JK circuit. This problem is avoided by
ensuring that the lo k i put is at logi o l fo a e sho t ti e, o to p odu e a more
sophisticated JK flip-flop circuit called a Master–slave flip-flop.
Que9: Explain the working of a Master-Slave Flip-Flop.
Ans: The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse. The outputs from Q and Q
f o the “la e flip-flop a e fed a k to the i puts of the Maste ith the outputs of the Maste flip flop ei g o e ted to the t o i puts of the “la e flip flop. This feed a k o figu atio f o the sla e s output to the aste s i put gi es the ha a te isti toggle of the JK flip flop.
The input signals J and K are o e ted to the gated aste “‘ flip flop hi h lo ks the
i put o ditio hile the lo k Clk i put is HIGH at logi le el . As the lo k i put of the
sla e flip flop is the i e se o ple e t of the aste lo k i put, the sla e “‘ flip flop does ot toggle. The outputs f o the aste flip flop a e o l see the gated sla e
flip flop he the lo k i put goes LOW to logi le el .
Whe the lo k is LOW , the outputs f o the aste flip flop a e lat hed a d a additional ha ges to its i puts a e ig o ed. The gated sla e flip flop o espo ds to the state of its i puts passed o e the aste se tio .
The o the Lo -to-High t a sitio of the lo k pulse the i puts of the aste flip flop a e
fed through to the gated i puts of the sla e flip flop a d o the High-to-Lo t a sitio the
sa e i puts a e efle ted o the output of the sla e aki g this t pe of flip flop edge o pulse-triggered.
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Chapter
– 8
Timers
Que1: Draw the block diagram of 555 timer.
Ans:
Que2: Explain in detail the working of Astable multivibrator.
Ans: The Astable Multivibrator is another type of cross-coupled transistor switching circuit that
has NO stable output states as it changes from one state to the other all the time. The astable
circuit consists of two switching transistors, a cross-coupled feedback network, and two time delay capacitors which allows oscillation between the two states with no external triggering to produce the change in state.
In electronic circuits, astable multivibrators are also known as Free-running Multivibrator as they do not require any additional inputs or external assistance to oscillate. The basic transistor circuit for an Astable Multivibrator produces a square wave output from a pair of grounded emitter cross-coupled transistors. Both transistors either NPN or PNP, in the multivibrator are biased for linear operation and are operated as Common Emitter Amplifiers with 100% positive feedback.
Basic Astable Multivibrator Circuit
• Assu e that t a sisto , T‘ has just s it hed OFF ut-off) and its collector voltage is
isi g to a ds V , ea hile t a sisto T‘ has just tu ed ON . Plate A of
capacitor C1 is also rising towards the +6 volts supply rail of Vcc as it is connected to the collector of TR1 which is now cut-off. Since TR1 is in cut-off, it conducts no current so there is no volt drop across load resistor R1.
• The othe side of apa ito , C , plate B , is o e ted to the ase te i al of t a sistor
TR2 and at 0.6v because transistor TR2 is conducting (saturation). Therefore, capacitor
C1 has a potential difference of +5.4 volts across its plates, (6.0 – 0.6v) from point A to
point B.
• Since TR2 is fully-on, capacitor C2 starts to charge up through resistor R2 towards Vcc.
When the voltage across capacitor C2 rises to more than 0.6v, it biases transistor TR1 into conduction and into saturation.
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• The i sta t that t a sisto , T‘ s it hes ON , plate A of the apa ito hi h as originally at Vcc potential, immediately falls to 0.6 volts. This rapid fall of voltage on plate A auses a e ual a d i sta ta eous fall i oltage o plate B the efo e plate
B of C is pulled do to -5.4v (a reverse charge) and this negative voltage swing is
applied the ase of T‘ tu i g it ha d OFF . O e u sta le state.
• Transistor TR2 is driven into cut-off so capacitor C1 now begins to charge in the opposite
direction via resistor R3 which is also connected to the +6 volts supply rail, Vcc. Thus the base of transistor TR2 is now moving upwards in a positive direction towards Vcc with a time constant equal to the C1 x R3 combination.
• However, it never reaches the value of Vcc because as soon as it gets to 0.6 volts
positi e, t a sisto T‘ tu s full ON i to satu ation. This action starts the whole process over again but now with capacitor C2 taking the base of transistor TR1 to -5.4v while charging up via resistor R2 and entering the second unstable state.
• Then we can see that the circuit alternates between one unstable state in which
t a sisto T‘ is OFF a d t a sisto T‘ is ON , a d a se o d u sta le i hi h T‘ is ON a d T‘ is OFF at a ate dete i ed the ‘C alues. This p o ess ill epeat itself over and over again as long as the supply voltage is present.
Que3: Explain in detail the working of monostable multivibrator.
Ans: Mo osta le Multi i ato s ha e o l ONE sta le state he e thei a e: Mo o , a d
produce a single output pulse when it is triggered externally. Monostable Multivibrators only return back to their first original and stable state after a period of time determined by the time constant of the RC coupled circuit.
Monostable Multivibrator Circuit
• The basic collector-coupled transistor Monostable Multivibrator circuit and its associated waveforms are shown above. When power is firstly applied, the base of transistor TR2 is connected to Vcc via the biasing resistor, RT thereby turning the t a sisto full -ON a d i to satu atio a d at the sa e ti e tu i g T‘ OFF i the
process. This the ep ese ts the i uits “ta le “tate ith ze o output. The u e t
flowing into the saturated base terminal of TR2 will therefore be equal to Ib = (Vcc –
0.7)/RT.
• If a negative trigger pulse is now applied at the input, the fast decaying edge of the
pulse will pass straight through capacitor, C1 to the base of transistor, TR1 via the lo ki g diode tu i g it ON . The olle to of T‘ hi h as p e iousl at V d ops quickly to below zero volts effectively giving capacitor CT a reverse charge of -0.7v across its plates. This action results in transistor TR2 now having a minus base voltage at poi t X holdi g the t a sisto full OFF . This the ep ese ts the i uits se o d state, the U sta le “tate ith a output oltage e ual to V .
• Timing capacitor, CT begins to discharge this -0.7v through the timing resistor RT,
attempting to charge up to the supply voltage Vcc. This negative voltage at the base of transistor TR2 begins to decrease gradually at a rate determined by the time constant of the RT CT combination. As the base voltage of TR2 increases back up to Vcc, the
t a sisto egi s to o du t a d doi g so tu s OFF agai t a sisto T‘ hi h esults in the monostable multivibrator automatically returning back to its original stable state awaiting a second negative trigger pulse to restart the process once again.
