AN EXPANSIVE AND COMPARABLE STUDY OF EFFECTUAL ALGORITHMS FOR PLACEMENT IN PHYSICAL DESIGN

AN EXPANSIVE AND COMPARABLE

STUDY OF EFFECTUAL ALGORITHMS

FOR PLACEMENT IN PHYSICAL

DESIGN

PRAGYA SHARMA*

Department of EECE, ITM University, Gurgaon (Haryana), India

UPASANA YADAV

Department of EECE, ITM University, Gurgaon (Haryana), India

NEERAJ KR.SHUKLA

Department of EECE, ITM University, Gurgaon (Haryana), India

Abstract :

This review paper consists of comprehensive study of VLSI algorithms for placement in physical design. The work has been classified under different perspectives like performance,area,wirelength,cost and power and the algorithms address the coverage and optimization of these factors. Placement is a major step for VLSI physical design as it involves placing the blocks on the chip with minimum possible area consumption however the initial placement is done by constructive placement algorithms such as constructive and iterative placement. Under the survey work which is done, the knowledge of placement algorithms with their merits and limitations has been provided so that according to the requirement one can choose the best algorithm. The survey involves simulation of different algorithms implemented in C and C++ programming languages. Tools from the EDA vendors have been provided for the simulation work so as to achieve the results and to have best possible outcomes. We survey the history of placement research, the progress achieved up to now, and outstanding challenges. Some future work has also been mentioned in which the research work can be carried upon.

Keywords: Algorithm, Physical Designing, Placement, VLSI.

1. Introduction

Integrated Circuit (IC) technology is emerging in electronics field very rapidly. According to Moore's law, the number of transistors on an IC doubles after every 2 years. Gradually this field of electronics is flourishing by packing more and more logic devices into the smaller areas on a circuit board. Placement algorithms are divided on the basis of input to the algorithm, nature of output generated and process used by the algorithm. The algorithms can be deterministic or probabilistic. According to the ITRS Roadmap, the maximum number of transistors per chip will be over 1.6 billion, with a clock frequency of 28.7 GHz by the year 2016. Such high complexity poses significant challenges to the scalability of placement algorithms. The VLSI design cycle involve some specific steps which is shown in Fig 1 according to which the different abstraction levels of a designing a chip are performed.

VLSI chip and after undergoing through above steps, it produces a packaged chip. A typical digital design follows steps such as specification of architecture, behavioural or functional design, logic design, circuit design, physical design, fabrication, packaging, testing and debugging. The main algorithms for placement are discussed in Fig 2

The rest of the paper is organised as follows, Section II gives some of the placement algorithms which are used in physical design. Section III describes the literature survey. Finally Sections IV concludes the paper and discusses some possible extension of proposed work.

Fig 2 Evolution Tree

2. Some Placement Algorithms

2.1.Simulated Annealing

If any change in the placement configuration is to be done then that change is done by moving the component or by interchanging the location of two components. The moves that results in the decrease in the cost are accepted. Moves that results in increase in the cost are accepted with the probability that with some iteration done, the cost will gradually decrease.

The acceptance probability is given as e- ▲C/T where C is cost and T is temperature. The algorithm

starts with a very high value of temperature which gradually decreases so that moves that increase cost have lower probability of being accepted.

2.2.Simulated Evolution

It is also called as genetic algorithm which starts with the initial set of placement configuration called as population. The initial placement configuration can be generated randomly. There are three genetic operators which are used for creating offsprings which are:

2.2.1 Crossover

Crossover generates offsprings by combining schemata of two individuals at a time.

2.2.2 Mutation

This is not directly responsible for producing new offsprings but it causes incremental random changes in the offspring produced by crossover.

2.2.3 Selection

After the offspring is generated,individuals for the next generation are chosen which is based on certain criteria.

2.3Breuer Algorithm

In addition to different objective functions, Breuer algorithm also presents various placement procedures in which different sequence of cut lines are used like cut oriented min cut placement, quadrature placement procedure,bisection placement procedure and slice bisection placement procedure.

2.4Terminal Propogation Algorithm

The partitioning algorithm partitioned the circuit to reduce the net cut, so it can’t be used directly for placement. If it is used directly then the terminals A and B will move away from each other as a result of partitioning which increases the net length and congestion. To overcome this,we need to propagate a dummy terminal to nearest point on boundary. When this dummy terminal is generated,the partitioning algorithm will not assign the two terminals in each partition as this will not result in minimum cut. This method is called as terminal propagation method.

Dummy terminal Terminal

Fig 3 Terminal propagation [41]

3. Literature Survey

Table 1 represents the comparison of work so far in terms of various parameters like cost, area, performance and wirelength.Technology, algorithms used, achievements, future trends, limitations and trade offs have been compared.

A

B

B

A

A

A

B

Table 1 Comparison of placement algorithms, achievements, parameters, limitations and trade off PAPER TITLE/ AUT HOR TECHN O L OGY /

TOOL/ LA

NGU AG E USE D ALG O RI TH M S USE D ACHIEVEME N TS PARAME TER S FUT U RE TRENDS LIM ITA TI ONS AN D TR A D E OFF COMM ENTS Solving Standard Cell Placement Problem using an evolutionary approach- 2013 Jobanpreet Kaur and Maninder Kaur [1]

Turbo C Genetic algorithm and EASCP

EASCP is better than GA in terms of quality and time .Trial value is associated with every solution and is modified to produce a better offspring.

Fitness factor =1/wirelength which is better in EASCP

-- -- Great

approach toward EASCP algorithm,com parison table also mentioned giving a better understanding Simulated annealing based placement algorithms and research challenges: A survey-2012 Suchismita Pattanaik, Subhendu Prakash Bhoi and Rakesh Mohanty [2]

-- Simulation based algo , partitioning based algo

-- Configuration , cost , cooling

schedule , starting and final temp , iteration at each step , temp decrement Right selection of initial position and temperatur e should be known by finding max distance between two blocks Slow due to iteration to be done at each temperatur e Many placement algorithms have been discussed giving a better view and good idea

Digital

implementation of 16 bit

synchronous counter with soc encounter for placement and routing-2012 Mr. Pillem Ramesh and Venkata Aravind Bezawada [3] 130 nm technology using Cadence encounter version 9.1

-- TNS and WNS are

improved at each step. At last setup slack = 0.034ns and hold slack = 0.016ns. density of design = 90.079%

Setup slack is 0.034ns and hold slack is 0.016ns. final density of states is 90.079%

-- Negative values of setup and hold time are to be removed 16 bit synchronous counter has been implemented using cadence encounter tool and reduction in different factors has been done SimPL: An effective placement algorithm Myung-Chul Kim, Dong-Jin Lee and Igor L Markov [4]

C++ SimPL Iterative nature ,

Logic on logic 3D integration and placement Thorlindur Thorolfsson, Guojie Luoy, Jason Congy and Paul D. Franzon[5] For 2D placement – cadence encounter For 3D placement – Tezzaron’s 130nm 3DIC process 3D standard cell placement algorithm i.e 3D placement using sequential off the shell 2D placement , True 3D analytical placement , 3D placement using

simultaneous 2D placement

Improve max clock frequency upto 22.6% and power consumption upto 12.9% for AES and PE module. Face to face integration improves results as microbumps don’t block routing. Power and frequency are improved by 12.9% and 22.6% respectively. Other parameters are Footprint , pitch , block and grid

3D integration can be used to have a better results between 2D and 3D routing also

-- 3 D placement techniques have been introduced Chip dependent leakage power aware placement algorithm for FPGA Behzad Salami [6] VARIUS for process variation , ACE for netlist static probability , VPR , power model TPAP (total power aware placement), DPAP (dynamic power aware placement) , PTPAP(pure total power aware placement algorithm)

PDP is improved upto 7.2% , run time improved upto 35% PDP improvement 7.2% ,leakage power improvement by 3.2%, utilisation rate of FPGA = 60%,other parameters are Vth and

technology scaling Early prediction model for routing resource’s leakage power consumpti on and apply it to the DPAP , some other chip dependent algo for routing

-- Leakage power,dynami c power and delay have been considered for minimisation which are important parameters for a chip Comparison of hierarchical mixed size placement algorithm for VLSI physical synthesis B. Sekhara Babu, Rajine Swetha R and Dr. Sumithra Devi K. A [7]

NTU place

3 Mixed size placement : flat and hierarchical

Analytical , quadratic , macro , timing driven , power aware placements have been discussed with advantages of each

Wirelength

optimisation Macro placement and routability , timimg , power , thermal placement optimisatio n Placement quality in timimg driven placement is bad because nets length is made very short than they need to be.

Flat and hierarchical approaches have been discussed and all the different algorithms have been implemented in various placers. Interleaving of

gate sizing and constructive placement for predictable performance - Sungjae Kim, Eugene Shragowitz, George Karypis and Rung-Bin Lin2 [8] C , cadence: buildgate ,SOC encounter , timing driven amoeba, route , synopsis edif2verilo g convertor Gate sizing

algorithm CP and AMOEBA placers are compared to a given set of floorplan and found that CP produces better results

Delay improvement by 19% other factors are wirelength and run time

POLAR : placement based on novel rough legalization and refinement - Tao Lin, Chris Chu, Joseph R. Shinnerl, Ismail Bustany and Ivailo Nedelchev [9]

C++ ,

fastDP Polar algorithm – initial placement, density driven placement, local legalization. Runtime improvement of PCG(48.1%), rough legalization (13.9%), legalization and detailed placement (22.9%) Wirelength =2.5% , speed = 5.16 times faster than MAPLE

Enhancem ent of algorithm to find ill shaped hotspot rather than restricting number of bins, extend POLAR to handle with big movable macros POLAR is faster than NTUPlace 3,mPL6 but slower than SIMpl,Co mPLx Polar algorithm gives a basic idea for rough legalisation which further helps in global placement

Latch planner : latch planner algorithm for datapath oriented high performance VLSI design-2013 Minsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler and Ruchir Puri [10]

C++ Latch planner

algorithm Comparison of latch planner, BL, SC is done.

Improvement in Wirelength= 32%,Total negative slack=25% and area=3%

-- -- Latch Planner

handles complex datapath by optimizing the dimension of each cluster based on the algorithm Relay node placement algorithm in wireless sensor network-2014 Kumar Nitesh and Prasanta K. Jana [11] Matlab Minimum relay node connected cover Minimum number of relay nodes with full coverage and connectivity of WSN with the constraint of minimising overall communication cost

Cost for communicatio n , coverage area , connectivity problem , coverage problem

-- -- For a fully covered and connected problem relay node placement is done in wireless sensor networks Design and

evaluation of a hierarchical application placement algorithm in large scale clouds-2011 Hendrik Moens, Jeroen Famaey, Steven Latre, Bart Dhoedt and Filip De Turck [12]

Linux server with intel core i3 CPU Centralised and hierarchical

Large parts of applications are managed at root level. Lower level nodes can execute placement much faster.

Solution within 5% of optimum placement when using centralised algo could be achieved in 25% less time

Improve robustness of Hierarchic al manageme nt system. Reconstruc t the manageme nt tree and adjust parameter Demand decoupling has a demerit that all the manageme nt levels need to be passed to enable scheduling. Hierarchical approach is faster and, thus, more scalable. A reliability oriented placement algorithm for reconfigurable digital micro fluidic biochips using 3D deferred decision making

C++ Reliability

oriented non SA 3D placement algorithm using 3D-DDM technique Factors favourable for reliability enhancement were placed in algorithm so that problem could be effectively solved within time

High throughput, Reliability and non

overlapping

technique-2013 Ying-han chen, chung-lun hsu, li-chen tsai, tsung-wei huang, and tsung-yi ho [13]

biochips

(DMFB) reliability degradation and introduced a new

and practical formulation of reliability-oriented 3-D placement Problem. Optimal Reservoir

Operation Using a Hybrid

Simulated Annealing Algorithm-Genetic

Algorithm-2010 Yong-yong Zhang,Qiang Huang,Fan Gao and Xiao-yi Sun[14]

-- Hybrid SA-GA algorithm

Effective optimisation method , more feasible and valid , less execution time , more speed

Better convergence, fast speed

-- -- SA is introduced which is feasible and has validity also,global optimum solution is obtained in a little time

A Parallel Clustering Algorithm for Placement-2014 Amir Momeni, Perhaad Mistry, David Kaeli [15]

GCC compiler

Clustering algorithm

Parallel

implementation of this algorithm is 27.2 times better than best choice , 16.2 times better than safe choice , 2.9 times faster than first choice

Performance , quality of placement , execution time

Impact of selection policies on design quality , improveme nt in quality of parallel algorithm as that of serial algorithm

-- Parallel clustering algorithm can be time consuming and can lead to effect on cluster area

A standard-cell placement algorithm of optimizing multiple objects-2000 Wenting hou, Xianlong hong, Weimin wu and Yici cai [16]

-- Timing and

congestion driven placement

Congestion and delay decreases by 30% and 10% respectively

Timing = 30% decrease congestion=10 % decrease

-- -- Timing and congestion have been optimised to a great extent

Progress and challenges in VLSI placement research - Igor L. Markov, Jin Hu and Myung-Chul Kim [17]

-- High performance wirelength driven placement , mix size placement , routability driven placement , timing and power driven placement

Different placement algorithms have been studied and different aspects are represented

Wirelength , timing , cells placement

More integrated timing and power optimisatio ns , layout friendly high level synthesis

-- This paper

Walking Pads: Fast Power-Supply Pad-Placement Optimization-2014 Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron and Mircea Stan [18]

-- WP algorithm A fast method of determining minimum number of pads to satisfy IR drop constraint and the optimisation locations Speedup achieved upto 634X as compared to SA, 0.01% IR drop

Join optimisatio n of Vdd and gnd pad placement , use of WP for TSV (through silicon via) placement in 3D IC

-- In this paper

use of minimum number of pads have been adviced so as to reduce the voltage drop in the chip Comparing VM-Placement Algorithms for On-Demand Clouds-2011 K. Mills, J. Filliben and C. Dabrowski [19]

Koala VM placement

algorithm Developed an objective method to compare resource allocation algorithm in simulation of large distributed system Number of clusters , number of nodes per cluster , probability of user’s and node

configuration type , hold time Include more and different VM placement algorithms to reduce cost and enhance the performan ce

-- PM(physical machines) have been partitioned in 2 sets in which one set is having some criteria foundation and other does not VMAP: a Variation Map-aware Placement Algorithm for Leakage Power Reduction in FPGA-2011 Behzad Salami, Morteza Saheb Zamaniand Ali Jahanian [20] VARIUS (open source tool) , ACE , Hspice VMAP (variation map aware placement)

Power delay is reduced upto 7.2% as compared to other conventional placement algorithms Leakage power consumtion , critical path , threshold voltage , activity of nets , cost , power dealy product decreased by 7.2% with less than 16.8% standard deviation Feasible study of VMAP for real industry FPGA chips PDP (power delay product ) is main optimisatio n parameter because of trade off between power and delay of the product leakage power contributes to total power consumption. process variation is an important challenge in nano-scale technologies Markov Clustering-Based Placement Algorithm for Hierarchical FPGA -2011 DAI Hui,ZHOU Qiang and BIAN Jinian [21]

-- Cluster based FPGA placement algorithm , markov clustering algorithm Half perimeter evaluation model is replaced by minimm spanning topological tree evaluation model for calculating net wirelength Wirelength is 22.3% shorter than hierarchical FPGA placer Factors like power and timing should also be optimised Trade off between partitionin g and cluster based algorithm for good quality runtime Markov Clustering algorithm is useful in decreasing the total wirelength,tim ing and power

A standard cell placement algorithm of optimising multiple objects-2002 Wenting hou, xianlong hong, weimin wu and yici cai [22]

ULTRA SPARC workstatio n in C language Congestion and timing driven placement Maximum congestion decrease by 10% , maximum delay is unchanged

Timing , decrease in congestion of wires=10%, delay decrease=30%

-- For minimising delay and congestion critical paths and cells placement have to be changed

DRAGON : standard cell placement tool for large industry circuit-2000 Maogang wang, xiaojian yang and majid sawafzadeh [23]

Dragon

2000 Top down hierarchical approach to develop dragon 2000

Dragon 2000 produces better placement results ,

Wirelength , runtime , congestion, better placement results=1.4%, speed= 2X of highly optimised commercial tools

-- -- Top down approach is used for wirelength minimisation for good performance Optimal capacitor placement using deterministic and genetic algorithms-2000 Maurizo Delfanti, Gianpietro P. Granelli Paolo MaranninoandMa rio Montagna [24]

-- Branch and

bound , genetic algorithm

Hybrid of both algorithms is used to so that placement cost of the capacitor is reduced upto 16% as compared to incomplete branch and bound technique

16% saving in cost with respect to branch and bound solution

-- -- Branch and bound algorithm is used to reduce linear

programming calculations

A new timing driven standard cell placement algorithm-2003 Jun Cheng Chi, Jei Ming Feng and Mely Chen Chi [25] Cadence hyper extract , synopsis design time QUAD quadrisection based placement algorithm Timing driven partitioning method can produce placement with short time delay

Wirelength , moment of cell , region in which cell is to be placed

-- -- The algorithm uses sum of timing delays of all nets in circuit as cost function,timin g driven partitioning can reduce placement timing delay Plic Place : a

novel constructive algorithm for placement -2003 Renato Hentschke and Ricardo Reis [26]

C++ Plic Place ,

cluster growth , quadratic placement , horizontal bi partitioning force directed placement Improvement in wirelength upto 39.5% as compared to random

algorithm , congestion improvement by 48.8%

Running time , congestion improvement= 48.8% , wirelength improvement= 39.5% Other spanning trees should be tried , this algo may work for cluster placement , floorplanni ng and large size cell placement CPU time is a drawback when designing larger circuits

Pic Place is based on heuristics which can be beneficial for initial placement Sensor placement for effective coverage and surveillance in distributed sensor networks-2003 Santpal Singh Dhillon and Krishnendu Chakrabarty [27] C MAX_AVG_ COV and MAX_MIN_ COV MAX_AVG_COV maximise the average coverage of the grid points and MAX_MIN_COV maximise the coverage of the grid point that is covered least effectively Threshold voltage , quality of sensor

Improving the scalability of data centre networks with traffic aware virtual machine placement -2010 Xiaoqiao Meng, Vasileios Pappas, Li Zhang [28]

C Cluster and

cut , VM Min K cut

Cluster and cut is 10% more efficient and CPU time is also less

-- -- --

Optimality and Scalability Study of Existing Placement Algorithms –2004 Chin Chih Chang, Jason Cong Michail Romesis Min Xie[29]

C , cadence Qplace

PEKO

algorithm Wirelength produced is 1.59 – 2.40 times optimal in worst case and 1.43 – 2.12 times optimal on average

Average solution quality of each tool

deteriorates by 9 % to 17% with increases in problem size

-- All the

modules are of fixed size

Use of PEKO algorithm is helpful in generating benchmarks having optimal wirelength and for matching any net degree distribution profile Robust Pole

Placement With Moore’s Algorithm -2014 Robert Schmid, Amit Pandey and Thang Nguyen [30]

Moore’s

algorithm Matlab toolbox – span Parametric formulation of exact pole placemet of linear systems

-- -- -- Pole

placement of LTI systems have been considered using eigen values and eigen vectors A bottom up

approach for placement and compaction of standard modules in VLSI circuit-2013 Dhiraj , Seema Verma and Rajesh Kumar [31]

MATLAB Bottom up

approach Reduction in dead space upto 85-99% , faster than other iterative approaches , very quick and compact solution for hard modules

Minimisation of Cost , area = 85% to 99% could be achieved in very less time

-- Composite block

formation behaves like a hard block so the dead space cant be

accessed in future

The use of the algorithm gives the best possible idea of orientation of the block or the macros to be placed in the module

Fine granularity clustering based placement-2004 Bo Hu and Malgorzata Marek-Sadowska [32]

-- Clustering algorithms –

net absorption and wire length prediction

Useful technique for efficient placers to handle large scale problems

Placement efficiency improvement = 39% to 46%

-- Placement efficiency and quality trade off

Fast placer implementatio n has been proposed and final

granularity technique has been

implemented to handle large scale

problems,use of

Optimisation of Standard Cell based Detailed Placement for 16nm FinFET process–2014 Yuelin Du and Martin D.F. Wong [33]

C++ Algorithm is able to

handle cell flipping and cell switching simultaneously so that optimal solutions an be achieved

Timing , net

congestion -- FinFET has high

parasitic capacitanc e and resistance and edge device degradatio n

FINFET employs a vertical FIN structure due to which transistors have low leakage current and fast switching performance Placement and

routing in computer aided design of standard cell arrays by exploiting the structure of the interconnects graph – Ioannis Fudos , Xrysovalantis Kavousianos , Dimitrios Markouzis and Yiorgos Tsiatouhas [34]

C++ ,

Xilinx DFS and Maze -- congestion Wirelength ,

and timing optimisation

-- -- This paper

gives the details of placement and routing of a cell using DFS algorithm in which traversing is done so as to obtain best possible orientation

A mixed mode placement algorithm for combined design of macro blocks and standard cells – Wu Weimin , Hong Xianlong , Cai Yici , Yang Changqi , Gu Jun [35]

-- Hierarchical mixed mode placement algorithm

Feasible and stable on all test circuits , it is competent for non slicing structure

Placement quality improvement up to 29.4%

Extend this algorithm for solving timing driven mix mode placement problem

-- Partitioning of

cells is also explained in this following inter block global placement,glo bal placement and detail placement

A cells and I/O pins partitioning refinement algorithm for 3D VLSI Circuits-2009 Sandro Sawicki , Gustavo Wilke , Marcelo Johan , Ricardo Reis [36]

-- Portioning

algorithm Number of 3D vias was reduced by 19% , 17% , 12% , 16% when benchmark circuits were designed using 2 , 3, 4 and 5 tiers

Improvement in cells partitioning up to

16.53%,impro vement in cost and net length

-- -- 3D VLSI

circuits have been used for the

implementatio n work using graph partitioning algorithms

Placement for modern FPGA-2005 Wai kei Mak , Hao Li [37]

-- Net based

force directed FPGA placement algorithm

Better than VPR in both wirelength and critical path delay , able to find a legal I/O placement

Shorter Wire length=10.7% shorter critical path =11.5%

-- -- Top down

Reg Place: A high quality open source placement framework for structured ASIC-2009 Ashutosh Chakraborty , Anurag Kumar , David Z Pan [38]

C++ , regular placer

Wirelength

minimisation Placement of up to 1 million cells in 4 hours

Wirelength reduction up to 35%

Incorporat e multi density constraints in global placer which can reduce wirelength penalty associated with site and clock legalisatio n

-- Structured ASIC provides high

performance and short time to market which is of advantage at the time of manufacturing

Post- Placement Pin Optimisation-2005 Jurjen Westra , Patrick Groeneveld [39]

-- Post placement pin optimisation

2.55% reduction in wire length due to restructuring of placement , design is routable if 90% utilisation is achieved.

Critical paths , congestion and reduction in wirelength up t o 2.55%

Automatic ways to determine the pin constraints from the congestion will be valuable

-- Focused on

pin assignment according to which power and ground connections would be made resulting in minimum congestion CROP : Fast and

Effective Congestion Refinement of Placement-2009 Yanheng Zhang and Chris Chu [40]

Tool – CROP (congestio n

refinement of

placement)

-- Improvement in

routing , CROP is independent of any placer and router , techniques – congestion driven module shifting and detail placement

Wirelength

and speed Further improve performan ce and stability

-- CROP is

useful in improving the overall routability,con gestion driven module shifting and congestion driven detailed placement helped to do so

4. CONCLUSION

This paper comprises of different placement algorithms. We conclude that iterations done can improve the runtime. Congestion and delay have been overcome. Wirelength is also a major constraint which has been examined in many papers and has been reduced. Several limitations and future work has also been proposed on which further work could be performed.

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[41] Sherwani,Naveed A, “Algorithms for VLSI Physical Design Automation,” Kluwer Academic Publishers,3rd _{ed. 1998} About the authors

Pragya Sharma Pursuing M.Tech from ITM University Gurgaon in VLSI (Very Large Scale Integration) disciple and have done B.Tech from Gurgaon College of Engineering for Women (MDU), Bilaspur in EEE (Electrical and Electronics). Her main area of interest is Placement and routing in physical designing and digital VLSI design.

Upasana Yadav Pursuing M.Tech from ITM University Gurgaon in VLSI (Very Large Scale Integration) disciple and have done B.Tech from Gurgaon College of Engineering for Women (MDU), Bilaspur in ECE (Electronics and Communication). Her main area of interest is Placement and routing in physical designing and digital VLSI design.

Neeraj Kr. Shukla (IETE, IE, IACSIT, IAENG, CSI, ISTE, VSI-India), an Associate Professor in the Department of Electrical, Electronics & Communication Engineering, and Project Manager – VLSI Design at ITM University, Gurgaon, (Haryana) India. He received his PhD from UK Technical University, Dehradun in Low-Power SRAM Design and M.Tech. (Electronics Engineering) and B.Tech. (Electronics &