CPU
The CPU is made up of three major parts.
Register set
The register set stores intermediate data used during the execution of the instructions.
The ALU performs the required micro operations for executing the instructions.
Stack Organization
A useful feature that is included in the CPU of most computers is a stack or LIFO list.
Stack pointer
Stack operations
The two operations of a stack are – insertion of items
Stack operations – push and pop
The operation of insertion is called push.
The operation of deletion is called pop.
Register stack or Memory stack
Register stack
Let us consider a 64 word register stack.
3 items are placed in the stack: A, B and C. Item C is on the top of the stack. Therefore the content of SP is 3.
To remove the top item, the stack is popped by reading the memory word at address 3 and decrementing the content of SP.
To insert a new item, the stack is pushed by incrementing SP and writing a word in the next higher location in the stack.
In a 64 word stack, the stack pointer contains 6 bits because 26 = 64
The 1 bit register FULL is set to 1 when the stack is full.
the 1 bit register EMTY is set to 1 when the stack is empty.
Initially, SP is cleared to 0, EMTY is set to 1, and FULL is cleared to 0, so that SP points the word at address 0 and stack is marked empty and not full.
Memory stack
A stack can exist as a stand alone unit or can be implemented in a RAM attached to a CPU.
PC points at the address of next instruction in the program.
AR points at an array of data.
SP points at the top of the stack.
PC is used during the fetch phase to read an instruction.
AR is used during the execute phase to read an operand.
The initial values of SP is 4001. The stack grows with decreasing addresses.
Thus the first item stored in the stack is at address 4000,
The second item stored in the stack is at address 3999,
Memory stack – push operation
We assume that the items in the stack communicate with a data register DR.
The stack pointer is decremented so that it points at the address of the next word.
Memory stack – pop operation
A new item is deleted with pop operation as follows:
Stack limits
Most computer do not provide hardware to check for stack overflow (full stack) or underflow (empty stack).
The stack limits can be checked by using 2 processor registers:
one holds the upper limit (here 3000)
After a push operation, SP is compared with the upper limit register.
The 2 microoperations needed for either the push or pop are –
Arithmetic expression
Different representation of Arithmetic expression
Infix notation
Prefix or Polish notation
RPN
-RPN conversion
The expression A * B + C * D
RPN notation evaluation
Scan the expression from left to right.
Conversion to RPN
Consider the expression – (A+B)*[C*(D+E)+F]
Stack operations
Consider the arithmetic expression – (3*4)+(5*6)
Instruction Formats
Instruction Formats
The most common fields found in the instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register.
Address Field of an Instruction Formats
Address Field of an Instruction Formats
Operands residing in memory are specified by their memory address.
Register address
Register address
Let us consider a CPU has 16 processor registers (R0 to R15).
Register address field = 4 bits
The binary number 0101 will designate register R5 .
CPU organizations
Computers may have instructions of different lengths containing varying number of addresses.
Types of CPU organizations
1. Single accumulator organization
2. General register organization
Single accumulator organization
All operations are performed with an implied accumulator register.
Example
The instruction for an arithmetic addition may be written in an AL as
ADD X
Here, X is the address of the operand
The ADD instruction results in the operation
General register organization
General register type computers employ two or three address fields in their instruction format.
Example
The instruction for an arithmetic addition may be written in an AL as
ADD R1, R2, R3
Example continued
The number of address fields in the instruction can be reduced from 3 to 2 if the destination register is same as one of the source registers.
Thus the instruction ADD R1, R2
Stack organization
Computers with stack organization would have PUSH and POP instructions which require an address field.
Thus the instruction PUSH X
Stack organization continued
Stack organization continued
Example – ADD
This operation pop the two top numbers from the stack, add the numbers and push the sum into the stack.
Influence of number of addresses on computer programs
Let us consider the arithmetic statement –
X = (A+B)*(C+D)
Influence of number of addresses on computer programs
We assume that the operands are in memory addresses A, B, C and D.
3 address instructions
Computers with 3 address instruction format can use each address field to specify either a processor register or a memory operand.
3 address instructions
ADD R1, A, B R1 M[A] + M[B] ADD R2, C, D R2 M[C] + M[D] MUL X, R1, R2 M[X] R1 * R2
3 address instructions
Advantage –
it results in short programs when evaluating arithmetic expressions.
Disadvantage –
2 address instructions
Two address instructions are most common in commercial computers.
Here each address field can specify either a processor register or a memory word.
2 address instructions
MOV R1, A R1 M[A]
ADD R1, B R1 R1 + M[B] MOV R2, C R2 M[C]
ADD R2, D R2 R2 + M[D] MUL R1, R2 R1 R1 * R2
1 address instructions
One address instruction use an implied accumulator (AC) register for all data manipulation.
1 address instructions
LOAD A AC M[A]
ADD B AC AC + M[B] STORET M[T] AC
LOAD C AC M[C]
1 address instructions
All operations are done between the AC register and a memory operand.
0 address instructions
The name “zero address” is given to the stack – organized computer because of the absence of an address field in the computational instructions.
0 address instructions
PUSH A TOS A PUSH B TOS B
ADD TOS (A+B)
PUSH C TOS C PUSH D TOS D
ADD TOS (C+D)
0 address instructions
TOS stands for top of stack
RISC instructions
RISC – Reduced Instruction Set Computer
✔ Use load and store instructions when communicating between memory and CPU.
RISC instructions
The program to evaluate X=(A+B)*(C+D) is as follows –
LOAD R1, A R1 M[A]
LOAD R2, B R2 M[B]
LOAD R3, C R3 M[C]
LOAD R4, D R4 M[D]
Addressing mode
The operation field of an instruction specifies the operation to be performed.
This operation must be executed on some data stored in computer registers or memory words.
Addressing mode
Addressing mode techniques are used to–
✔ Give programming versatility to the user
Mode field
The operation code specifies the operation to be performed.
Note:
There may or may not be an address field in the instruction.
If there is an address field, it may designate a memory address or a processor register.
Types of addressing modes
✔ Implied mode
✔ Immediate mode
✔ Register mode
✔ Register indirect mode
✔ Autoincrement or autodecrement mode
✔ Direct address mode
✔ Indirect address mode
✔ Relative address mode
✔ Indexed addressing mode
Implied mode
In this mode the operands are specified implicitly in the definition of the instruction.
Note:
Immediate mode
In this mode the operand is specified in the instruction itself.
Note:
Register mode
In this mode the operands are in registers that reside within the CPU. The particular register is selected from a register field in the instruction. A k – bit field can specify any one of 2k registers.
Note:
Register indirect mode
In this mode the instruction specifies a register in the CPU whose contents give the address of the operand in memory.
Note:
Autoincrement or autodecrement mode
This is similar to the register indirect mode except that the register is incremented or decremented after (or before) its value is used to access memory.
Note:
Direct address mode
In this mode the effective address is equal to the address part of the instruction. The operands resides in memory and its address is given directly by the address field of the instruction.
Note:
Indirect address mode
In this mode the address field of the instruction gives the address where the effective address is stored in memory.
Note:
Relative address mode
In this mode the content of the program counter is added to the address part of the instruction in order to obtain the effective address.
Note:
Indexed addressing mode
In this mode the content of an index register is added to the address part of the instruction to obtain the effective address.
Note:
Base register addressing mode
In this mode the content of a base register is added to the address part of the instruction to obtain the effective address.
Note:
Numerical Example
Let us consider there is a two – word instruction at address 200 and 201.
Types of computer instruction
1. Data transfer instructions
2. Data manipulation instructions
Data transfer instructions
Data transfer instructions move data from one place in the computer to another without changing the data content.
Data manipulation instructions
Data manipulation instructions
Types of data manipulation instructions –
1. Arithmetic instructions
2. Logical and bit manipulation instructions
Arithmetic instructions
The 4 basic arithmetic operations are addition, subtraction, multiplication and division.
Logical and bit manipulation instructions
Logical instructions perform binary operations on strings of bits stored in registers.
Shift instructions
Shifts are operations in which the bits of a word are moved to left or right.
Program control instructions
Subroutine
A subroutine is a self contained sequence of instructions that performs a given computational task.
Subroutine
Each time a subroutine is called, a branch is executed to the beginning of the subroutine to start executing its set of instructions.
Subroutine
The instruction that transfers program control to a subroutine is known as ‘call subroutine’ or ‘jump to subroutine’ or ‘branch and save address’.
Program interrupt
It refers to the transfer of program control from a currently running program to another service program as a result of an external or internal generated request.
Interrupt procedure
1. The interrupt is usually initiated by an internal or external signal
2. The address of the interrupt service program is determined by the hardware
Program status word (PSW)
The collection of all status bit conditions in the CPU is sometimes called a Program status word or PSW. The PSW is stored in a separate
Supervisor mode
User mode
External interrupts
Examples that cause external interrupts –
• I/O device requesting transfer of data, • I/O device finished transfer of data,
• Elapsed time of an event,
Internal interrupts
It arise from illegal or erroneous use of an instruction or data.
Examples of interrupts caused by internal error conditions
-• Register overflow,
• Attempt to divide by zero, • An invalid operation code, • Stack overflow,
• Protection violation
Difference between internal and external interrupts
Internal interrupt is initiated by some exceptional condition caused by the program itself rather than by an external event.
Difference between internal and external interrupts
If the program is rerurn, the internal interrupts will occur in the same place each time.
Software interrupt
External and internal interrupts are initiated from signals that occur in the hardware of the CPU.
A software interrupt is initiated by executing an instruction.
Software interrupt
Examples
A program written by a user must run in user mode.
CISC
RISC
In the early 1980s, a number of computer designers recommended that computers use fewer instructions with simple constructs so they can be executed much faster within the CPU without having to use memory as often.
Overlapped register window
• The system has 74 registers (R0 – R73). • R0 – R9 are global registers.
• Global registers hold parameters shared by all procedures.
• The other 64 registers are divided into 4
Overlapped register window
• Each register window consists of 10
local registers and 2 sets of 6 registers common to adjacent windows.
• Local registers are used for local
variables.
Overlapped register window
• Only 1 register window is activated at
any given time.
• A pointer indicates the active window.
Overlapped register window
• The high registers of the calling
Overlapped register window
• For example procedure A calls
procedure B.
• Registers R26 – R31 are common to
both procedures.
Overlapped register window
• Procedure B uses local registers R32 –
