0.18 µm CMOS low power standard cell library

Rochester Institute of Technology

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Theses

Thesis/Dissertation Collections

10-1-2003

0.18 µm CMOS low power standard cell library

Suryadi Gunawan

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0.18

~m

CMOS Low Power Standard Cell Library

by

Suryadi Gunawan

A Thesis Submitted

III

Partial Fulfillment of the Requirements for the Degree of

Master of Science

III

Computer Engineering

Dr. Kenneth

w.

Hsu

Professor, Department of Computer Engineering

Principal Advisor

Dr. Pratapa V. Reddy

Professor, Department of Computer Engineering

Committee Member

Dr. Karl Hirschman

Associate Professor, Department of Microelectronic Engineering

Committee Member

Department of Computer Engineering

Kate Gleason College of Engineering

Rochester Institute of Technology

Rochester, New York

Release Permission

Rochester Institute of Technology

0.18 Jlm CMOS Low Power Standard Cell Library

I, Suryadi Gunawan, hereby grant permission to Wallace Library of Rochester Institute of

Technology to reproduce my thesis in whole or in part. Any reproduction will not be

commercial use or profit.

Abstract

With

the

increasing

number oftransistors

in

a single

integrated

_circuit, power

is

becoming

one ofthemajor

issues in integrated

circuit

development.

This

issue

requires

additionaleffort

from designers

in

ordertoproduce

lower

power

designs. The

purpose of

this thesis

is

to

develop

a standard cell

library

using

Taiwan

Semiconductor

Manufacturing

Company's 0.18-micron

CMOS

technology.

The

library

cells consume

less

power compared to thevendor

library

provided

by

MOSIS.

Although

a reduction

in

power consumption

is

themainobjective

in

thiscell

library,

the

timing

delay

and area are

two aspects thatcannot

be ignored.

However,

a sacrifice

has

to

be

made

in

timing

delay

or area

in

ordertoachievethegoal of

lower

power.

In

order to produce a

library

that contains

low

power _cells, a new

design

techniquemust

be

used while

keeping

in

mind thatpower reduction should not

adversely

affect othera spects o

ft

he

c ell.

D

rawbacks

i

n

p reviously p

ublished

d

esigntechniques

will

be

analyzed and a new

design

technique composed of parts of previous techniques

will then

be

postulated.

The

new technique will then

be

compared against the

best

technique

currently

available.

A

design

technique

for

standard cell

library

development

can

be

determined

based

ontheresults ofthatcomparison.

The

new

design

technique can then

be

implemented

into

a cell

library.

The

cell

cell

library

will then

be

compared to a similar technique used

by

the vendor

library,

determining

that the produced cells consume

lower

amounts of power.

Each

c ell will

then

be

characterized

by

timing

delay,

_area, truth

tables,

dimensions,

and

input

Acknowledgement

This

thesis could not

be

completed without the

helps

and supports

from

individuals

and companies.

Therefore,

to recognize _{their efforts,}

I

would

like

to express

my

gratitudeandthanks to:

1.

Dr.

Kenneth W.

Hsu,

my

advisor,

for

his

guidance, advice and

help

from

choosing

the topicuntilthe

finish

ofthe thesis.

2.

Dr.

Pratapa V.

Reddy

and

Dr. Karl

Hirschman,

my

thesiscommittee_members,

for

thesissuggestions.

3.

My

family

for

their

financial

support and encouragement.

4.

Tanner

Research,

Inc for

the permission to use their

Digital Low Power

Standard Cell

Library

for MOSIS TSMC CMOS 0.25

um

Process

Deep

Sub-Micron Technology.

5.

Mentor

Graphic

for

theirsupportto solve simulationtoolproblems.

6.

MOSIS

for

their

TSMC

CMOS 0. 1 8

urn process parameters

Also,

I

would

like

to

say

thanks to companies or

individuals

who

indirectly

helped

Table

of

Content 17

Abstract

iii

Acknowledgement

v

List

of

Figures

ix

1. Introduction

1

2. MOSFET

Modeling

6

2.1. MOS Structure

with

4

Terminals

6

2. 1

.

1

.

Drain

Current Behavior

7

2.1.2. Gate

capacitance

behavior

14

2.1.3.

Small

Geometry

Effects

15

2.2. BSIM3

22

3. Power Dissipation in CMOS Circuit

25

3.1. Types

of

Power Dissipation

25

3.2. StaticPower

25

3.3. Dynamic Power

29

3.4.

Short Circuit Power

30

3.5. Total Power Dissipated

32

4. Low Power Design

Methodology

33

4.1.

Types

of

Low Power

33

4.2. LowVoltage

34

4.3. Low Average Power Consumption

35

4.4. Low Power Techniques

36

4.4. 1

.

Changing

the

logic

style

36

4.4.2. Logic

Restructuring

41

4.4.3.

Input

Ordering

44

4.4.4. Better Layout

46

4.4.5. Transistor

Sizing

49

4.4.6. Buffer

/

Keeper Usage

47

4.4.7. Gated Clock

51

4.4.8. Dual Voltage

51

5.2.2. I/O lines /port

56

5.2.3.

Geometry

56

5.2.4.

Routing

Metal

56

5.2.5. Placement

56

5.3. Published Standard Cell

Methodology

57

5.3.1. Example

Methodology

1

57

5.3.2. Example

Methodology

2

59

5.3.3. Example

Methodology

3

60

6. Development

Strategy

for Low Power CMOS Cells

62

6.1.

SPICE FILE

62

6.2. Power Reduction

63

6.2. 1

.

Power

Supply

Reduction

63

6.2.2. Logic

Style

64

6.3. Experiment

71

7. Proposed Standard Cell

Library

80

7.1.

Standard Cell

Library Methodology

and

Design

Strategy

Implemented

80

7.2.

Standard Cell

Library

83

7.2.1. 1-BitAdder

84

7.2.2. 2x2 Input AND

OR Gate

(A022)

86

7.2.3. 2x2 Input AND NOR

Gate

(A0I22)

88

7.2.4. Non

Inverting

Buffer

(BUF1)

90

7.2.5. 4X Drive Buffer

(BUF4)

92

7.2.6. 4X Drive

Inverter

(BUFI4)

94

7.2.7. Tri

State Buffer

(BUFZ)

96

7.2.8. D

Flip Flop (DFF)

98

7.2.9. D

Flip Flop

with

Asynchronous Clear

(DFFC)

100

7.2.10. D

Flip Flop

with

Asynchronous Preset

(DFFP)

102

7.2.11. D

Flip Flop

with

Asynchronous Preset

and

Clear

(DFFPC)

1 04

7.2.12. Inverter

(INV)

106

7.2.13. Dual Inverter

(INV2)

108

7.2.14. Tri

State Inverter

(INVZ)

110

7.2.15.

Latch(LAT)

112

7.2.16. Latch

with

Asynchronous Clear

(LATC)

114

7.2. 17. Latch

with

Asynchronous Preset

(LATP)

116

7.2.18. Latch

with

Asynchronous Preset

and

Clear

(LATPC)

118

7.2.19. 2 Input Multiplexer

(MUX2)

120

7.2.20. 2 Input NAND

(NAND2)

122

7.2.21.

2 Input AND

(ATND2)

124

7.2.22. 3 Input NAND

(NAND3)

126

7.2.23. 3 Input AND

(AND3)

128

7.2.24. 4 Input NAND

(NAND4)

130

7.2.25. 4 Input

AND

(AND4)

132

7.2.27.

2 Input

OR

(0R2)

136

7.2.28.

3 Input NOR

(NOR3)

138

7.2.29. 3 Input OR

(OR3)

140

7.2.30.

4InputNOR(NOR4)

142

7.2.31.

4 Input OR

(OR4)

144

7.2.32. Schmitt Trigger Inverter

(SINV)

146

7.2.33. 2 Input Exclusive NOR

(XNOR2)

148

7.2.34.

2 Input Exclusive OR

(XOR2)

150

8. Conclusion

152

8.1.

Summary

152

8.2. Future Works

152

References

1 54

Appendix A

158

List

of

Figures

Figures

Figure 1-1. Heat

generated

by

CPU

4

Figure 2-1.4

terminal

MOS

structure

7

Figure 2-2.

Relationship

between

the

drain

current and

drain bias

11

Figure 2-3. The

gate capacitance ofthe

FET

structure

14

Figure 2-4. FET depletion

regions showsthat the gate

induced

depletion

region overlaps

withthesource and

drain depletion

regions

16

Figure 2-5. FET depletion

region shows charge

sharing between

thesource and

drain. 17

Figure 2-6. The

channel electron

mobility

versus gate voltage of athinoxide

FET

1 8

Figure

2-7. (a),

original

barrier

without

drain bias

applied

(b). Lowered barrier

afterthe

drain bias

applied.

The

dashed line

showstheexpected

barrier

19

Figure 2-8. Potential

profiles

in

FETs

with channel

dopant

redistribution

due

to

oxidation-enhanced

diffusion

21

Figure2-9.

BSHVI3

parameters

23

Figure 3-1

.

CMOS

model

describing

parasitic

diodes

26

Figure 3-2. Temperature

versus

leakage

current

in different feature

size

27

Figure 3-3.

Relation

subthreshold currentwiththe

Vgs in different Vt

28

Figure 3-4. Relation between Vt

and power

supply

depending

onthe

feature

size .

28

Figure 3-5. Circuit

model

load

29

Figure 3-6. Transient

waveform of

inverter

31

Figure

4-1. Standard CMOS

Architecture

37

Figure4-3.

Domino Logic Architecture

39

Figure 4-4.

Example

of

MCM Architecture

40

Figure4-5.

Power Dissipation

versus

Supply

voltage

41

Figure4-6. Adder

delay

versus

Supply

voltage

42

Figure 4-7. Transistor level

of

8

inputs

NAND

gate

42

Figure4-8. Schematic

of

8 inputs NAND

gate

40

Figure 4-9. Different implementation

of

4

input AND

gate

44

Figure 4-10. Two

input

NAND

power ratio

45

Figure 4-11. Input ordering

effect on speed

46

Figure 4-12. Elmore

delay

model

47

Figure 4-13.

Two

different layout

techniques

in

creating

transistorwith wide width

47

Figure 4-14. Power

consumption

is

not always minimized with minimum

device sizing

50

Figure5-1. Example

of

floorplan

55

Figure 5-2a.

Methodology

1

58

Figure 5-2b. Design strategy 1

58

Figure 5-3a.

Methodology

2

59

Figure 5-3b.

Design strategy 2

60

Figure 5-4a.

Methodology

3

61

Figure 5-4b. Design strategy 3

61

Figure 6-4. Selector

Logic

67

Figure

6-5.

Transmission

gate

logic

68

Figure6-6.

4

input

NAND using TGMOS logic

69

Figure 6-7. TGMOS logic

architecture

70

Figure

6-8. Han Carlson Adder

72

Figure

6-9. Kogge Stone

adder

72

Figure 6-10. Brent

Kung

adder

73

Figure 6-11. 8-bit Han Carlson

adder

74

Figure

6-12. 8-bit Han Carlson

adder

layout using TGMOS

library

75

Figure

6-13. 8-bit Han Carlson

adder

layout using

standard

CMOS

library

75

Figure 6-14. 8-Bit Han

Carlson Adder Power Dissipation using

TGMOS

Cell

Library

76

Figure

6-15. 8-Bit Han Carlson Adder Power Dissipation using

Standard CMOS

Cell

76

Figure

6-16. 2

input

nandgate

implemented using TGMOS logic

78

Figure

6-17. 4

input

or gate

implemented using TGMOS logic

78

Figure 7-1.

Standard Cell

Methodology

used

82

Figure 7-2. Cell

Strategy

used

83

Tables

Table 1-1.

Battery

Comparison Worksheet

3

Table 1-2.

Battery

technology

comparison chart

3

Table 4-1. Results

from

implemented

approaches of

8-input

AND

gate

in

lUm

CMOS

process

43

Table 6-2.

Power Dissipation

of

2

input

norgate and

4

input

nandgate

implemented

Chapter 1

Introduction

In

therecentyears, the

development

of

Very

Large

Scale Integrated

Circuit

(VLSI)

has

advanced and crossed new

boundaries

from

home computing

to

military

equipment.

This

a

dvancement

m akes

i

t

p

ossibleto

p

reduce powerful

p

ortable _electronics, s uch a s

notebook or

laptop

computers, personal

digital

assistants

(PDA),

cell _{phones, tablet}

PCs

and so on.

These

systems

have

multiple

functions

and

increased

capabilities over their

predecessors.

For

_example, cell phones can now

have integrated PDA

capabilities such

as music playback,

built-in

cameras,

creating

office

documents,

and even

connecting

to

the

internet. Notebook

computers are also

increasing

in

capability

and

may

soon replace

desktop

p

ersonal c_omputers, e

specially

s

ince

t

hey

can

p

erform a

dvanced d igital

s

ignal

processing

just

aswell as

home

computers.

Multi-functionality

refersto the

ability

of a

device

to

have

the

necessary hardware

to accommodate multiple

functions.

For

example, a cell phone that

is integrated

with a

PDA

must

have

an

RF

transmitter to connect to the cellular_network, an

LCD

screen

for

users to

interact

with,speakers to

listen

_{to music,} and a

way for

usersto

backup

data,

etc.

This supporting hardware

requires additional power.

In

_{addition, the}

device

must

be

capable of_producingresults

in

realtime.

A

good

the user's ear.

It

will

be

obsolete

if

the result

is

produced after a couple of minutes or

hours

[4].

It

is known

thatmore

energy

is

needed

in

ordertoproduce

fast devices.

Yet

the examples of portable electronics mentioned above are able to execute

their

functions

with a portable

energy

sourceora

battery. Batteries

have

become

the

life

source

for

these portable electronics,

meaning

the

energy

consumed

from

the

battery

must

be

as

little

as possible

in

ordertocontinue uninterrupted operation ofthe

devices.

The

question

is

how

can we achieve

better efficiency

with

higher

speed and

lower

power consumption?

Will

the solution

be

a

bigger

or

better

power _source, so that either

theuser

has

to

bring

a

bigger device

or

pay

more

money

in

order

for

the

device

tooperate

as

designed? How do

we

interpret

the

meaning

of portability?

Being

portable

involves

greater

accessibility

and

being

easy

to carry.

A bigger

and more powerful

battery

would

maketheportable

device

much

heavier

and sizewouldthen

be

an

issue.

Will selling

the

device

at a

higher

price

in

order to use a

better,

smaller

battery

be

a good solution?

It

may be

feasible,

but

manufacturers want their products to sell quickly.

Therefore

they

will

have

to

keep

theirprices

low

enough to attract additional customers.

The

tradeoffs

can

be

seen

in

table

1-1

and table

1-2.

NiMH,

NiCd

and

Lilon

are the three

battery

technologies that are

commonly

used

for

portable electronics.

Table 1-1

explains the

relationship between

price,

capacity

and size of the

different

battery

technologies.

Furthermore,

a

better-performing battery

may

not

necessarily

mean a safer one

for

NiMH AA NiMH AA NiMH C NiCd AA NiCd AA NiCd C Lead Acid n/a

Cell Size Voltage

Capacity

(Ah)

Energy

(kJ)

Volume_(cmA3) Weight

(g)

1.2 1.2 1.2 1.2 1.2 1.2 12 1.3 5.62 1.9 8.21 4.0 17.2B O.B 2.59 1.D 4.32 2.5 10.B0 4.0 172.B0

nA3| Wfeight

(g)

Cost kJ/$

kJ/fl

kJ'CinA3 7.9 27 $0.66 B.51 0.21 0.71

7.9 27 $1.15 7.14 0.30 1.04 24.4 BD $2.33 7.42 0.22 0.71

7.9 21 $0.27 9.B0 0.12 0.33

7.9 21 $0.49 B.B2 0.21 0.55

24.4 72 $1.05 10.29 0.15 0.44

643 1B72 $8.40 20.57 0.10 0.27

Table1-1.

Battery

Comparison

Worksheet

[47]

I

' i

Manufacturer TypejChemistiy

LT ,INominal NominalL. , ,

Nominal' _{|_ iUsable}

Voltage^

^f^^iCycles

i_Amp-hrsWatt-hrs ;

Watt

hr/kg

-Watt-hrf&er[discharge

[

rate

j

BYT 'AA [Lilon 3 6 ;0.75

[2.7

600+ 135 365 1.5A

1

! '

Tadiran AA [LiMetal 3 0 T8 [2.4 700 141 324 10mA

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:

|

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told

Peak LAA

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GoldPeak [AA [NiMH

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IPowercache Box JSupercapacitor

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.2500F 3.7 200,000+: 6 1800 A

Another

solution

is

to produce a

less

_powerful,

slightly

slower and more power efficient

device.

This

approach seems more _reasonable,

especially

with

CMOS

(Complementary

Metal

Oxide

Semiconductor) being

the

currently

used

technology..

CMOS

technology

has

been

proven to

be

a

low-power

design,

and

it

has been

shrunk to

very

small _sizes,

currently 90nm.

Even

though

CMOS

consumes small amounts of power, current

technology

has

enabled companies to manufacture

integrated

circuits

containing

hundreds

ofmillions oftransistors.

These

advances mean that the small size of

CMOS

uses

very little

_power, and what

little

power

is

used will

be

reduced

by

a

factor

of

108.

All

thepower used

in

switching

will

be dissipated

as

heat.

This

heat

dissipation

problem

is

worsening

withthe

increasing

number ofthe transistors

in

IC

as shown

in

the

figure

1-1.

1000

100

CM

10

v> C a s_

S

O 0_

Rocket

Nozzle

Nuclear

Reactor

808

Hot-too

800

80S

~

A38

sos'"-'

28

, --/

Pentium

?48

197

198

*

+

Sun's

Surface

199

Year

200

201

Thus,

by looking

attheneedsof

low-power

devices,

a

low-power

cell

library

may

help

easetheproblem

by

reducing

power consumption atthesmallest

logic

levels.

Low

power

devices

are needed

in

many

fields,

such as theautomotive

industry,

medicine, the military,spaceexploration,and soon.

In

theautomotive

industry,

electronics

installed in

thecar will

drain

thecar's

battery

if

they

usetoomuchpower.

This

issue is

becoming

more

important

as

batteries

could

likely

be

the

only energy

source

powering future

cars.

Military

and space exploration

have

similar_needs,

namely low

power communication

devices

suchas wireless communications

devices.

These devices

use a

lot

of powertotransmita_signal,withtheamount of power

being

dependent

onthe

distance. The

greaterthe

distance,

themorepowerthe

device

will consume.

In

theouter

space as well as

in

enemy

territory,

power

is

ascarce

commodity

and communication withthecommand centercannot

be lost. Low

power

devices

arenecessities

in

these areas.

The

field

of medicine also requires

low-power devices for

prosthetic

devices

built

to save

lives

and

help

people.

Prosthetic

devices

are powered with a small portable

Chapter

2

MOSFET

Modeling

This

work will

be

heavily

dependent

on a simulator

in

order to produce the

standard cell

library

and characterize each cell.

In

order to run the

simulator,

the

MOS

structure and a

SPICE

FET

model must

be defined. MOS

structure

is defined

by

how

the

FET

is

functioning

compared to the physical properties ofthe

FET.

This

includes

the

number ofterminals available

for

the

MOS

structure.

Each

terminal can

be

analyzed

for

its

effect

in

the

behavior

ofthecurrent

flowing

from

oneterminal to another.

A SPICE FET

model

is

consisted of a tabular set of model parameters that

describe

a particular

FET

technology.

These

parameters are needed

in

order to produce

characteristics ofthe

device

during

thecircuit simulation.

This

is

achieved

by

plugging

thecharacteristics

into

the

device

equationsthatare

implemented in SPICE.

The

rest ofthis chapter

discusses

the

SPICE

FET

model and

its

relation to the

actual

MOSFET. These discussions

aretaken

from [48].

2.1.

Four-terminal

MOS Structure

Although

there are two other

MOS

_structures, the two-terminal structure and the

three-terminal structure, this work will

only look

at the

four-terminal MOS

structure.

Thus,

a

four-terminal

MOS

structure

is

the

only

structurethatwill

be

analyzed.

2-Vds,

and

Vbs. The

current

behavior

ofthis structure

is

morecomplicatedcomparedto the

otherstructures.

The

current

flows

from

thesource to the

drain

whilethegate modulates

it.

The

capacitance

existing between

eachconnected terminalplaysarole

in

thecurrent's

behavior.

Further

analysis

is

required.

L

*1

r

n+

J

P"

v^

rr

I

Figure2-1. Four-terminal MOSstructure

2.1.1.

Drain

Current Behavior

The

current

density

in

a material

conducting

electric current

is

defined

as

following:

j

=-qnv

(2-1)

n=_the

conducting

charge

density

v=

thecarrier

velocity

Using

the

Ohm's law

approximation

for

thevelocity/field relationship:

v=_pE

(2-2)

E=

field

p

=the

mobility

constant

Equation

(2-1)

can

be

modifiedtoproduce:

j

=-qnpE

(2-3)

Based

on

Drude,

the

theory

of conduction that can

be

applied

for

conduction

in

any

j

=_oE

(2-4)

cr - the

material's_conductivity

Then

thecoefficientof

resistivity

can

be found:

oE=_-qnpE

a =

-qnp

p

=

I

=

-J-(2-5)

a

qnp

Knowing

thecoefficient ofresistivity, theresistance

for

the

conducting

material

is

found

to

be:

xW _xWqnp

W

=

the

FET

width

y

=

distance between

source and

drain

x=

thicknessofthe

conducting layer (assumed

to

be uniformly doped

and

perfectly

flattened)

If

x

is

consideredto

be very

small comparedto

W

andy, then the

conducting layer

can

be

imagined

as two-dimensional charge

layer,

andthe areal

inversion

charge can

be defined

as:

QM^xqn

(2-7)

Substituting (2-7)

into

(2-6)

producestheresult:

R

= - y

xW

MWQtoiy)

vds=idsR

I-V*

-WQ^y)V*

(2-8)

R

v

In

order to analyze

1^

, the voltage

drop

across a small part ofthe channel must

be

dR is

the

derivative

of equation

(2-6),

and

by

plugging

it into

(2-9),

we get:

dV*

=

wn t

^dy

(2_10)

Equation

(2-10)

requires

Qim{y)

to

be found.

In

a

depletion

and

inversion

_condition, the surface potential

</>s

reflects the

potential

drop

due

to the appliedgate

bias.

The

total potential

drop

Vgb

is

accounted

for

by

the work

function

difference between

the gate and the silicon

substrate,

and

any

change

layers in

thesilicon.

The

totalpotential

drop

can

be

writtenas:

Vgb=VJb-<t>s{y)-^-(2-11)

Vp

=_the

flatband

voltage

Qs

the totalsurfacecharge

density

induced in

thesubstrate

by

gate

bias

Qs-Qim+QdePl

(2-12)

Qm

=_the

inversion

charge composedof

free

carriers atthe

interface

Qdepi

=_me

depletion

charge

due

to

ionized impurities

The depletion

chargecan

be

expandedto:

Q^iy)

=

(^sqNJ.{y)i

(2-13)

While <ps(y)

is:

^iy)

=

V{y)

+

2t/,f-Vb,

(2-14)

V{y)

=_the

voltage at

any

point

y along

thechannel

due

tothe

drain

voltage

V^

(f>s

= _the

surface potential.

</>f

=the

Fermi

potential.

Substituting (2-14)

into

(2-13)

givestheresult:

Qdep,

(y)

=

[2saqNA

(V(y)

+

2^

-Vbs

f

(2-15)

Qs(y)

=

-c0XK

-vfi-ny)-20f+vbs)

(2-i6)

Thus,

by

using

equation

(2-12)

and

substituting

with equations

(2-15)

and

(2-16),

the

expression

for

Qinv

(

_v) can

be found.

Qinv(y)

=

Qs(y)-Qdepl(y)

0*00

=

-C^

-V

-V(y)-2^f+Vbs]-[2eSiqNA(v(y) +

2^-Vbsf

(2-17)

Using

the

relationship between V

and

V

_b, andtheequation

for

y

:

(2-18)

V =V -V

Y

gb rgs ybs

yJ^fA

(2.19)

Equation

[2-17]

can

be

rewritten asthe

following:

0*

(

v)=

-C

[^

-Vfi-V(y)

-2<Pf\-y

[v(

y)+

2</>f

-Vbs

(2-20)

Using

thesimilar_reasoning,the

Qinv

equation

for

atwo-terminalstructure

is:

QUy)

=

-c0.

Vgb-Vp-2^f-y\2^

(2-21)

and

defining

Vt

to

be:

Vt=Vfb+2<f>f+y\2</>f)\ Qinv(y) = -cm(v,-vl)

(2-22)

(2-23)

This

can

similarly be

appliedto the

QinY

equation

for

three-terminal structures toproduce

theresult:

Qo,v(y)

=

Unlike

the

Qjnv

equations

for

the two-terminalstructure

(2-23)

andthree-terminal

structures

(2-26),

the three-terminal equation

(2-20)

is

shown to

be

more complicated

with respectto

Vt

,

but

it

sharesthesame

fundamental

relationship

shown

between

(2-21)

and

(2-23)

and

between

(2-24)

and

(2-26).

Therefore,

as

Vgb

(2-18)

gets

larger

than

Vt

, the

inversion

layer

is formed

and

drain

current starts

flowing.

2.1.1.1.

Saturation Behavior

The relationship between

Vds

andthe

drain

current

is

shown

in figure

2-2. At low

drain

bias,

the

drain

current

increases

linearly

withthe

drain bias. At larger drain

biases,

the current no

longer has

the same

linear

relationship.

The

voltage at which the

drain

current no

longer

reflects a

linear relationship

with the

drain bias is

called the

Vdsat

.

This

Figure

2-2.

Relationship

betweenthedraincurrent anddrain bias

2.1.1.2.

Sub-threshold

Behavior

Based

on the equation

(2-26),

Qinv

reduces

0

when

Vgs

<

V,

.

This

incorrectly

implies

that

Ids

=

0

.

This incorrect implication

is

caused

by

simplicity

ofexpression

for

the totalsurface charge

Qs

which

is

written asthesum of

Qinv

and

Qdelp

.

This

allowsthe

inversion

charge to

be

calculated without

considering

the

energy band

structure ofthe

MOS

capacitor.

Therefore,

another approach must

be

taken to

determine

the current

behavior

for

thesub-threshold region.

The relationship between

</>s

and

</>f

determines

the region ofthe

drain

current

behavior. For

</>s

<

<f>f

, the

depletion

charge

density

is less

than the

intrinsic

silicon

charge

density

nt

and

is

therefore

very

small.

A depletion

region

forms

at the silicon

surface.

For </>s

>

20

f, the surface

density

exceeds the substrate

doping

concentration

(,.

>

N

_A

)

and

strong inversion

occurs.

For

</>f

<

</>s

<

2(/>f

, there exists a

free

electron

layer

with a

density

less

than the

doping

concentration, andthis

is

the regionthatwill

be

considered.

Assuming

bulk

p-dopedsilicon with complete

impurity

ionization,

the

Fermi

potential

is:

=

kbT

In

fp\

\niJ

<t>f

=

kbT

In

Solving

for free hole

density,

P:

nf

=

np

(2-30)

toproducethe

free

electron

density:

n=

(2-31)

If

the gate

bias

is

_{applied, the} surface _{electron concentration also}

increases

and therefore

changes equation

(2-31)

to:

b,=b/^v

(2-32)

ns

=theelectron concentration atthe silicon surface

ns

=,.

happens

when

</>s

=

(f>f

and the

inversion

ofp-type silicon surface starts.

Strong

inversion

starts when

</>s

=

2tfif

.

Equation

(2-31)

becomes:

nt

=n/'1 kJ

(2-33)

Based

on equations

(2-32)

and

(2-33),

when the surface electron concentration

is

less

than the

bulk hole

concentration,

Qim

Qdepl

.

With

this condition, equation

(2-12)

producestherelationship:

Qdepl

=

Qs

(2-34)

Equation

(2-11)

canthen

be

rearrangedtoproducethesurface potential:

A^-Pj.+TT-(2-35)

Substituting (2-18)

and

(2-34)

into

(2-1

1)

results

in:

ts=Vgs-Vfi-Vbs+^

^ox

(2-36)

Next,

the areal

inversion

layer

charge

density

can

be found:

Qinv=q[n{x)dx

(2-37)

/*=

MirQv*

y

(2-38)

The

equations

(2-36), (2-37),

and

(2-38)

have

thegeneral

form:

(2-39)

A*0^

Equation

(2-39)

describes

the

behavior

of the sub-threshold current

in

general terms.

This behavior

is

heavily

dependent

onthespecific

SPICE FET

models

being

used.

2.1.1.3.

Discontinuity

in Sub-threshold Current

When V

<Vt,

currenttransport

is

dominated

by

the

diffusion

of carriers overthe

channel's potential

barrier,

while

for

V^

>

Vt

current transport

is

dominated

by

drift

due

to the

lateral

electric

field.

The

expressions used to analyze

drain

current

for

above and

below

the subthreshold are approximated.

T

his

c auses

d

iscontinuities

for

Qinv

and

1^

between

the transition sections

from below

sub-threshold to above sub-threshold.

Each

SPICE FET

modeltreatsthe

discontinuity

differently.

2.1.2.

Gate Capacitance Behavior

Gate

capacitance

is

the

largest

capacitive

load

produced

by

the

FET

aside

from

the source-to-substrate and drain-to-substrate capacitances.

Gate

capacitance

is

strongly

affected

by

the

bias

appliedas shown

in

figure 2-3.

r[\=Zz

(a),nobiasesapplied

(b)-^>^^<^0,

V-vgs<K,vds>vdsat

Figure 2-3

a

illustrates

a small capacitance

between

the gate and the other three

terminalswhen there

is

no

inversion layer.

If

the

inversion

layer

is

present andthe

FET

is in

the

linear

region, thecapacitance

existing

between

the

inversion layer

andthegate

is

very

large.

This

condition also

greatly

reduces thecapacitance

between

thegate and the

substrate,

but

the reduction

is

very

small compared to the capacitance

between

the

inversion layer

andthe gate as shown

in

figure 2-3b.

At

the saturation _{region, the} gate

capacitance

becomes

smaller

because

the

inversion layer

nearthe

drain is

not

electrically

connected to the

drain.

However,

gate capacitance

is

still considered

large because

the

inversion layer

nearthesource

is

still_connected,

creating

gate capacitance.

2.1.3.

Small

Geometry

Effects

When MOSFET

was

first

invented,

its geometry

was wide and

long.

Over

the

past two

decades,

its

geometry

underwent

dramatic

changes.

MOSFET

became

smaller

and smaller.

It currently has

a

length

of

90

nm.

The shrinking geometry

creates a

growing list

of problems.

These

problems also affect

SPICE

because

it

was

developed

for

a particular geometry.

The

wide,

long

and simple

MOSFET

SPICE

model

is

becoming

m oreand m ore c omplicated.

T

he

model

i

s e

volving

to accommodatet

hese

growing

effects.

Different

models

have been introduced

in

order to model

MOSFET

more completely.

In

this

thesis,

the

BSIM3 MOSFET

model

is

used.

Below

are

issues

Depletion Region

Overlap

FET

is

basically

a combination of

2

p-n

junctions,

source-to-substrate and

drain-to-substrate,

with the

depletion

region of a

MOS

capacitor.

The

total charge can

be

described

as the sum of the charges

in

the

depletion

and

inversion

regions.

With

its

smaller_{size, the}

junction

depletion

region overlaps thegate

depletion

region as shown

in

figure

2-4.

This

fact

changes the equation

for

total charge

(2-12)

because

the charge

in

the

depletion

region

is less

thanpredicted,

causing

the charge

in

the

inversion

layer

to

be

higher.

Depletion

region

overlap

Figure 2-4. FET depletionregions showsthatthegateinduced depletionregion overlaps withthe source anddrain depletionregions

Source drain

charge

sharing

As

the channel

length

decreases,

the

depletion

region

overlap

problem even

bigger.

The

source and the

drain depletion

regions can overlap.

This overlap

results

in

charge

sharing between

the source and the

drain (figure 2-5).

The g

ate

losses

control

Source/drain

charge

sharing

xi

Figure2-5. FET depletionregion_showingcharge_{sharing between}thesource anddrain.

The

spread ofthe

depletion

region outsidethe channel width

In

a

very

wide

FET,

the

depletion

region caused

by

gate

induction

happens along

the gate.

It

does

not extend out

beyond

the gate edges.

However,

the gate-induced

depletion

region

does

extend outsidethe gate edges

in very

narrow

devices. This

causes

unreliable approximation ofthe charge

in

the

inversion

layer

because

the approximated

inversion layer

is

smallerthan the actual

inversion layer.

Mobility

reduction

due

tothe gate

field

The

carrier

velocity

introduced in

equation

(2-2)

describes

the carrier conduction

in

a

bulk

semiconductor material under

low

fields.

For

a

large

FET,

this

is

a good

approximation.

But

as thegate oxide gets

thinner,

the vertical

field

atthesilicon surface

increases,

resulting in different

mobility.

Figure 2-6

shows that

mobility decreases

with

soc

Gate Voftage(Vj

Figure

2-6. The channel electron_mobilityversus gate voltage of athin oxideFET

Lateral mobility

reductionand

velocity

saturation

As

the

field

gets

larger,

equation

(2-2)

no

longer holds. The relationship between

the carrier

velocity

and the

lateral

field is

no

longer linear.

The

carrier

velocity

will

be

constant

for

some

lateral field. This

phenomenon

is

called carrier

velocity

saturation and

themaximumcarrier

velocity

is

calledthesaturation velocity.

Since

the

lateral

field

varies

along

_{the channel,}

mobility

also varies

along

the

channel.

This

effect makes theapproximation

inaccurate. The

carrier

velocity

saturation

affects the

drain

current saturation as will

be

explained next.

Channel length

modulation

starts to move

away

from

the

drain

and toward the source.

In

other_{words, the}pinch off

point

is

moving

toward the source.

For

longer

channel

devices,

this

doesn't

pose

any

problem.

In

shorter channel

devices,

as the pinch off point moves closer to the source,

the

lateral field

along

the channel

(from

the source to the pinch off

point)

starts to

increase.

This

creates aslight

increase in

the

drain

current.

Series

resistance

Source-drain

resistance

is

larger

than the

drain

and source resistance

in

a

long-channel

FET.

This

does

not result

in

a

drop

in

V^

.

But

this

is

not the case

for

short-channel

FETs. In

fact,

theopposite condition applies.

The

drain

and source resistance

is

much

bigger

comparedto thesource-drainresistance

causing

a

decrease in drain

current.

Drain Induced Barrier

Lowering

(DIBL)

This

phenomenon also affects

Vt

.

In longer-channel

devices,

a

bias

applied to the

drain

does

n ot a

ffect

t

he

channel.

H

_owever,

i

n s

hort-channel d

_evices, a

b

ias

appliedtot

he

drain

will

lower

the thresholdvoltage

(figure 2-7).

T"

0chan

1

^chan

i

v*

(a)

(b)

Figure 2-7. (a). Original barrierwithoutdrain

bias

applied

(b). Lowered barrierafterthedrain

bias

applied.

Punchthrough

DIBL lowers

the

bias

applied to the gate until

drain

current

flows

through the

channel.

Basically,

the gate

is

still able to control the

flow

ofthe current.

However,

if

the

bias

appliedto the

drain

is

large

_enough, gate

may lose

control overthe channel.

This

loss

of control

happens

when the

depletion

region

for

the

drain

and the source are

combined.

The loss

of control

is

called punchthrough.

Hot Carrier Effects

In

a _simulation,

it

is

shown that the velocities ofthe carriers are

distributed in

a

certain way.

As

the

field

increases,

the

distribution becomes

more spread out.

At

the

upper end ofthe

distribution,

therearethe

high-energy

carriers

causing

impact

ionization,

generating

a

hole

and an electron.

In

_{nFET, the}

hole

is

sweptto the

bulk

andtheelectron

is injected into

the oxide.

This

ionization

can

damage

the

device,

and

it is

called

hot

carrier

degradation.

The degradation is

correlated to the substrate current

in

nFETs and

thegate current

in

pFETs.

Gate-induced Drain Leakage

Consider

an nFET

drain

regionwiththe gate

overlapping

the

drain

diffusion.

The

gate

is

then grounded and the

drain is

then

biased causing

the silicon surface to

be

This is

agenerationmechanism, with

holes

swept

into

the

bulk

andthe electrons

into

the

drain,

where

they

appear as a

leakage

current.

This leakage

mechanism

is

called

gate-induced drain

leakage.

Threshold

Voltage Roll-Off

Threshold

voltage roll-off

is

caused

by

the

fabrication

process.

After

the

polysilicon gate

is

defined

by

reactive

ion

_etching,

its

sides are cleaned up.

Depending

on the oxidation used

for

_cleaning,

defects

can

be

produced

just

below

the gate.

This

effect

is

shown

in

figure 2-8.

In

a

very

long

_{channel, the two}

defect

bumps

are

insignificant.

As

the channel gets shorter, the threshold voltage

increases

and

they

become

significant.

Na

N,

NA

L

\*t _-| 1'' '''0H ^ p^1"""

Figure

2-8. PotentialprofilesinFETswith channeldopantredistributiondueto oxidation-enhanceddiffusion

Substrate Current Induced

Body

Effect

Hot

carriers generate electron-hole pairs.

In

nFET, the

holes

are swept

into

the

bulk

and appear as substrate current.

If

the

hole

generation

becomes

large,

the

hole

theeffect of asmall positive substrate

bias.

In

turn,

this effect

increases

the

drain

current

and

decreases

thethresholdvoltage.

2.2.

BSIM3

Level

1,

Level 2

and

Level 3

models are the

first

generation of

SPICE FET

models.

These

models emphasize

detailed

analytical

descriptions

of

device behavior.

The

models

have

a small number of_parameters, which eases parametere xtraction

but

places a great

burden

onthe simulator.

Thus,

BSIM3

focuses

more onthe robustness of

theequation andthe

efficiency

ofthe simulation.

BSIM3

is

themodel which will

be

used

in

developing

the

low

power

library

cell.

Each

cell will

be

characterized

using

the

BSIM3

model

file.

With

the goals of robustness and efficiency, the model takes on a great

deal

of

empirical _character, with a

large

number of model parameters

(figure 2-9).

These

parameters provide a

description

ofthe

underlying

process

technology

andthevariations

associated with that process.

The

issues

related to

shrinking geometry

are one such

variation.

These

parameters add more terms to the equations

defined

_earlier,

but

the

fundamental

principles ofthe equations are still the same.

More

explanation

relating

to

BISM3

can

be found

in

"MOSFET

Modeling

with

SPICE"

and

"BSIM3

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Figure2-9.

0>)

[image:37.506.54.415.41.530.2]

Chapter 3

Power

Dissipation in CMOS Circuit

3.1.

Types

of

Power Dissipation

Low

power usage will

be

the

differentiating

aspect of this

CMOS

cell

library

with respectto other

CMOS

cell

libraries.

Therefore,

it

is

vitalto

know how

the

CMOS

circuit

dissipates

power.

Power

dissipated

by

the

CMOS

circuit can

be

categorized

into

two types: static power

dissipation due

to

any

other current which

is

drawn

continuously

from

the power _supply, and

dynamic

power

dissipation

due

to the

charging

and

discharging

ofthecircuit's

load

whenthere

is

logic switching [1].

3.2.

Static

Power

Theoretically,

CMOS

circuits are

designed

withthe

idea

thattherewill

be

no path

from

VCC

to

VSS.

That

is,

when the circuit

is in

a stable

logic

level,

there will

be

no

power

dissipated.

Yet,

in

a real _circuit, power

is dissipated.

This

is known

as static

power

dissipation.

There

are reasons

why

there

is

still power

being

dissipated.

One

of

the reasons

is junction leakage

current caused

by

the

hot

carrier

[6].

For

_simplicity, an

inverter

will

be

used to understand the

junction

leakage

current.

It

is

represented

by

V

_in

^~T

vum

WJU

^

mm

n-well

n+

/

\

7

A

A

[image:39.506.55.451.56.266.2]

p-substrate

Figure 3-1. CMOSmodel

describing

parasiticdiodes [1].

With

the model

in

figure

3-1,

leakage

current

is

produced

only

by

theseparasitic

diodes

in

accordancewith equation

(3-1):

lo

=h\

e

qV/

\

kT _^

J

(3-1)

where:

i

, =

reservesaturation current.

V=_{diodevoltage.}

q=

electron charge

(l

.602x

10",9c).

k=_Boltzmann's

constant

(l

.38

xlO"23

f

T=

10000

30

40

50

60

70

80

90

100

110

TempfC)

Figure 3-2. Temperatureversusleakagecurrentfor different featuresizes [37].

Based

on equation

(3-1),

the

leakage

current worsens with an

increase

in

temperature.

This

is

shown

in figure

3-2.

Another

reason that power

is

still

being

dissipated

when there are no

switching

activities

in

the transistor

is

due

to the sub

threshold current.

When

the transistor

is in

cut-off_mode,

in

this case

NMOS, Vgs

=

0,

there

is

no current

flowing

from

the

drain

to the source ofthe

NMOS,

meaning

there

is

no

channel created

from

thesourceto the

drain.

If

Vgs

startsto

increase,

therewill

be

a point

where a channel

is

createdtoconnectthe source andthe

drain. At

that point, thevoltage

applied to

Vgs

is

called

Vt,

the threshold voltage.

Ideally,

therewill

be

no current

below

Vt,

but

as

Vgs

gradually

increases

closer to

Vt,

a small amount of carriers produce a

current called the sub-threshold current.

When

Vt decreases,

the sub-threshold current

increases

as shown

in figure

3-3,

because

theregion wherethetransistorwill

be

in

cut-off

<

Q

VGS

(V)

Figure 3-3. Relation betweensub-threshold current and

Vgs

with

differing

Vt

[37].

Currently,

static power

dissipation

is

becoming

growing

problem

because

ofthe

shrinking feature

size.

The

power

supply

must

be decreased

at smaller

feature

sizes,

resulting in lower Vt

as shown

in

figure

3-4.

3.3.

Dynamic

Power Dissipation

Most

ofthe power

dissipated in

a

CMOS

_{circuit comes}

from dynamic

_power

dissipation.

This charging

and

discharging

ofthe circuit's

load

causes this

dissipation.

Suppose

thecircuit

load

is

acapacitoras shown

in figure

3-5.

vcc

M1

r>

L = 0.18u

nO

CMOSP'

W

-1.08u

M2 _K"

Oout

CHOSNl

L = Q.18u W 0.36u

10f

Figure 3-5. Circuitmodelload

Therefore,

when the power

supply

changes

from 0

to

Vdd,

the

PMOS

will either switch

from closing

thepathto

Vdd

or

opening

the pathto

Vdd-

If

thepath to

Vdd

is

_{opened, the}

load

will

be

chargedto

Vdd-

On

the other

hand,

if

the pathto the

Vdd

is

_{closed, the}

load

will

be discharged

throughthe

NMOS.

Therefore,

the average power

dissipation,

Pd,

can

be found

by

assuming

thatthe

input

is

a square wave withthemaximum

voltage,

Vin,

and

I M t DD

^substitute fp=V

(3-2)

"rf

=

^V

DD JP

Furthermore,

by

analyzing

figure

3-5,

atthe

charging

time,

not all the

energy

will

be

stored

into

the capacitor since the charge still

has

to go through the

PMOS,

which

in

turn

dissipates

some ofthe

energy

as

heat

[4].

The energy

stored

in

the capacitor can

then

be

expressed as:

Es,oreAT)=

f

v{t)-dq=

[DDv{t)-Cdv

=

\l2CVDD2

(3-3)

The energy

supplied

by

thepower

supply

is:

Esap(T)

= CVDD2

(3-4)

Using

equations

(3-3)

and

(3-4),

energy dissipated

into

heat

can

be

expressed as the

following:

Em*

<T)

=

^sup

P)

-Estored (T)

= CVDD2

-

1/2

CVDD2 =

1/2

CVDD2

(3-5)

It

can

be

concluded that

50%

ofthe power

dissipated becomes heat.

In

certain

types ofcircuits, such as a pass

logic

circuit, the size ofthe

final

voltage

is

not equal to

In

addition, there

is

another type of power

dissipation

which can

be

categorized

into

either

dynamic

or static power

dissipation,

namely

short circuit power

dissipation.

Short

circuitpower

dissipation

happens

only

whenthecircuit

is

changing

theoutput

logic.

For

example,

if

the previous state

is logic

1

and the circuit changes to

logic

0,

or vice

versa.

For

simplicity, an

inverter

is

used and the transient output waveform when the

inverter

changes

from

logic 1

to

logic 0

is

shown

in figure

3-6.

The

region where the

waveform

is located between

Vdd-(-Vtp)

and

Vm

on the

Y-axis

is

the region where the

PMOS

is

going

to

be

shut off andthe

NMOS

will

be

turnedon.

Ideally,

whenthe

NMOS

is

on, the

PMOS

must

be

off,

but

this

is

notthe case.

When PMOS is starting

toturnoff,

the

NMOS

is

starting

to turn on,

creating

a

direct

path

from

Vdd

to ground

VTC

of

Inverter

1.8-> '< ro o 3 o

1.5-]A-z

\2-_

]-_

800m-600m 400m- 200m-/ouLv

i i i i

I i i i i

|

i i i i _| i i i i

|

i i i i

|

i i i

| ' '

200m 400m 600m 800m 1 1.2

DC

SWEEPof/In (Voltagev

)

Figure 3-6. Transientwaveformofinverter

1 I | I | i j p

If

thewaveform

input

to thecircuit

has

a

fast

rise time and

fall

time,

short circuit

power

dissipation is

small.

Short

circuit power

dissipation

only

grows when the

input

waveform's risetime and/or

fall

time

is

slow.

3.5.

Total Power Dissipated

In

_{short, total}power

dissipation

of a

CMOS

circuit can

be

obtained

by

summing

up

the threepower

dissipations

explained above.

Chapter

4

Low Power

Design

Methodology

4.1.

Types

of

Low Power

Having

a

low

power

design

methodology

which can

be

implemented

by

following

a

step-by-step

procedure will

be

very

useful.

However,

this

is

not

feasible because

the

methodology

must

be

applied

depending

on the target where the circuit

design

will

be

used.

Each device

in

which the circuit

is

used will

have different in low

power

requirements.

For

_example, a tablet pc

has different low

power requirements than a

desktop

computer.

A

tabletpc

is

expectedto

have

very low

voltage and

very low

average

power_consumption, unlike a

desktop

where

low

average power consumption

is

_expected,

but

v

ery 1

ows

tandby

power

d issipation i

s n ot r equired.

T

his

d ifference

i

s

d

uetot

he

availability

ofthe power source.

A

tabletpc

depends

on

battery

life,

whereas a

desktop

has

a

"limitless"

power source.

Therefore,

depending

onthe target application wherethe

circuit will

be

implemented,

low

powercan

be

divided into:

1

.

Low

peak current

The

circuit's performance

impacts

the time

necessary

for

discharging

the

battery. This

also affectsthecostofthe

battery.

The b attery

i

s a

lso

a

ffected

h ere,

b

utt

he

scope

i

s e

ssentially

o verall

p

ower

dissipation in

the whole circuit.

This

includes

the

buffer

drive

and

heat

generated

by

thecircuit.

3.

Low standby

current

Low standby

current relates to the condition

in

which the circuit

is

neither

in

operation nor

in

sleep

mode.

Inputs

are not _changing, so outputs remain the

same.

Ideally

there should

be

no power

dissipated in

thecase of

CMOS.

4.

Low

voltage

This

relatesto the number of

battery

cells andthecircuit's performance.

5.

Low

EMC

This

impacts

the circuit and

layout

technique to reduce

receiving

or

radiating

EMC (Electromagnetic

Compatibility)

[4].

Different

techniques exist to achieve

low

power

based

on the above criteria.

In

this

1

ibrary,

1

ow a verage c onsumption a nd

1

owv oltage a ret

he

two

i

ssuest

hat

w

ill b

e

dealt

with _extensively, so

they

are the

only

two

low

power criteria thatwill

be

explained

explicitly.

In

addition,

low

peak current

may

also

be

briefly

discussed.

The first

scenario

is

whenthe circuitoperates ata

low

voltage.

Based

on equation

(2-2),

namely:

Pd=CLVDD2fp

(4-1)

If

thecircuit

is

operating

atthe

lower

voltage,

theratio of power consumption

is:

P C V 2 f

1_low voltage

_

^Lr

VDD low J

P

C V 2 f

x

normal ^Lr

DD J , . _.

d (ir ^z

' lowvoltage P normal DDlow V

V VDD J

Suppose

_{the new,}

lower

voltage

is half

ofthe original

operating

voltage.

Based

ontheequation_{above, the}power savings

is

75%. The

power savings

is

_significant,

but

at

the expense of

increasing

gate

delay

since the

driver has

to charge the same

load.

Lowering

supply

voltage

does

increase

the

delay,

whereas

increasing

the

supply

voltage

means an

increase in

speed until the speed saturates.

There

are certainthings that can

be

done in

orderto overcomethe

delay

caused

by

low

voltage.

Some

oftechniquesusedto

reduce the

delay

are the same techniques which are used to reduce _power, and will

be

explained

below.

4.3.

Low Average Power Consumption

The

second scenario

is

when the circuit

dissipates

less

power when compared to

the typical circuit.

There may

be

times when the circuit

has

a

higher

peak _current,

but

during

the overall period of

time,

the circuit will consume

less

averagepower.

Suppose

battery.

It

will

be

expected that the

low-average-power

circuit will operate

for

a

longer

timecomparedtoatypicalcircuit.

This

can

be

achievedthroughseveraltechniques.

4.4.

Low Power Techniques

4.4.1.

Changing

the

Logic

Style

Logic

style

is

the most effective

way

to achieve either

lower

power or

higher

speed.

M. W. Allam

and

M. I. Elmasry's

paper, published

in

the

1998 Midwest

Symposium

on

Circuits

and

Systems

withthe title

"Low Power

CMOS

Logic

Fami