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This is a repository copy of

C-NNAP - A parallel processing architecture for binary neural

networks

.

White Rose Research Online URL for this paper:

http://eprints.whiterose.ac.uk/1870/

Book Section:

Kennedy, J.V., Austin, J. orcid.org/0000-0001-5762-8614, Pack, R. et al. (1 more author)

(1995) C-NNAP - A parallel processing architecture for binary neural networks. In:

Proceedings of the IEEE International Conference on Neural Networks (ICNN 95).

(University of Western Australia, Perth, Australia, Nov 27-Dec 01, 1995). IEEE , New York ,

pp. 1037-1041.

https://doi.org/10.1109/ICNN.1995.487564

[email protected]

https://eprints.whiterose.ac.uk/

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White Rose Consortium ePrints Repository

http://eprints.whiterose.ac.uk/

This is an author produced version of a paper published in Proceedings of the

IEEE International Conference on Neural Networks (ICNN 95).

White Rose Repository URL for this paper:

http://eprints.whiterose.ac.uk/1870/

Published paper

Kennedy, J.V., Austin, J., Pack, R. and Cass, B. (1995) C-NNAP - A parallel

processing architecture for binary neural networks. In: Proceedings of the IEEE

International Conference on Neural Networks (ICNN 95). (University of Western

Australia, Perth, Australia, Nov 27-Dec 01, 1995). IEEE, New York, pp.

1037-1041.

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References

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