(51) Int Cl.: H04L 29/02 ( ) H04L 12/801 ( )

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Note: Within nine months of the publication of the mention of the grant of the European patent in the European Patent Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the

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EUROPEAN PATENT SPECIFICATION

(45) Date of publication and mention of the grant of the patent:

03.12.2014 Bulletin 2014/49

(21) Application number: 11784039.7 (22) Date of filing: 16.05.2011

(51) Int Cl.:

H04L 29/02(2006.01) _{H04L 12/801}(2013.01)

(86) International application number:

PCT/US2011/036666

(87) International publication number:

WO 2011/146400 (24.11.2011 Gazette 2011/47)

(54) METHOD AND APPARATUS FOR IMPLEMENTING NON-BLOCKING PRIORITY BASED FLOW

CONTROL

VERFAHREN UND VORRICHTUNG ZUR IMPLEMENTIERUNG EINER FLUSSSTEUERUNG AUF BASIS VON ENTSPERRUNGSPRIORITÄTEN

PROCÉDÉ ET APPAREIL POUR IMPLÉMENTER UNE COMMANDE DE FLUX À BASE DE PRIORITÉ NON BLOQUANTE

(84) Designated Contracting States:

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30) Priority: 16.05.2010 US 201061345124 P

13.05.2011 US 201113107689

(43) Date of publication of application:

27.03.2013 Bulletin 2013/13

(73) Proprietor: Altera Corporation

San Jose, CA 95134 (US)

(72) Inventor: DUBEY, Ajay

San Jose CA 95134 (US)

(74) Representative: Appelt, Christian W.

Boehmert & Boehmert Anwaltspartnerschaft mbB Patentanwälte Rechtsanwälte Pettenkoferstrasse 20-22 80336 München (DE) (56) References cited: US-A1- 2002 093 910 US-A1- 2003 016 628 US-A1- 2004 081 090 US-A1- 2006 092 837 US-A1- 2009 122 702 US-B1- 6 618 378 US-B1- 6 721 797

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5 10 15 20 25 30 35 40 45 50 55 Description BACKGROUND

[0001] With the movement in Storage Area Networks

(SANs) to Fiber Channel over Ethernet (FCoE) and the acceptance of 10 Gigabit (Gb) Ethernet standard, a loss-less methodology must be utilized to support the FCoE. Priority-based flow control is intended to eliminate frame loss due to congestion resulting from head of line block-ing. Current methodologies. i.e., the 802.3x mechanism and extensions of this mechanism, for priority flow control (PFC) attempt to ensure zero loss under congestion in Data Center Bridging Networks and specify traffic class-es that may be paused. Thclass-ese methodologiclass-es tend to stop other types of data traffic when storage needs more bandwidth. In addition, a buffer overflow situation may occur due to the partially blocking nature of the current architecture where a traffic scheduler managing traffic from multiple priority queues as the traffic scheduler blocks the head of the line carrying all priorities.

[0002] It is in this context that embodiments arise. [0003] US 2004/081090 A1 relates to a congestion

controller, which suppress transmission traffic based on a traffic attribute in the event of congestion especially in a circumstance in which a plurality of Ethernet switches are connected. The congestion controller in the Ethernet switch comprises a plurality of transmission queues hav-ing different priority each other, a receivhav-ing unit for re-ceiving a PAUSE frame, and a restriction unit to restrict transmission traffic from the transmission queue by the received PAUSE frame, wherein the restriction unit re-stricts the transmission traffic from a transmission queue of lowest priority by a PAUSE frame received at a time other than a PAUSE time and suppresses transmission traffic from a transmission queue of highest priority by a PAUSE frame received during the PAUSE time.

SUMMARY

[0004] The invention is defined in the independent

claims. Advantageous embodiments are subject to the dependent claims.

[0005] Embodiments described herein provide circuits

and methods implementing priority based flow control for a communication standard such as 10 Gb Ethernet. It should be appreciated that the present embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a device or a method on a com-puter readable medium. Several inventive embodiments are described below.

[0006] In one embodiment, an integrated circuit having

the priority based flow control logic described herein is provided. The integrated circuit includes a link controller and a plurality of queue controllers in communication with the link controller. Each of the plurality of queue control-lers are operable to be coupled to a dedicated buffer of a remote transmitter of data external to the integrated

circuit. The plurality of queue controllers are operable to monitor a buffer full level for the dedicated buffer and each of the plurality of queue controllers are operable to transmit a signal indicating the buffer full level to the link controller. The link controller is operable to transmit a priority flow control signal to the remote transmitter, wherein a time period from transmission of the signal indicating the buffer full level to detection of the buffer full level is consistent for each dedicated buffer. In one embodiment, each of the plurality of queue controllers is operable to independently control a response to the sig-nal indicating the buffer full level.

[0007] In another embodiment, a method for providing

priority based flow control in a non-blocking manner is provided. The method includes monitoring a buffer level for a plurality of external buffers processing data. The monitoring is performed through dedicated queue con-trollers for each of the plurality of buffers, wherein the dedicated queue controllers are located off chip from the plurality of external buffers. The method also includes detecting a buffer full condition at a first buffer through a first queue controller and transmitting a first signal oper-able to cause the first buffer to discontinue the process-ing. The monitoring of the first buffer is paused for a time period specified by the first signal. Upon expiration of the time period, the monitoring of the buffer level for the first buffer is continued, wherein during the pausing of the monitoring of the first buffer a buffer full condition at a second buffer is detected through a second queue con-troller.

[0008] Other aspects will become apparent from the

following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of exam-ple the princiexam-ples of the embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments may best be understood by

reference to the following description taken in conjunction with the accompanying drawings.

Figure 1 is a simplified schematic diagram illustrating a high level overview of a system employing priority based flow control in accordance with one embodi-ment.

Figure 2 is a simplified schematic diagram illustrating further details on the circuitry for a priority based flow control in accordance with one embodiment. Figure 3 is a simplified schematic diagram illustrating an exemplary packet format utilized by the priority based flow control in accordance with one embodi-ment.

Figure 4 is a simplified schematic diagram illustrating the partitioned link control and queue control in ac-cordance with one embodiment.

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Figure 5 is a simplified schematic diagram illustrating state diagram for the exchange of status information between the link controller and the queue controllers in accordance with one embodiment.

Figure 6 is a waveform diagram illustrating the non-blocking flow control between queues in accordance with one embodiment.

Figure 7 is s simplified flowchart diagram for a finite state machine implementing the method for priority based flow control in accordance with one embodi-ment.

DETAILED DESCRIPTION

[0010] The following embodiments describe circuits

and methods for a priority based flow control mechanism. It should be appreciated that the present exemplary em-bodiments may be practiced without some or all of these specific details. In other instances, well-known opera-tions have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0011] Current implementations for priority based flow

control require a tradeoff between bandwidth and time for response, i.e., the time period to verify or re-check whether Xoff/Xon signals are to be transmitted. The cur-rent embodiments address this issue by decoupling the functions. The decoupling is achieved by a dedicated queue controller for each queue, and a link controller in communication with the dedicated queue controllers. This decoupled architecture handles a priority based flow control in Ethernet full duplex link and is scalable to sup-port multiple priority queues, where a dedicated queue controller is provided for each queue. The partitioning of the link control function and the queue control function is achieved in a pseudo independent fashion. The link controller and queue controllers publish their current sta-tus to each other and provide the earliest possible op-portunity to transmit either an Xoff or Xon frame for any queue. Each queue controller has access to the status of link controller to indicate when to transmit Xon/Xoff frames. The link controller accesses the status of every queue controller to send Xoff/Xon frames for correspond-ing priorities. In one embodiment, as many queue con-trollers as needed by the system may be provided. For example, if a user wants to have a priority flow control (PFC) controller support four queues, there will be four instances of the queue Finite State Machine (FSM) and one common Link FSM. Through the embodiments de-scribed in further detail below a priority based flow control technique is provided for an Ethernet transmission, such as a transmission over a 10Gb Ethernet system.

[0012] Figure 1 is a simplified schematic diagram

illus-trating a high level overview of a system employing pri-ority based flow control in accordance with one embod-iment. System 100 includes storage area network (SAN) 102, local area network (LAN) 104 and servers 106a

through 106c, each of which are connected through ap-pliance 108. In one embodiment, apap-pliance 108 is a switch which enables unified access to a unified fabric which may include LAN traffic, Internet Protocol (IP) based storage traffic, and fiber Channel-based storage traffic. In another embodiment the unified fabric is pro-vided through a 10 Gigabit (Gb) Ethernet system. It should be appreciated that the logic defined through the embodiments below may reside within appliance 108 or servers 106a through 106c in one exemplary implemen-tation.

illus-trating further details on the circuitry for a priority based flow control in accordance with one embodiment. In Fig-ure 2, client 122 is in communication with integrated cir-cuit 120, which in turn is in communication with storage area network 102. It should be appreciated that integrat-ed circuit 120 and client 122 may reside in the server or appliance illustrated in Figure 1, in one embodiment. In another embodiment, client 122 may be a local central processing unit. In yet another embodiment, integrated circuit 120 may be a programmable logic device, such as a field programmable gate array or application specific integrated circuit. Within integrated circuit 120 are priority flow control (PFC) logic 124a, media access control (MAC) logic 124b, and physical (PHY) layer 124c. As illustrated, within each of these modules is a correspond-ing transmit (Tx) and receive (Rx) component. Client 122 also includes a corresponding transmit and receive com-ponents, wherein each transmit and receive component includes a plurality of queues. Within the transmit com-ponent of client 122 are queues 126a through 126n, and within the receive component of the client are queues 128a through 128n. Priority flow control logic 124a of integrated circuit 120 provides dedicated queue control-lers for each of the queues within client 122. In addition, priority flow control logic 124a includes a link controller in communication with a plurality of the dedicated queue controllers as described in further detail below with re-gard to Figure 4.

illus-trating an exemplary packet format utilized by the priority based flow control in accordance with one embodiment. Packet 150 is configured to include a plurality of fields, such as header 152 and opcode 154. Enable vector 156 is a bit setting indicating whether the parameters set be-low are valid or invalid, e.g., ignore the pause time or consider the pause time. Parameters 158a-n provide a pause time for each corresponding queue, which is com-municated to a corresponding queue controller. In one embodiment, individual queue times for up to eight queues may be covered through packet 150. In another exemplary embodiment, a bit value of 1 in enable vector 156 indicates that a pause time for the corresponding parameter associated with the corresponding queue should be instituted. It should be appreciated that the amount of pause time may be indicated through a bit value. The bit value representing the pause time may be

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referred to as a quanta. A value of zero in enable vector 156 will essentially disable whatever value is indicated in the corresponding parameter 158. In another embod-iment, determination of whether an Xoff or Xon frame is transmitted to the external buffer is based on the corre-sponding bit values in parameters 158a-n. For example, if the bit value within parameter 158a is a zero, then an Xon frame is sent to the corresponding external buffer. If the bit value is any value besides zero, then an Xoff frame is transmitted to the corresponding external buffer located at the remote end of the network link. In addition, if the bit value is any value besides zero, the bit value represents the amount of pause time, or quanta where one quanta is equal to 512 bit times, prior to rechecking the buffer level. Further details on the packet configura-tion may be found in IEEE standard 802.1Qbb.

illus-trating the partitioned link control and queue control in accordance with one embodiment. Priority flow control logic 124a includes queue controller logic 180a through 180n. In communication with each instance of queue con-troller logic 180 is link concon-troller logic 182. It should be appreciated that in one embodiment there is a one to one correspondence between the number of queues, or in-gress buffers, in the client and the number of queue con-trollers 180 in the priority flow control logic, i.e., one queue controller is dedicated to one buffer. For example, if there are eight queues, then there would be eight queue con-trollers where each queue is associated with a dedicated queue controller. Queue controllers 180a-180n receive a pulse that indicates a corresponding queue or ingress buffer is full. In one embodiment, queue controllers 180a-n mo180a-nitor a sig180a-nal li180a-ne for a tra180a-nsitio180a-n. For example, whe180a-n the signal transitions from a logical low value to a logical high value, this may indicate that the buffer/queue has reached a full limit. It should be noted that the full limit may be a percentage of the full level for the queue in one embodiment. In turn, the corresponding queue controller 180a-n issues a signal, such as a queue status signal to link controller 182 that triggers the link controller to in-struct the remote sender to discontinue sending packets to the queue. In one exemplary embodiment, an Xoff sig-nal provides the instruction to discontinue sending pack-ets to the queue.

[0016] Still referring to Figure 4, link controller 182

transmits the Xoff signal to the corresponding remote sender and then communicates back to queue controllers 180a-n that link controller 182 is ready for any further action through the link status signal. If the signal moni-tored by the queue controller transitions from a high value to a low value, the corresponding queue is now available for additional data. Accordingly, the queue status signal will transition to indicate to link controller 182 that an Xon signal may be transmitted to the remote sender in order to continue sending packets. As noted above, the time period (quanta) for waiting before link controller 182 checks the status of the queue status signal is commu-nicated to the link controller through corresponding

queue controller 180. Thus, the time period (quanta) for each queue/buffer can be customized through the em-bodiments described herein so that a non blocking loss-less Ethernet connection that does not block any other queue Xoff request is achieved. Thus while link controller 182 is waiting for the time period (quanta) to check the status of a first queue, the link controller is able to check the status of the remaining queues and transmit applica-ble Xon and Xoff signals for each of the remaining queues as required. In addition, the embodiments eliminate the possibility of buffer overruns as discussed in more detail with reference to Figure 6.

illus-trating a state diagram for the exchange of status infor-mation between the link controller and the queue con-trollers in accordance with one embodiment. The state diagram for queue controller 180 indicates that the queue controller initially sits idle until a buffer full signal is re-ceived. As mentioned above, the buffer full signal may be triggered when the buffer level obtains a percentage of a completely full level. In response to the buffer full signal, an Xoff state occurs and indicates to the link con-troller that the ingress buffer is full. Upon completion of the transmission of the Xoff signal, link controller 182 communicates the completion of the transmission to queue controller 180 and a wait period occurs for the link controller prior to rechecking the status of the queue con-troller signal for the queue experiencing the buffer full condition. Once the buffer not full condition is detected an Xon state occurs and link controller 182 transmits an Xon frame. If the buffer congestion still continues, then the state transitions back to the XOFF state. With regard to the state diagram for link controller 182, the link con-troller is idle until an Xoff or Xon condition is detected through the link_xoff_xon_valid and link_pquanta values. The link_xoff_xon_valid signal indicates that the ingress buffers require either an Xoff or Xon frame to be sent by the link controller in one embodiment. The type of frame may be indicated through a non zero pause quanta value as discussed above. The link_pquanta signal indicates the pause quanta requested by the client in one embod-iment. Link controller 182 transmits the corresponding priority flow control frame (Xon or Xoff) to the correspond-ing remote issuer and returns to an idle state. The link_ready signal indicates that the link controller has sent the corresponding priority flow control frame (Xon or Xoff) and is going to scan the current status information from the queue controller or queue controllers.

[0018] Figure 6 is a waveform diagram illustrating the

non-blocking flow control between queues in accordance with one embodiment. As illustrated by waveform pairs 200/202 and 204/206, the dedicated queue controllers are able to service their dedicated queues with consistent timing and enable the Xoff frames to be transmitted by the link controller without any blocking. In addition, through the embodiments described herein the specified wait period may be customized for each buffer. The ingress_buffer_full signal of waveform 200 transition to

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a high level and triggers the Xoff[0] transmission depicted in waveform 202. During the wait/pause period after Xoff[0], ingress_buffer_full signal of waveform 204 tran-sitions to a high level. In response, transmission of Xoff[n] is triggered as depicted in waveform 206. Continuing with waveform 202, upon expiration of the first wait period, the level of ingress_buffer_full signal of waveform 200 is sampled and as the level remains at a logical high level, an Xoff transmission results followed by a second wait period. Upon expiration of the second wait period on waveform 202, waveform 200 has transitioned to a logical low value and Xon[0] is transmitted to indicate that buffer 0 can continue to receive data. In a similar manner, upon expiration of the first wait period in waveform 206, the level of ingress_buffer_full signal of waveform 204 is sampled and as the level remains at a logical high level, an Xoff transmission results followed by a second wait period as illustrated on waveform 206. Upon expiration of the second wait period on waveform 206, waveform 204 has transitioned to a logical low value and Xon[n] is transmitted to indicate that buffer n can continue to re-ceive data. It should be appreciated that the embodi-ments described herein eliminate the possibility of a buff-er ovbuff-errun as a time pbuff-eriod from transmission of the signal indicating the buffer full level to detection of the buffer full level is consistent for each dedicated buffer since the queue controllers independently control a response to the signal indicating the buffer full level. It should be fur-ther appreciated that under a single controller architec-ture it is possible to block new Xoff requests for a period of time defined by the wait period and during that wait period, one of the buffers may overflow resulting in a loss of data. The decoupling of the link and queue controller functionality ensures a non-blocking, e.g., lossless envi-ronment, which cannot be ensured through a single uni-fied controller architecture. While the exemplary embod-iments discuss the link controller as maintaining the pause, it should be appreciated that each queue control-ler may incorporate the functionality to manage or main-tain their respective pauses in an alternative embodi-ment.

[0019] Figure 7 is a simplified flowchart diagram for a

finite state machine implementing the method for priority based flow control in accordance with one embodiment. The ingress buffers are scanned for a full condition in operation 250. It should be appreciated that the corre-sponding queue controller for each ingress buffer may perform the scanning for a full condition in the corre-sponding buffer. In operation 252, Xoff/Xon signals are transmitted for buffers, with the buffer full flag/not full flag, respectively. As illustrated with reference to Figure 6, transition from between logical values on an ingress_buffer_full signal line may represent a transition from a buffer full condition (buffer full flag) to a buffer not full condition (buffer not full flag). In operation 254, the timers are turned on for the corresponding paused buff-ers when the buffer full flag is asserted, thereby pausing data being sent to the buffer. If the buffer not full flag is

asserted in operation 252, then operation 254 is by-passed and the method returns to operation 250 and re-peats as described above.

[0020] Embodiments described above may be

prac-ticed with various computer system configurations in-cluding hand-held devices, microprocessor systems, mi-croprocessor-based or programmable consumer elec-tronics, minicomputers, mainframe computers and the like. The embodiments can also be practiced in distrib-uted computing environments where tasks are per-formed by remote processing devices that are linked through a wire-based or wireless network.

[0021] The embodiments, thus far, were described

with respect to integrated circuits. The method and ap-paratus described herein may be incorporated into any suitable circuit. For example, the method and apparatus may be incorporated into numerous types of devices such as microprocessors or programmable logic devices. Exemplary programmable logic devices include pro-grammable array logic (PAL), propro-grammable logic arrays (PLAs), field programmable logic arrays (FPLAs), elec-trically programmable logic devices (EPLDs), elecelec-trically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FP-GAs), application specific standard products (ASSPs), application specific integrated circuits (ASICs), just to name a few.

[0022] The programmable logic device described

herein may be part of a data processing system that in-cludes one or more of the following components; a proc-essor; memory; I/O circuitry; and peripheral devices. The data processing system can be used in a wide variety of applications, such as computer networking, data net-working, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable logic device can be used to perform a variety of different logic functions. For example, the programmable logic device can be con-figured as a processor or controller that works in coop-eration with a system processor. The programmable logic device may also be used as an arbiter for arbitrating ac-cess to a shared resource in the data proac-cessing system. In yet another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable logic device may be one of the family of devices owned by the assignee.

[0023] Although the method operations were

de-scribed in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described opera-tions may be distributed in a system which allows the occurrence of the processing operations at various inter-vals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.

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[0024] Although the foregoing embodiments have

been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodi-ments are to be considered as illustrative and not restric-tive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

[0025] With the above embodiments in mind, it should

be understood that the invention can employ various computer-implemented operations involving data stored in computer systems. These operations are those requir-ing physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manip-ulated.

[0026] Any of the operations described herein that form

part of the invention are useful machine operations. The embodiments also relate to a device or an apparatus for performing these operations. The apparatus can be spe-cially constructed for the required purpose, or the appa-ratus can be a general-purpose computer selectively ac-tivated or configured by a computer program stored in the computer. In particular, various general-purpose ma-chines can be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.

[0027] The embodiments can also be embodied as

computer readable code on a computer readable medi-um. The computer readable medium is any data storage device that can store data, which can be thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network-coupled computer system so that the computer readable code is stored and executed in a dis-tributed fashion.

[0028] Although the foregoing embodiments have

been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodi-ments are to be considered as illustrative and not restric-tive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended exemplary claims.

Claims

1. An integrated circuit (120) comprising;

a link controller (182); and

a plurality of queue controllers (180a, ..., 180n) in communication with the link controller (182), each of the plurality of queue controllers (180a, ..., 180n) operable to be coupled to a corresponding ex-ternal dedicated buffer (126a, ..., 126n; 128a, ..., 128n), wherein each external dedicated buffer re-sides in a remote transmitter (122) that is external to the integrated circuit (120),

each of the plurality of queue controllers (180a, ..., 180n) operable to

monitor and detect a buffer full level for its corre-sponding external dedicated buffer (126a, ..., 126n; 128a, ..., 128n), and

transmit a signal indicating the buffer full level asso-ciated with its corresponding external dedicated buff-er to the link controllbuff-er (182), and

the link controller (182) operable to:

receive, from a first queue controller, a signal indicating the buffer full condition associated with an monitored external dedicated buffer monitored by said first queue controller, transmit a priority flow control signal to control the data flow to discontinue sending data to said monitored external dedicated buffer based on the received signal from the first queue control-ler,

indicate to the first queue controller that the pri-ority flow control signal was transmitted to said monitored external dedicated buffer,

receive, from the first queue controller, a pause time associated with said monitored external dedicated buffer, the pause time indicating a time period that the link controller waits before rechecking a buffer level of said monitored ex-ternal dedicated buffer.

2. The integrated circuit (120) according to claim 1,

wherein said time period from transmission of the signal indicating the buffer full level associated with its corresponding external dedicated buffer to the link controller (182), to detection of the buffer full level is consistent for each external dedicated buffer.

3. The integrated circuit (120) of claim 1, wherein the

priority flow control signal is a data packet including a pause time associated with the external dedicated buffer residing in the corresponding remote trans-mitter (122).

pause time is independently programmable for each external dedicated buffer.

integrated circuit is a programmable logic device.

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integrated circuit is incorporated into a switch oper-able to process storage data over a network.

7. A method for non-blocking priority flow control,

com-prising the steps of:

monitoring a plurality of buffer level signals in-dicating a buffer status for a plurality of buffers (126a,...,126n; 128a,...,128n) processing data, the monitoring performed through dedicated queue controllers (180a, ..., 180n), wherein each queue controller of the plurality of queue controllers (180a, ..., 180n) is coupled to a cor-responding buffer of the plurality of buffers (126a,...,126n; 128a,...,128n), wherein the plu-rality of buffers reside in a remote transmitter (122) of data that is external to an integrated circuit (120) in which the plurality of queue con-trollers (180a, ..., 180n) reside;

detecting a buffer full condition at a first buffer of the plurality of buffers processing data through a first queue controller (180a, ..., 180n); transmitting an output signal indicating the buff-er full condition of the first buffbuff-er of the plurality of buffers processing data to a link controller (182);

receiving, at the link controller (182), said output signal indicating the buffer full condition associ-ated with the first buffer,

transmitting a priority flow control signal to con-trol the data flow to discontinue sending data to the first queue controller based on the output signal,

indicating to the first queue controller that the priority flow control signal was transmitted to the first buffer,

pausing monitoring of an output signal of the first queue controller for a time period specified by the first signal; and

upon expiration of the time period, continuing the monitoring of the output signal of the first queue controller, wherein contemporaneously during the pausing of the monitoring of the out-put signal of the first queue controller, a second queue controller is monitored.

8. The method of claim 7, further comprising the steps

of:

transmitting a second signal to cause another, second buffer of the plurality of buffers process-ing data to discontinue the processprocess-ing in re-sponse to detecting a buffer full condition at the second buffer of the plurality of buffers process-ing data through a second queue controller of; and

pausing the monitoring of an output signal of the second queue controller for a time period

spec-ified by the second signal, wherein transmitting the second signal occurs prior to the time period specified by the first signal.

9. The method of claim 8, wherein the time period

spec-ified by the second signal is different than the time period specified by the first signal.

10. The method of claim 7, further comprising the steps

of:

transmitting a data packet having a bit setting that causes the first buffer to discontinue the processing, wherein the processing is one of transmitting or receiving data packets, and wherein the plurality of buffers processing data are located off chip from the dedicated queue controllers.

11. The method of claim 7, further comprising:

detecting a buffer below full condition upon ex-piration of the time period; and

transmitting a third signal to cause the first buffer to continue the processing.

12. The method of claim 11, wherein the third signal and

the first signal are data packets and wherein the third signal differs from the first signal solely by a single bit setting of a common field of the data packets.

Patentansprüche

1. Integrierte Schaltung (120), die folgendes umfasst:

einen Link-Controller (182) und

mehrere Queue-Controller (180a, ..., 180n) in Kommunikation mit dem Link-Controller (182), wobei jeder der mehreren Queue-Controller (180a, ..., 180n) betriebsfähig ist, an einen ent-sprechenden externen dedizierten Puffer (126a, ..., 126n; 128a, ..., 128n) gekoppelt zu werden, wobei sich jeder externe dedizierte Puf-fer in einem entPuf-fernten Sender (122) befindet, der sich außerhalb der integrierten Schaltung (120) befindet,

wobei jeder der mehreren Queue-Controller (180a, ..., 180n) betriebsfähig ist, einen Puffer-Voll-Pegel für seinen entsprechenden externen dedizierten Puffer (126a, ..., 126n; 128a, ..., 128n) zu überwachen und detektieren, und ein Signal, das den mit seinem entsprechenden externen dedizierten Puffer assoziierten Puffer-Voll-Pegel anzeigt, an den Link-Controller (182) zu übertragen, und

wobei der Link-Controller (182) betriebsfähig ist zum:

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Empfangen eines Signals von einem ersten Queue-Controller, das den Puffer-Voll-Zu-stand anzeigt, der mit einem überwachten externen dedizierten Puffer assoziiert ist, der von dem ersten Queue-Controller über-wacht wird,

Übertragen eines Prioritätsstrom-Steuersi-gnals zum Steuern des Datenstroms, um das Senden von Daten an den überwachten externen dedizierten Puffer auf der Basis des empfangenen Signals von dem ersten Queue-Controller abzubrechen.,

dem ersten Queue-Controller anzeigen, dass das Prioritätsstrom-Steuersignal an den überwachten externen dedizierten Puf-fer übertragen wurde,

Empfangen einer mit dem überwachten ex-ternen dedizierten Puffer assoziierten Pau-sezeit von dem ersten Queue-Controller, wobei die Pausezeit eine Zeitperiode an-zeigt, während der der Link-Controller war-tet, bevor er einen Pufferpegel des übwachten externen dedizierten Puffers er-neut prüft.

2. Integrierte Schaltung (120) nach Anspruch 1, wobei

die Zeitperiode von der Übertragung des Signals, das den mit seinem entsprechenden externen dedi-zierten Puffer assoziierten Puffer-Voll-Pegel an-zeigt, an den Link-Controller (182), bis zur Detektion des Puffer-Voll-Zustands für jeden externen dedi-zierten Puffer konsistent ist.

das Prioritätsstrom-Steuersignal ein Datenpaket ist, das eine Pausenzeit enthält, die mit dem externen dedizierten Puffer assoziiert ist, der in dem entspre-chenden entfernten Sender (122) befindet.

die Pausenzeit für jeden externen dedizierten Puffer unabhängig programmiert werden kann.

die integrierte Schaltung ein programmierbares Lo-gikbauelement ist.

die integrierte Schaltung in einen Schalter integriert ist, der betätigt werden kann, um Speicherdaten über ein Netzwerk zu verarbeiten.

7. Verfahren für eine entsperrende

Prioritätsflusssteu-erung, das die folgenden Schritte umfasst:

Überwachen mehrerer Pufferpegelsignale, die einen Pufferstatus anzeigen, für mehrere Puffer (126a, ..., 126n; 128a, ..., 128n), die Daten

ver-arbeiten, wobei das Überwachen durch dedi-zierte Queue-Controller (180a, ..., 180n) durch-geführt wird, wobei jeder Queue-Controller (180a, ..., 180n) der mehreren Queue-Control-ler (180a, ..., 180n) mit einem entsprechenden Puffer der mehreren Puffer (126a, ..., 126n; 128a, ..., 128n) gekoppelt ist, wobei sich die mehreren Puffer in einem entfernten Sender (122) von Daten befinden, der sich außerhalb einer integrierten Schaltung (120) befindet, in der sich die mehreren Queue-Controller (180a, ..., 180n) befinden;

Detektieren eines Puffer-Voll-Zustands eines ersten Puffers der mehreren Daten verarbeiten-den Puffer durch einen ersten Queue-Controller (180a, ..., 180n);

Übertragen eines Ausgangssignals, das den Puffer-Voll-Zustand des ersten Puffers der meh-reren Daten verarbeitenden Puffer anzeigt, an einen Link-Controller (182);

Empfangen des Ausgangssignals, das den mit dem ersten Puffer assoziierten Puffer-Voll-Zu-stand anzeigt, an dem Link-Controller (182), Übertragen eines Prioritätsstrom-Steuersignals zum Steuern des Datenstroms, um das Senden von Daten an den ersten Queue-Controller auf der Basis des Ausgangssignals abzubrechen, dem ersten Queue-Controller anzeigen, dass das Prioritätsstrom-Steuersignal an dem ersten Puffer übertragen wurde,

Pausieren des Überwachens eines Ausgangs-signals des ersten Queue-Controllers für eine durch das erste Signal spezifizierte Zeitperiode und

nach Ablauf der Zeitperiode, Fortsetzen des Überwachens des Ausgangssignals des ersten Queue-Controllers, wobei während des Pausie-rens des Überwachens des Ausgangssignals des ersten Queue-Controllers gleichzeitig ein zweiter Queue-Controller überwacht wird.

8. Verfahren nach Anspruch 7, das weiterhin die

fol-genden Schritte umfasst:

Übertragen eines zweiten Signals, um zu bewir-ken, dass ein anderer, zweiter Puffer der meh-reren Daten verarbeitenden Puffer das Verar-beiten als Reaktion auf das Detektieren eines Puffer-Voll-Zustands beim zweiten Puffer der mehreren Daten verarbeitenden Puffer durch ei-nen zweiten Queue-Controller einstellt; und Pausieren des Überwachens eines Ausgangs-signals des zweiten Queue-Controllers für eine durch das zweite Signal spezifizierte Zeitperio-de, wobei das Übertragen des zweiten Signals vor der durch das erste Signal spezifizierten Zeitperiode erfolgt.

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9. Verfahren nach Anspruch 8, wobei die durch das

zweite Signal spezifizierte Zeitperiode von der durch das erste Signal spezifizierten Zeitperiode verschie-den ist.

10. Verfahren nach Anspruch 7, das weiterhin die

fol-genden Schritte umfasst:

Übertragen eines Datenpakets mit einer Bitein-stellung, die bewirkt, dass der erste Puffer das Verarbeiten einstellt, wobei das Verarbeiten das Übertragen oder Empfangen von Datenpaketen ist und wobei sich die mehreren Daten verarbei-tenden Puffer außerhalb eines Chips von den dedizierten Queue-Controllern befinden.

11. Verfahren nach Anspruch 7, das weiterhin

Folgen-des umfasst:

Detektieren eines Puffer-unterhalb-desVoll-Zu-stands nach Ablauf der Zeitperiode; und Übertragen eines dritten Signals, um zu bewir-ken, dass der erste Puffer das Verarbeiten fort-setzt.

12. Verfahren nach Anspruch 11, wobei das dritte Signal

und das erste Signal Datenpakete sind und wobei sich das dritte Signal ausschließlich durch eine ein-zelne Biteinstellung eines gemeinsamen Felds der Datenpakete von dem ersten Signal unterscheidet.

Revendications

1. Circuit intégré (120), comprenant :

un contrôleur de liaison (182) ; et

une pluralité de contrôleurs de file d’attente (180a, ..., 180n) en communication avec le con-trôleur de liaison (182) ;

chaque contrôleur de la pluralité de contrôleurs de file d’attente (180a, ..., 180n) étant exploita-ble de manière à être couplé à une mémoire tampon dédiée externe correspondante (126a, ..., 126n ; 128a, ..., 128n), dans lequel chaque mémoire tampon dédiée externe réside dans un émetteur distant (122) qui est externe au circuit intégré (120) ; chaque contrôleur de la pluralité de contrôleurs de file d’attente (180a, ..., 180n) étant exploitable de manière à : surveiller et détecter un niveau de mémoire tampon pleine pour sa propre mémoire tam-pon dédiée externe correstam-pondante (126a, ...,126n ; 128a, ..., 128n) ; et transmettre un signal, indiquant le niveau de mémoire tampon pleine associé à sa mé-moire tampon dédiée externe

correspon-dante, au contrôleur de liaison (182) ; et le contrôleur de liaison (182) étant exploitable de manière à :

recevoir, à partir d’un premier contrôleur de file d’attente, un signal indiquant l’état de mémoire tampon pleine associé à une mé-moire tampon dédiée externe surveillée, la-quelle est surveillée par ledit premier con-trôleur de file d’attente ;

transmettre un signal de commande de flux prioritaire destiné à commander au flux de données d’interrompre l’envoi de données à ladite mémoire tampon dédiée externe surveillée, sur la base du signal reçu à partir du premier contrôleur de file d’attente ; indiquer au premier contrôleur de file d’at-tente que le signal de commande de flux prioritaire a été transmis à ladite mémoire tampon dédiée externe surveillée ; recevoir, à partir du premier contrôleur de file d’attente, une durée de pause associée à ladite mémoire tampon dédiée externe surveillée, la durée de pause indiquant une période de temps pendant laquelle le con-trôleur de liaison attend avant de revérifier un niveau de mémoire tampon de ladite mé-moire tampon dédiée externe surveillée.

2. Circuit intégré (120) selon la revendication 1, dans

lequel ladite période de temps, depuis la transmis-sion du signal, indiquant le niveau de mémoire tam-pon pleine associé à sa mémoire tamtam-pon dédiée ex-terne correspondante, au contrôleur de liaison (182), jusqu’à la détection du niveau de mémoire tampon pleine, est constante pour chaque mémoire tampon dédiée externe.

lequel le signal de commande de flux prioritaire est un paquet de données incluant une durée de pause associée à la mémoire tampon dédiée externe rési-dant dans l’émetteur distant corresponrési-dant (122).

lequel la durée de pause est programmable indé-pendamment pour chaque mémoire tampon dédiée externe.

lequel le circuit intégré est un dispositif logique pro-grammable.

lequel le circuit intégré est intégré dans un commu-tateur exploitable de manière à traiter des données de stockage sur un réseau.

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7. Procédé de commande de flux à base de priorité non

bloquante, comprenant les étapes ci-dessous con-sistant à :

surveiller une pluralité de signaux de niveau de mémoire tampon indiquant un état de mémoire tampon pour une pluralité de mémoires tam-pons (126a, ..., 126n ; 128a, ..., 128n) traitant des données, dans lequel la surveillance est mi-se en oeuvre par des contrôleurs de file d’attente dédiés (180a, ..., 180n), dans lequel chaque contrôleur de file d’attente de la pluralité de con-trôleurs de file d’attente (180a, ..., 180n) est cou-plé à une mémoire tampon correspondante de la pluralité de mémoires tampons (126a, ..., 126n ; 128a, ..., 128n), dans lequel la pluralité de mémoires tampons réside dans un émetteur distant (122) de données, lequel est externe à un circuit intégré (120) dans lequel réside la plu-ralité de contrôleurs de file d’attente (180a, ..., 180n) ;

détecter un état de mémoire tampon pleine au niveau d’une première mémoire tampon de la pluralité de mémoires tampons traitant des don-nées, par le biais d’un premier contrôleur de file d’attente (180a, ..., 180n) ;

transmettre un signal de sortie, indiquant l’état de mémoire tampon pleine de la première mé-moire tampon de la pluralité de mémé-moires tam-pons traitant des données, à un contrôleur de liaison (182) ;

recevoir, au niveau du contrôleur de liaison (182), ledit signal de sortie indiquant l’état de mémoire tampon pleine associé à la première mémoire tampon ;

transmettre un signal de commande de flux prio-ritaire destiné à commander au flux de données d’interrompre l’envoi de données au premier contrôleur de file d’attente, sur la base du signal de sortie ;

indiquer au premier contrôleur de file d’attente que le signal de commande de flux prioritaire a été transmis à la première mémoire tampon ; interrompre momentanément la surveillance d’un signal de sortie du premier contrôleur de file d’attente pendant une période de temps spé-cifiée par le premier signal ; et

à l’expiration de la période de temps, reprendre la surveillance du signal de sortie du premier contrôleur de file d’attente, dans lequel, simul-tanément, au cours de l’interruption momenta-née de la surveillance du signal de sortie du pre-mier contrôleur de file d’attente, un second con-trôleur de file d’attente est surveillé.

8. Procédé selon la revendication 7, comprenant en

outre les étapes ci-dessous consistant à :

transmettre un second signal destiné à amener une autre seconde mémoire tampon de la plu-ralité de mémoires tampons traitant des don-nées à interrompre le traitement en réponse à la détection d’un état de mémoire tampon pleine au niveau de la seconde mémoire tampon de la pluralité de mémoires tampons traitant des don-nées, par le biais d’un second contrôleur de file d’attente ; et

interrompre momentanément la surveillance d’un signal de sortie du second contrôleur de file d’attente pendant une période de temps spé-cifiée par le second signal, dans lequel la trans-mission du second signal se produit avant la pé-riode de temps spécifiée par le premier signal.

9. Procédé selon la revendication 8, dans lequel la

pé-riode de temps spécifiée par le second signal est différente de la période de temps spécifiée par le premier signal.

10. Procédé de la revendication 7, comprenant en outre

les étapes ci-dessous consistant à :

transmettre un paquet de données présentant un réglage de bit qui amène la première mémoi-re tampon à interrompmémoi-re le traitement, dans le-quel le traitement correspond à l’une parmi une transmission ou une réception de paquets de données, et dans lequel la pluralité de mémoires tampons traitant des données est située hors puce par rapport aux contrôleurs de file d’attente dédiés.

11. Procédé selon la revendication 7, consistant en outre

à :

détecter une mémoire tampon dont l’état est in-férieur à l’état plein suite à l’expiration de la pé-riode de temps ; et

transmettre un troisième signal destiné à ame-ner la première mémoire tampon à poursuivre le traitement.

12. Procédé selon la revendication 11, dans lequel le

troisième signal et le premier signal correspondent à des paquets de données, et dans lequel le troisiè-me signal ne diffère du premier signal qu’en ce qui concerne un réglage de bit unique d’un champ com-mun des paquets de données.

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REFERENCES CITED IN THE DESCRIPTION

This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description • US 2004081090 A1 [0003]