ITAUTEC A7520 - 6-71-W2400-D03 GP

(1)

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Notebook Computer

W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/

W249BUQ

Service Manual

(2)

B

B -- 1

1 B

B

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This appendix has circuit diagrams of the

This appendix has circuit diagrams of the W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/W249BUQ

W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/W249BUQ note-

note- book’s PCB’s. The following table indicate

book’s PCB’s. The following table indicates where to find the appropriate sche

s where to find the appropriate schematic diagram.

matic diagram.

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System Block Diagr

am - Page

B - 2

HUDSON PCIE/ PCI

/ CLOCK/ FCH

- Page

B - 16

USB/ FAN/ TP/ MULTI CON - Page

B - 30

ONTARIO MEM & PCIE I

/F, AP - Page

B - 3

HUDSON GPIO/ USB/

STRAP - Page

B - 17

5VS/ 3.3VS/ 1

.8VS/ 1.5VS

/ 1.1VS - Page

B - 31

ONTATIO DISPLAY/ CLK

/ MISC - Page

B - 4

HUDSON SATA/ DE

BUG IO/ SPI - Pa

ge

B - 18

POWER VDD3/ VDD

5 - Page

B - 32

ONTARIO POWER & DEC

OUPLING - Page

B - 5

HUDSON POWER DEC

OUPLING - Page

B - 19

Power 1.5V/ 0.7

5 - Page

B - 33

INAGUA DDR3 SO

-DIMMS A - Page

B - 6

POWERGOOD/ TPM - Pa

ge

B - 20

Power 1.1V/ 1VS

- Page

B - 34

INAGUA DDR3 S

O-DIMMS B - Page

B - 7

LVDS, INVERTE

R - Page

B - 21

Power 1.8VS - P

age

B - 35

Robson S3 PCI

E/ LVDS 1/6 -

Page

B - 8

HDMI/ CRT -

Page

B - 22

APU CORE/ NB

CORE - Page

B - 36

Robson S3 MA

IN 2/6 - Page

B - 9

CCD/ 3G - Pa

ge

B - 23

VGA POW

ER - Page

B - 37

Robson S3 ME

M Interface 3/6 - Page B - 10

Card Reader/ LAN JMC261C - Page

B - 24

CHARGER/ DC

IN - Page

B - 38

Robson S3 S

traps 4/6 - Page

B - 11

MINI PCIE/ SA

TA HDD/ ODD - Page

B - 25

Click Board - Pag

e

B - 39

Robson S3 Pow

er 5/6 - Page

B - 12

AUDIO CODEC A

LC261C - Page

B - 26

Audio Board/ US

B - Page

B - 40

Robson S3 Pow

er 6/6 - Page

B - 13

USB 3.0 VL80

0 - Page

B - 27

Power Switch &

LID Board - Page

B - 41

Robson DDR3 M

EM CH-A - Page

B - 14

KBC- ITE IT8518

- Page

B - 28

EXTERNAL ODD

Board - Page

B - 42

Robson DDR3 M

EM CH-B - Page

B - 15

LED/ MDC/ BT

- Page

B - 29

Table B - 1

Schematic

Diagrams

Version Note

The schematic

dia-grams in this chapter

grams in this chapter

are based upon

ver-sion

6-7P-W2405-sion

6-7P-W2405-003. If your

003. If your

main-board

(or

other

board

(or

other

boards) are a later

version,

please

version,

please

check with the

Serv-ice Center

ice Center for

for updat-

updat-ed

diagrams

(if

ed

diagrams

(if

required).

(3)

B

B -- 1

1 B

B

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A

Ap

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pen

end

diix

x B

B:

: Sc

Sch

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atiic

c Di

Diagr

agram

ams

s

This appendix has circuit diagrams of the

This appendix has circuit diagrams of the W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/W249BUQ

W241BU/W241BUQ/W240BU/W245BUQ/W248BUQ/W249BUQ note-

note- book’s PCB’s. The following table indicate

book’s PCB’s. The following table indicates where to find the appropriate sche

s where to find the appropriate schematic diagram.

matic diagram.

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System Block Diagr

am - Page

B - 2

HUDSON PCIE/ PCI

/ CLOCK/ FCH

- Page

B - 16

USB/ FAN/ TP/ MULTI CON - Page

B - 30

ONTARIO MEM & PCIE I

/F, AP - Page

B - 3

HUDSON GPIO/ USB/

STRAP - Page

B - 17

5VS/ 3.3VS/ 1

.8VS/ 1.5VS

/ 1.1VS - Page

B - 31

ONTATIO DISPLAY/ CLK

/ MISC - Page

B - 4

HUDSON SATA/ DE

BUG IO/ SPI - Pa

ge

B - 18

POWER VDD3/ VDD

5 - Page

B - 32

ONTARIO POWER & DEC

OUPLING - Page

B - 5

HUDSON POWER DEC

OUPLING - Page

B - 19

Power 1.5V/ 0.7

5 - Page

B - 33

INAGUA DDR3 SO

-DIMMS A - Page

B - 6

POWERGOOD/ TPM - Pa

ge

B - 20

Power 1.1V/ 1VS

- Page

B - 34

INAGUA DDR3 S

O-DIMMS B - Page

B - 7

LVDS, INVERTE

R - Page

B - 21

Power 1.8VS - P

age

B - 35

Robson S3 PCI

E/ LVDS 1/6 -

Page

B - 8

HDMI/ CRT -

Page

B - 22

APU CORE/ NB

CORE - Page

B - 36

Robson S3 MA

IN 2/6 - Page

B - 9

CCD/ 3G - Pa

ge

B - 23

VGA POW

ER - Page

B - 37

Robson S3 ME

M Interface 3/6 - Page B - 10

Card Reader/ LAN JMC261C - Page

B - 24

CHARGER/ DC

IN - Page

B - 38

Robson S3 S

traps 4/6 - Page

B - 11

MINI PCIE/ SA

TA HDD/ ODD - Page

B - 25

Click Board - Pag

e

B - 39

Robson S3 Pow

er 5/6 - Page

B - 12

AUDIO CODEC A

LC261C - Page

B - 26

Audio Board/ US

B - Page

B - 40

Robson S3 Pow

er 6/6 - Page

B - 13

USB 3.0 VL80

0 - Page

B - 27

Power Switch &

LID Board - Page

B - 41

Robson DDR3 M

EM CH-A - Page

B - 14

KBC- ITE IT8518

- Page

B - 28

EXTERNAL ODD

Board - Page

B - 42

Robson DDR3 M

EM CH-B - Page

B - 15

LED/ MDC/ BT

- Page

B - 29

Table B - 1

Schematic

Diagrams

Version Note

The schematic

dia-grams in this chapter

grams in this chapter

are based upon

ver-sion

6-7P-W2405-sion

6-7P-W2405-003. If your

003. If your

main-board

(or

other

board

(or

other

boards) are a later

version,

please

version,

please

check with the

Serv-ice Center

ice Center for

for updat-

updat-ed

diagrams

(if

ed

diagrams

(if

required).

(4)

B - 2

B - 2 Syst

System Block D

em Block Diagr

iagram

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System Block Diagram

Sheet 1 of 41

System Block

Diagram

512MB DDR3

(USB2)

TOUCH PAD

LPC

CARD

READER

GPU POWER, VDDC

SO-DIMM1

HP

OU

OUT

T

INT SPK R

CLICK BOARD

SOCKET

PCIE

480 Mbps

DDRIII

Mini

Mini PCI

PCIE

E

SPI

DDRIII

INT MIC

25

25 MHz

MHz

LCD CONNECTOR

AMD

FUSIO

N AP

U

CRT Connector

HDMI

HDMI Connecto

Connector

r

24 MHz

SHEET 6

MI

MIC

C

IN

SHEET 5

128pins LQFP

SO-DIMM2

32.768KHz

(USB6)

Bluetooth

1.1V, 1VS

EC SMBUS

USB PORT

AZAL

AZALIA L

IA LINK

INK

(U

S

B0

)

(U

SB

1)

USB PORT

SATA ODD

SATA HDD

BIOS

SPI

LAN

ITE 8518

INT. K/B

Azal

Azalia C

ia Codec

odec

EC

5V,3V,5VS,3.3VS

1.5V,0.75VS(VTT_MEM)

USB2.0

AT

I ROBSO

N

VDD3

VDD3,VDD

,VDD5

5 UMI*4

UMI*4

W

W83L77

83L771A

1AWG

WG

32.768 KHz

JMICRO

APU_

APU_CORE

CORE,NB_C

,NB_CORE

ORE

SATA I/II 3.0Gb/s

1066MHz

DDR3 / 1.5V

(Reserve)

TPM

CCD

(USB5)

REALTEK

ALC269

33 MHz

THERMAL

SENSOR

100 MHz

14141.6

14141.6mm

mm

(S3 TYPE)

SMART

FAN

SMART

BATTERY

AC- AC-IN

IN

PCIE*4

JMC261C

W240BU/

W240BU/W250BUQ

W250BUQ/W2

/W250BAQ Sys

50BAQ Sys tem B

tem B lock

lock Diagram

Diagram

SHEET 38

R

RJ

J-

-4 5

4 5

7 I

7 IN 1

N 1

SOCKET

INT SPKER

POWER SWITCH+HOTKEY X 3

6-71-E51QS-D02

CLICK BOARD

EXT. ODD

EXTERNAL ODD BOARD

6-71-W2402-D01

POWER SWITCH BOARD

USB+EARPHONE+EXT.MIC

AUD

AUDIO BO

IO BOARD

ARD

6-71-E51QN-D01

(Reserve)

6-71-W2408-D02

(USB4)

USB PORT

Ontario FT1

41 3-BALL

19 mm X19mm BGA

V G A D A C

D I S P L A Y P O R T X 2

4 X1 PCIE GEN2 GPP

1 X4 UM I-L INK GEN1

SINGLE CHANNEL DDR3

DX11 IGP

AMD

HUDS

ON

-M1

23mmX

23mmX23mmBGA

23mmBGA

HW M ONITOR

GB M AC

605-BALL

AZALIA HD AUDIO

SPII/F

I N T

I N T. C L K G E N

. C L K G E N

USB2.0(12) + 1.1 (2)

PCIE GEN1

PCIE GEN1 I/

I/F (4 x1)

F (4 x1)

LPC I/F

SAT AII(3 PORTS)

CHARGER,DC IN

U

US B

S B

3 .

3 .0

0 3 G

3 G

C

CA R

A RD

D

(USB9)

(Optional)

WLAN

1.8VS

1.5VS,1.1VS

MVDDQ,1.8V_REG,1.0V_REG

(USB3)

(5)

ON

ONTAR

TARIO

IO ME

MEM

M & PC

& PCIE

IE I/

I/F,

F, AP

AP B

B -- 3

3 B

B

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ONTARIO MEM & PCIE I/F, AP

Sheet 2 of 41

ONTARIO MEM &

PCIE I/F, AP

VG A_ RXP3 VG A_ RXP3 7 7 VG A_ RXP2 VG A_ RXP2 7 7 VG A_ RXN 2 VG A_ RXN 2 7 7 VG A_ RXN 3 VG A_ RXN 3 7 7 MEM _ DA T A6 3 MEM _ DA T A6 3 C1 0 C1 0 0 .1 u _ 10 .1 u _ 10 V _ X 0 V _ X 7 R_ 0 47 R_ 0 4 MEM _ DA T A4 MEM _ DA T A4 C1 1 C1 1 0 .1 u _ 10 .1 u _ 10 V _ X 0 V _ X 7 R_ 0 47 R_ 0 4 C1 2 C1 2 0 .1 u _ 10 .1 u _ 10 V _ X 0 V _ X 7 R_ 0 47 R_ 0 4 MEM _ DA T A3 5 MEM _ DA T A3 5 C1 3 C1 3 0 .1 u _ 10 .1 u _ 10 V _ X 0 V _ X 7 R_ 0 47 R_ 0 4 C _U MI_ P _ R X 0 C _U MI_ P _ R X 0 1 5 1 5 C1 4 C1 4 0 .1 u _ 10 .1 u _ 10 V _ X 0 V _ X 7 R_ 0 47 R_ 0 4 C _U MI_ N _ RX 0 C _U MI_ N _ RX 0 1 5 1 5 MEM _ DA T A5 MEM _ DA T A5 C _U MI_ P _ R X 1 C _U MI_ P _ R X 1 1 5 1 5 C _U MI_ N _ RX 1 C _U MI_ N _ RX 1 1 5 1 5 C _U MI_ N _ RX 2 C _U MI_ N _ RX 2 1 5 1 5 C _U MI_ P _ R X 2 C _U MI_ P _ R X 2 1 5 1 5 C1 5 C1 5 0 .1 u _ 10 .1 u _ 10 V _ X 0 V _ X 7 R_ 0 47 R_ 0 4 C _U MI_ P _ R X 3 C _U MI_ P _ R X 3 1 5 1 5 C _U MI_ N _ RX 3 C _U MI_ N _ RX 3 1 5 1 5 C1 C1 6 6 0 0 .1 .1 u u _ _ 10 10 V V _ _ X X 7 7 R_ R_ 0 0 44 MEM _ DA T A3 6 MEM _ DA T A3 6 C8 4 2 C8 4 2 1 0 u_ 6 .3 V _ X 5 R_ 0 6 1 0 u_ 6 .3 V _ X 5 R_ 0 6 C_ U MI_ P _ T X0 C_ U MI_ P _ T X0 1 51 5 C_ U MI_ N _ TX0 C_ U MI_ N _ TX0 1 51 5 C_ U MI_ N _ TX1 C_ U MI_ N _ TX1 1 51 5 C_ U MI_ P _ T X1 C_ U MI_ P _ T X1 1 51 5 C_ U MI_ N _ TX2 C_ U MI_ N _ TX2 1 51 5 C_ U MI_ P _ T X2 C_ U MI_ P _ T X2 1 51 5 C_ U MI_ N _ TX3 C_ U MI_ N _ TX3 1 51 5 C_ U MI_ P _ T X3 C_ U MI_ P _ T X3 1 51 5 MEM _ DA T A6 MEM _ DA T A6 R 1 R 1 1 . 1 . 2 7 2 7 K K _ _ 1 1 % % _ _ 0 0 44 MEM _ DA T A3 7 MEM _ DA T A3 7 MEM _ DA T A7 MEM _ DA T A7 MEM _ DQ S_ H0 MEM _ DQ S_ H0 5 ,6 5 ,6 M EM_ EV E NT # M EM_ EV E NT # 5 ,6 5 ,6 M E M_ A D DR [1 5 :0 ] M E M_ A D DR [1 5 :0 ] 5 ,6 5 ,6 MEM _ DA T A3 9 MEM _ DA T A3 9 M EM_ C LK _H 0 M EM_ C LK _H 0 5 5 MEM _ DA T A8 MEM _ DA T A8 MEM _ DA T A3 8 MEM _ DA T A3 8 MEM _ DA T A9 MEM _ DA T A9 M EM _B ANK 1 M EM _B ANK 1 5 ,6 5 ,6 M EM _B ANK 2 M EM _B ANK 2 5 ,6 5 ,6 MEM _ DA T A4 0 MEM _ DA T A4 0 MEM _ DA T A1 0 MEM _ DA T A1 0 ONT ARIO ( ONT ARIO (2.0)2.0) PA R PA RT1T1O F5O F5 M M E E M M O O R R Y Y I I / / F F U1 E U1 E O N TA R IO _A PU O N TA R IO _A PU V1 7 V1 7 M_WE_LM_WE_L V1 9 V1 9 M_CA S_LM_CA S_L U1 8 U1 8 M_RA S_L M_RA S_L V1 6 V1 6 M1_CS _L1M1_CS _L1 U1 7 U1 7 M1_CS _L0M1_CS _L0 W 1 6 W 1 6 M0_CS _L1M0_CS _L1 T 1 7 T 1 7 M0_CS _L0M0_CS _L0 W 1 5 W 1 5 M1_O DT1M1_O DT1 U1 9 U1 9 M1_O DT0M1_O DT0 V1 5 V1 5 M0_O DT1M0_O DT1 W 1 9 W 1 9 M0_O DT0M0_O DT0 E1 5 E1 5 M_CK E1M_CK E1 F 1 5 F 1 5 M_CK E0M_CK E0 N1 7 N1 7 M_EV ENT _LM_EV ENT _L L 2 3 L 2 3 M_RE SET _L M_RE SET _L L 1 7 L 1 7 M_C LK_L3M_C LK_L3 L 1 8 L 1 8 M_C LK_H 3 M_C LK_H 3 N1 9 N1 9 M_C LK_L2M_C LK_L2 N1 8 N1 8 M_C LK_H 2M_C LK_H 2 M1 8 M1 8 M_C LK_L1M_C LK_L1 M1 9 M1 9 M_C LK_H 1M_C LK_H 1 M1 6 M1 6 M_C LK_L0M_C LK_L0 M1 7 M1 7 M_C LK_H 0M_C LK_H 0 AC1 6 AC1 6 M_DQ S_L 7 M_DQ S_L 7 AB1 6 AB1 6 M_DQ S_H 7M_DQ S_H 7 AC2 1 AC2 1 M_DQ S_L 6M_DQ S_L 6 AC2 0 AC2 0 M_DQ S_H 6M_DQ S_H 6 V2 2 V2 2 M_DQ S_L 5M_DQ S_L 5 W 2 2 W 2 2 M_DQ S_H 5M_DQ S_H 5 P2 2 P2 2 M_DQ S_L 4M_DQ S_L 4 R2 2 R2 2 M_DQ S_H 4M_DQ S_H 4 J 2 3 J 2 3 M_DQ S_L 3M_DQ S_L 3 J 2 2 J 2 2 M_DQ S_H 3M_DQ S_H 3 E2 2 E2 2 M_DQ S_L 2M_DQ S_L 2 E2 3 E2 3 M_DQ S_H 2 M_DQ S_H 2 A2 0 A2 0 M_DQ S_L 1M_DQ S_L 1 B2 0 B2 0 M_DQ S_H 1M_DQ S_H 1 B1 6 B1 6 M_DQ S_L 0M_DQ S_L 0 A1 6 A1 6 M_DQ S_H 0M_DQ S_H 0 AA1 6 AA1 6 M_DM7M_DM7 AB2 0 AB2 0 M_DM6M_DM6 V2 3 V2 3 M_DM5 M_DM5 P2 3 P2 3 M_DM4M_DM4 H2 2 H2 2 M_DM3M_DM3 D2 1 D2 1 M_DM2M_DM2 B1 9 B1 9 M_DM1M_DM1 D1 5 D1 5 M_DM0M_DM0 F 1 6 F 1 6 M_BA NK2M_BA NK2 T 1 8 T 1 8 M_BA NK1M_BA NK1 R1 8 R1 8 M_BA NK0M_BA NK0 G1 5 G1 5 M_AD D15M_AD D15 E1 6 E1 6 M_AD D14M_AD D14 W 1 7 W 1 7 M_AD D13M_AD D13 E1 8 E1 8 M_AD D12M_AD D12 F 1 7 F 1 7 M_AD D11M_AD D11 T 1 9 T 1 9 M_AD D10 M_AD D10 E1 9 E1 9 M_AD D9M_AD D9 F 1 9 F 1 9 M_AD D8M_AD D8 G1 8 G1 8 M_AD D7M_AD D7 H1 5 H1 5 M_AD D6M_AD D6 G1 7 G1 7 M_AD D5M_AD D5 H1 7 H1 7 M_AD D4M_AD D4 H1 8 H1 8 M_AD D3M_AD D3 J 1 7 J 1 7 M_AD D2M_AD D2 H1 9 H1 9 M_AD D1M_AD D1 R R 1 1 7 7 M_AD D0 M_AD D0 M 2 2 M 2 2 M_Z VDD IO_ME M_S M_Z VDD IO_ME M_S M 2 3 M 2 3 M_V RE F M_V RE F A C1 5 A C1 5 M_D ATA 63 M_D ATA 63 A B1 5 A B1 5 M_D ATA 62 M_D ATA 62 A B1 8 A B1 8 M_D ATA 61 M_D ATA 61 A C1 8 A C1 8 M_D ATA 60 M_D ATA 60 A C1 4 A C1 4 M_D ATA 59 M_D ATA 59 A B1 4 A B1 4 M_D ATA 58 M_D ATA 58 Y 1 6 Y 1 6 M_D ATA 57 M_D ATA 57 A C1 7 A C1 7 M_D ATA 56 M_D ATA 56 Y 1 8 Y 1 8 M_D ATA 55 M_D ATA 55 A B1 9 A B1 9 M_D ATA 54 M_D ATA 54 A A2 0 A A2 0 M_D ATA 53 M_D ATA 53 A A2 3 A A2 3 M_D ATA 52 M_D ATA 52 A A1 8 A A1 8 M_D ATA 51 M_D ATA 51 A C1 9 A C1 9 M_D ATA 50 M_D ATA 50 A B2 2 A B2 2 M_D ATA 49 M_D ATA 49 Y 2 0 Y 2 0 M_D ATA 48 M_D ATA 48 Y 2 1 Y 2 1 M_D ATA 47 M_D ATA 47 W 23 W 23 M_D ATA 46 M_D ATA 46 U 2 3 U 2 3 M_D ATA 45 M_D ATA 45 T 2 1 T 2 1 M_D ATA 44 M_D ATA 44 Y 2 2 Y 2 2 M_D ATA 43 M_D ATA 43 Y 2 3 Y 2 3 M_D ATA 42 M_D ATA 42 V 21 V 21 M_D ATA 41 M_D ATA 41 V 20 V 20 M_D ATA 40 M_D ATA 40 T 2 2 T 2 2 M_D ATA 39 M_D ATA 39 R 2 3 R 2 3 M_D ATA 38 M_D ATA 38 P 20 P 20 M_D ATA 37 M_D ATA 37 M 2 0 M 2 0 M_D ATA 36 M_D ATA 36 T 2 3 T 2 3 M_D ATA 35 M_D ATA 35 T 2 0 T 2 0 M_D ATA 34 M_D ATA 34 P 21 P 21 M_D ATA 33 M_D ATA 33 N 2 3 N 2 3 M_D ATA 32 M_D ATA 32 K 23 K 23 M_D ATA 31 M_D ATA 31 K 20 K 20 M_D ATA 30 M_D ATA 30 H 2 0 H 2 0 M_D ATA 29 M_D ATA 29 G 2 3 G 2 3 M_D ATA 28 M_D ATA 28 K 21 K 21 M_D ATA 27 M_D ATA 27 K 22 K 22 M_D ATA 26 M_D ATA 26 H 2 3 H 2 3 M_D ATA 25 M_D ATA 25 H 2 1 H 2 1 M_D ATA 24 M_D ATA 24 F 21 F 21 M_D ATA 23 M_D ATA 23 F 20 F 20 M_D ATA 22 M_D ATA 22 D 2 2 D 2 2 M_D ATA 21 M_D ATA 21 C 2 2 C 2 2 M_D ATA 20 M_D ATA 20 F 22 F 22 M_D ATA 19 M_D ATA 19 F 23 F 23 M_D ATA 18 M_D ATA 18 D 2 3 D 2 3 M_D ATA 17 M_D ATA 17 C 2 3 C 2 3 M_D ATA 16 M_D ATA 16 C 2 0 C 2 0 M_D ATA 15 M_D ATA 15 A 21 A 21 M_D ATA 14 M_D ATA 14 B 18 B 18 M_D ATA 13 M_D ATA 13 A 18 A 18 M_D ATA 12 M_D ATA 12 D 2 0 D 2 0 M_D ATA 11 M_D ATA 11 B 21 B 21 M_D ATA 10 M_D ATA 10 A 19 A 19 M_D AT A9 M_D AT A9 C 1 8 C 1 8 M_D AT A8 M_D AT A8 D 1 6 D 1 6 M_D AT A7 M_D AT A7 C 1 6 C 1 6 M_D AT A6 M_D AT A6 C 1 4 C 1 4 M_D AT A5 M_D AT A5 A 14 A 14 M_D AT A4 M_D AT A4 D 1 8 D 1 8 M_D AT A3 M_D AT A3 A 17 A 17 M_D AT A2 M_D AT A2 A 15 A 15 M_D AT A1 M_D AT A1 B 14 B 14 M_D AT A0 M_D AT A0 M EM_ C LK _L 1 M EM_ C LK _L 1 5 5 M EM_ C LK _L 2 M EM_ C LK _L 2 6 6M EM_ C LK _H 2M EM_ C LK _H 2 6 6 M EM_ C LK _L 3 M EM_ C LK _L 3 6 6 M EM_ C LK _H 3 M EM_ C LK _H 3 6 6 MEM _ DA T A4 1 MEM _ DA T A4 1 MEM _ DA T A1 1 MEM _ DA T A1 1

be

be dire

directly tothe

ctly tothe planewitho

planewithout

ut along tra

along trace

ce

R6 connectionto VDDIO_SUSshould

Note

Note: O

: O penthesodlermaskfor Vias

penthesodlermaskfor Vias onMem

onMem interf

interface

ace

MEM _ DA T A1 2 MEM _ DA T A1 2 MEM _ DA T A4 2 MEM _ DA T A4 2 ME M _ CK E 1 ME M _ CK E 1 5, 6 5, 6 ME M _ CK E 0 ME M _ CK E 0 5, 6 5, 6 ON TAR IO(2.0) ON TAR IO(2.0) P ART 2O F 5 P ART 2O F 5 U U M M I I I I / / F F P P C C I I E E I I / / F F U1 A U1 A O NT AR IO_ AP U O NT AR IO_ AP U AB 7 AB 7P _UMI_RX N3P _UMI_RX N3 A C7 A C7P _UMI_RX P3P _UMI_RX P3 A C1 0 A C1 0P _UMI_RX N2P _UMI_RX N2 A B1 0 A B1 0 P _UMI_RX P2 P _UMI_RX P2 Y1 0 Y1 0P _UMI_RX N1P _UMI_RX N1 A A1 0 A A1 0P _UMI_RX P1P _UMI_RX P1 Y1 2 Y1 2P _UMI_RX N0P _UMI_RX N0 A A1 2 A A1 2P _UMI_RX P0P _UMI_RX P0 Y1 4 Y1 4P _ZV DD _10P _ZV DD _10 Y 3 Y 3P _GPP_ RXN 3P _GPP_ RXN 3 Y 4 Y 4P _GPP_ RXP 3P _GPP_ RXP 3 AA 2 AA 2P _GPP_ RXN 2P _GPP_ RXN 2 AA 1 AA 1P _GPP_ RXP 2P _GPP_ RXP 2 A C4 A C4P _GPP_ RXN 1P _GPP_ RXN 1 AB 4 AB 4 P _GPP_ RXP 1 P _GPP_ RXP 1 Y 6 Y 6P _GPP_ RXN 0P _GPP_ RXN 0 AA 6 AA 6P _GPP_ RXP 0P _GPP_ RXP 0 AC8 AC8 P _UMI_TX N3 P _UMI_TX N3 AB 8 AB 8 P _UMI_TX P3 P _UMI_TX P3 Y8 Y8 P _UMI_TX N2 P _UMI_TX N2 AA 8 AA 8 P _UMI_TX P2 P _UMI_TX P2 AB 1 1 AB 1 1 P _UMI_TX N1 P _UMI_TX N1 AC1 1 AC1 1 P _UMI_TX P1 P _UMI_TX P1 AC1 2 AC1 2 P _UMI_TX N0 P _UMI_TX N0 AB 1 2 AB 1 2 P _UMI_TX P0 P _UMI_TX P0 AA 1 4 AA 1 4 P_ ZVS S P_ ZVS S V4 V4 P_GPP _TX N3 P_GPP _TX N3 V3 V3 P_GPP _TX P3 P_GPP _TX P3 Y2 Y2 P_GPP _TX N2 P_GPP _TX N2 Y1 Y1 P_GPP _TX P2 P_GPP _TX P2 AC3 AC3 P_GPP _TX N1 P_GPP _TX N1 AB 3 AB 3 P_GPP _TX P1 P_GPP _TX P1 AC6 AC6 P_GPP _TX N0 P_GPP _TX N0 AB 6 AB 6 P_GPP _TX P0 P_GPP _TX P0 C 8 4 4 C 8 4 4 0 .1u _ 1 0 V_ X7R _ 04 0 .1u _ 1 0 V_ X7R _ 04 MEM _ DA T A1 3 MEM _ DA T A1 3 MEM _ DA T A4 3 MEM _ DA T A4 3 D IMM 0 _O DT 1 D IMM 0 _O DT 1 5 5D IMM 0 _O DT 0D IMM 0 _O DT 0 5 5 D IMM 1 _O DT 1 D IMM 1 _O DT 1 6 6D IMM 1 _O DT 0D IMM 1 _O DT 0 6 6 M EM_ C LK _L 0 M EM_ C LK _L 0 5 5 D IMM 0 _C S # 1 D IMM 0 _C S # 1 5 5D IMM 0 _C S # 0D IMM 0 _C S # 0 5 5 D IMM 1 _C S # 1 D IMM 1 _C S # 1 6 6D IMM 1 _C S # 0D IMM 1 _C S # 0 6 6 MEM _ DA T A1 4 MEM _ DA T A1 4 MEM _ DA T A4 4 MEM _ DA T A4 4

PLACE NEAR U1

Anal

Analog Th

og Therma

ermal Sen

l Sensor

sor

3 3 2 2 1 1 C3 6 4 C3 6 4 0 .1u _ 1 0 V_ X 5R _ 0 4 0 .1u _ 1 0 V_ X 5R _ 0 4 Q1 5 Q1 5 G 7 11 ST 9 U G 7 11 ST 9 U OU T OU T11 VC C VC C 22 G ND G ND 33 C 3 65 C 3 65 0 .1 u _ 10 V_ X5 R_ 0 4 0 .1 u _ 10 V_ X5 R_ 0 4 1:2 (4mils:8mils)

1:2 (4mils:8mils) T HE RM _ VOL T 2 7T HE RM _ VOL T 2 7 3. 3V 3. 3V R R 6 7 6 7 9 9 * * 0 0 _ 0 _ 0 44 MEM _ DA T A1 5 MEM _ DA T A1 5 MEM _ DA T A4 5 MEM _ DA T A4 5 1 .5 V 1 .5 V MEM _ DA T A1 6 MEM _ DA T A1 6 MEM _ DA T A4 6 MEM _ DA T A4 6 C5 C5 * 0. 1* 0. 1u _ u _ 1 0 1 0 V_ X7 V_ X7 R _ 0R _ 044 MEM _ DA T A1 7 MEM _ DA T A1 7 MEM _ DA T A4 7 MEM _ DA T A4 7 ON _ Z V SS ON _ Z V SS ON _Z V DD ON _Z V DD

ROUT

ROUTE A-LINKDIFF PAIR@ 85

E A-LINKDIFF PAIR@ 85 OHM +/-10%

OHM +/-10%

ME M _ RA S # ME M _ RA S # 5, 6 5, 6 ME M _ W E # ME M _ W E # 5, 6 5, 6ME M _ CA S #ME M _ CA S # 5, 6 5, 6 MEM _ DA T A1 8 MEM _ DA T A1 8 1 VS 1 VS R R 668 8 0 0 0 0 _ _ 0 0 44 MEM _ DA T A4 8 MEM _ DA T A4 8 MEM _ DA T A1 9 MEM _ DA T A1 9 MEM _ DA T A4 9 MEM _ DA T A4 9 MEM _ DA T A2 0 MEM _ DA T A2 0 MEM_A DD R0 MEM_A DD R0 M EM _A DD R1 0 M EM _A DD R1 0 M EM _A DD R1 2 M EM _A DD R1 2 M EM _A DD R1 1 M EM _A DD R1 1 M EM _A DD R1 3 M EM _A DD R1 3 M EM _A DD R1 4 M EM _A DD R1 4 M EM _A DD R2 M EM _A DD R2 M EM _A DD R3 M EM _A DD R3 M EM _A DD R5 M EM _A DD R5 M EM _A DD R1 5 M EM _A DD R1 5 M EM _A DD R4 M EM _A DD R4 M EM _A DD R1 M EM _A DD R1 M EM _A DD R8 M EM _A DD R8 M EM _A DD R7 M EM _A DD R7 M EM _A DD R9 M EM _A DD R9 M EM _A DD R6 M EM _A DD R6 MEM _ DA T A5 0 MEM _ DA T A5 0 M EM_ R ESE T # M EM_ R ESE T # 5 ,6 5 ,6 M EM _D M1 M EM _D M1 M EM _D M3 M EM _D M3 M EM _D M0 M EM _D M0 M EM _D M2 M EM _D M2 C 84 3 C 84 3 1 0 0 0 p_ 5 0 V 1 0 0 0 p_ 5 0 V_ X 7R _ 0 4_ X 7R _ 0 4 M EM _D M7 M EM _D M7 M EM _D M5 M EM _D M5 M EM _D M6 M EM _D M6 M EM _D M4 M EM _D M4 R R 2 2 2 2 K K _ _ 11% % _ _ 0 0 44 MEM _ DA T A2 1 MEM _ DA T A2 1 M E M _Z VDD IO M E M _Z VDD IO MEM _ DA T A5 1 MEM _ DA T A5 1 R 67 8 R 67 8 1 K_ 1 % _0 4 1 K_ 1 % _0 4 MEM _ DQ S_ H1 MEM _ DQ S_ H1 5 ,6 5 ,6 MEM _ DQ S_ L 0 MEM _ DQ S_ L 0 5 ,6 5 ,6 MEM _ DQ S_ L 2 MEM _ DQ S_ L 2 5 ,6 5 ,6 MEM _ DQ S_ H2 MEM _ DQ S_ H2 5 ,6 5 ,6 MEM _ DQ S_ L 1 MEM _ DQ S_ L 1 5 ,6 5 ,6 MEM _ DQ S_ H4 MEM _ DQ S_ H4 5 ,6 5 ,6 MEM _ DQ S_ L 3 MEM _ DQ S_ L 3 5 ,6 5 ,6 MEM _ DQ S_ H3 MEM _ DQ S_ H3 5 ,6 5 ,6 MEM _ DQ S_ H5 MEM _ DQ S_ H5 5 ,6 5 ,6 MEM _ DQ S_ L 4 MEM _ DQ S_ L 4 5 ,6 5 ,6 MEM _ DQ S_ L 6 MEM _ DQ S_ L 6 5 ,6 5 ,6 MEM _ DQ S_ H6 MEM _ DQ S_ H6 5 ,6 5 ,6MEM _ DQ S_ L 5MEM _ DQ S_ L 5 5 ,6 5 ,6 MEM _ DQ S_ L 7 MEM _ DQ S_ L 7 5 ,6 5 ,6 MEM _ DQ S_ H7 MEM _ DQ S_ H7 5 ,6 5 ,6 MEM _ DA T A2 2 MEM _ DA T A2 2 M E M_ D M[7 :0 ] M E M_ D M[7 :0 ] 5 ,6 5 ,6 M EM _B ANK 0 M EM _B ANK 0 5 ,6 5 ,6

For

For W250B

W250BAQ

AQ

M E M _D A T A[6 3 :0 ] 5 ,6 M E M _D A T A[6 3 :0 ] 5 ,6 MEM _ DA T A5 2 MEM _ DA T A5 2 MEM _ DA T A2 3 MEM _ DA T A2 3

ONTARIO MEM & PCIE I/F,

ONTARIO MEM & PCIE I/F, AP

AP

MEM _ DA T A5 3 MEM _ DA T A5 3 VGA _ R XN0 VGA _ R XN0 7 7 VGA _ R XP1 VGA _ R XP1 7 7 VGA _ R XN1 VGA _ R XN1 7 7 C6 C6 * 0. 1* 0. 1u _ u _ 1 0 1 0 V_ X7 V_ X7 R _ 0R _ 044 VGA _ R XP0 VGA _ R XP0 7 7 MEM _ DA T A2 4 MEM _ DA T A2 4 MEM _ DA T A5 5 MEM _ DA T A5 5 MEM _ DA T A2 5 MEM _ DA T A2 5 MEM _ DA T A5 4 MEM _ DA T A5 4 MEM _ DA T A2 6 MEM _ DA T A2 6 R 6 R 6 3 3 9 . 9 . 2 _ 2 _ 1 1 % % _ _ 0 0 44 M EM_ C LK _H 1 M EM_ C LK _H 1 5 5 R 68 1 R 68 1 1 K_ 1 % _0 4 1 K_ 1 % _0 4 MEM _ DA T A5 6 MEM _ DA T A5 6 MEM _ DA T A2 7 MEM _ DA T A2 7 C1 C1 * 0. 1* 0. 1u _ u _ 1 0 1 0 V_ X7 V_ X7 R _ 0R _ 044 C2 C2 * 0. 1* 0. 1u _ u _ 1 0 1 0 V_ X7 V_ X7 R _ 0R _ 044 C3 C3 * 0. 1* 0. 1u _ u _ 1 0 1 0 V_ X7 V_ X7 R _ 0R _ 044 MEM _ DA T A2 8 MEM _ DA T A2 8 C4 C4 * 0. 1* 0. 1u _ u _ 1 0 1 0 V_ X7 V_ X7 R _ 0R _ 044 MEM _ DA T A0 MEM _ DA T A0 MEM _ DA T A5 7 MEM _ DA T A5 7 V G A_ TXN 0 7 V G A_ TXN 0 7 V G A_ TXP V G A_ TXP 0 0 77 VT T _M EM VT T _M EM V G A_ TXN 1 7 V G A_ TXN 1 7 V G A_ TXP V G A_ TXP 1 1 77 MEM _ DA T A2 9 MEM _ DA T A2 9 MEM _ DA T A5 8 MEM _ DA T A5 8 C7 C7 * 0. 1* 0. 1u _ u _ 1 0 1 0 V_ X7 V_ X7 R _ 0R _ 044 MEM _ DA T A3 0 MEM _ DA T A3 0 MEM _ DA T A5 9 MEM _ DA T A5 9 MEM _ DA T A3 1 MEM _ DA T A3 1 MEM _ DA T A6 0 MEM _ DA T A6 0 MEM _ DA T A1 MEM _ DA T A1 MEM _ DA T A3 2 MEM _ DA T A3 2 V G A_ T X V G A_ T X P3 P3 77 V G A_ T X V G A_ T X N2 N2 77 V G A_ T X V G A_ T X N3 N3 77 V G A_ T X V G A_ T X P2 P2 77 MEM _ DA T A6 1 MEM _ DA T A6 1 C8 C8 * 0. 1* 0. 1u _ u _ 1 0 1 0 V_ X7 V_ X7 R _ 0R _ 044 MEM _ DA T A2 MEM _ DA T A2 MEM _ DA T A3 3 MEM _ DA T A3 3 MEM _ DA T A6 2 MEM _ DA T A6 2 MEM _ DA T A3 MEM _ DA T A3 1 .5 V 1 .5 V C9 C9 0 .1 u 0 .1 u _ 10 _ 10 V _ X V _ X 7 R_ 0 7 R_ 0 44 MEM _ DA T A3 4 MEM _ DA T A3 4