SPACE DDR4 SDRAM MEMORY

PRODUCT OVERVIEW

3D PLUS offers a family of space qualified DDR4 Synchronous Dynamic RAM (SDRAM) memory modules, with densities up to 48 Gbit; data bus widths of 16bits, 48 bits and 72 bits; and operating at frequencies up to 1.2 GHz.

3D PLUS’s DDR4 products are a perfect fit for systems requiring best in class, high performance memories; offering high speed bandwidth solutions that are qualified and characterized for use in the extreme environments present in most space applications.

Those memories are typically well suited to gain all benefits from space grade microprocessors, DSPs and/or FPGAs.

3D PLUS’s DDR4 memory modules are part of a DDR4 ecosystem, providing fully space qualified memory subsystem solution.

KEY BENEFITS

3D PLUS’s DDR4 Ecosystem includes:

 A wide range of DDR4 memories to handle high speed computing data requirements

 A DDR4 Termination Regulator to efficiently provide stable VTT to DDR4 components

 DDR4 RIMC (Radiation Intelligent Memory Controller) IP that allows enhanced protection and mitigation against SEU/SEFI.

KEY FEATURES PERFORMANCES

 Organization: 256M x (64 bits + 8 bits ECC)

 Including decoupling and termination

 Max Clock rate available: 1200MHz

 Max Transfer Rate 2400MT/s

 VDD/VDDQ = 1.2V, VPP = 2.5V

 JEDEC JESD-79-4 compliant

 Command Address Parity Check

 Data bus Write CRC (Cyclic Redundancy Check)

 Programmable #CAS latency (CL): from 9 to 16

 Burst length (BL): 8 (BL8), Burst Chop 4(BC4) or 8 on the fly

 Bi-directional Differential Data Strobe (DQS)

 Programmable on-die termination (ODT)

 Data bus inversion (DBI)

 ZQ calibration for DQ drive and ODT

 Available temperature range: 0°C to +70°C, - 40°C to +85°C , -40°C to +105°C

 Qualified for Space Applications.

SPACE QUALIFICATION

 Qualified with 3D PLUS ESA certification per ESCC 2566001

 Up to NASA Level 1

 Long Term Availability and High Reliability

 Radiation Hardened Designed for High End Space computing applications

 Flight heritage : 3D PLUS expertise in space memories for more than 20 years *

*From SRAM, SDRAM to DDR1/2/3/4

RADIATION TOLERANCE

 TID >100 krad

 SEL immune up to LET > 62.8 MeV.cm2/mg

 SEU protection/ mitigation thanks to RIMC

DDR4.

TABLE OF CONTENT

PRODUCT OVERVIEW... 1

KEY BENEFITS... 1

KEY FEATURES ... 1

PERFORMANCE ... 1

SPACE QUALIFICATION ... 1

RADIATION TOLERANCE ... 1

1. DOCUMENTS ... 8

1.1 APPLICABLE DOCUMENTS... 8

1.2 REFERENCE DOCUMENTS ... 8

1.3 ACRONYMS ... 8

2. GENERAL DESCRIPTION ... 9

1.1 INTRODUCTION ... 9

2.1 TYPE VARIANTS ... 10

2.2 RADIATION PERFORMANCES... 10

3. FUNCTIONAL DESCRIPTION... 11

3.1 COMMERCIAL, INDUSTRIAL AND SPECIFIC TEMPERATURE ... 11

3.2 SIMPLIFIED STATE DIAGRAM ... 12

4. PINOUT ... 14

4.1 BALL ASSIGNMENTS... 14

4.2 INPUT/OUTPUT DESCRIPTION... 15

5. ABSOLUTE MAXIMUM RATINGS ... 17

6. ELECTRICAL CHARACTERISTICS ... 18

6.1 RECOMMENDED DC OPERATING CONDITIONS... 18

6.2 INPUT AC AND DC OPERATING CONDITIONS ... 18

6.2.1 VREF... 18

6.2.2 Single ended inputs measurements levels ... 20

6.3 AC AND DC LEVELS FOR DIFFERENTIAL SIGNALS ... 21

6.3.1 Differential signal definition ... 21

6.3.2 Differential input swing requirements for CK-CK_n ... 21

6.3.3 Single-ended requirements for CK differential signals... 22

6.3.4 Slew rate definition for CK differential input signal ... 23

6.3.5 CK differential input cross point voltage... 23

6.3.6 Slew rate definitions for DQS differential input signals ... 24

6.3.7 DQS differential input cross point voltage... 24

6.4 OVERSHOOT AND UNDERSHOOT SPECIFICATIONS ... 26

6.4.1 Address, commands and controls... 26

6.4.2 Clock ... 26

6.4.3 Data, strobe and mask ... 27

6.5 MODULE CAPACITANCE... 28

6.6 CURRENT SPECIFICATION LIMITS ... 29

6.7 OUTPUT AC AND DC OPERATING CONDITIONS ... 29

6.8 SPEED BINS ... 30

6.9 AC TIMING PARAMETERS ... 32

7. RESET, POWER-UP AND INITIALIZATION... 40

7.1 POWER-UP INITIALIZATION SEQUENCE ... 40

7.2 RESET INITIALIZATION WITH STABLE POWER... 42

8. MODE REGISTER DEFINITION... 43

8.1 MODE REGISTER MR0 ... 44

8.2 MODE REGISTER MR1 ... 45

8.3 MODE REGISTER MR2 ... 46

8.4 MODE REGISTER MR3 ... 47

8.5 MODE REGISTER MR4 ... 48

8.6 MODE REGISTER MR5 ... 49

8.7 MODE REGISTER MR6 ... 50

8.8 MODE REGISTER MR7 ... 51

8.9 MULTI PURPOSE MODE REGISTER (MPR)... 52

9. TRUTH TABLES ... 53

9.1 COMMAND TRUTH TABLE ... 53

9.2 CKE TRUTH TABLE ... 55

10. COMMANDS ... 56

10.1 NOP ... 56

10.2 DESELECT ... 56

10.3 ACTIVATE ... 56

10.4 PRECHARGE ... 57

10.5 REFRESH... 57

10.5.1 Input clock frequency change ... 59

10.6 COMMAND ADDRESS LATENCY... 60

10.7 MAXIMUM POWER SAVING MODE (MPSM) ... 61

10.8 COMMAND/ ADDRESS PARITY (CAP) ... 61

10.9 PER-DRAM ADDRESSABILITY (PDA) ... 61

10.10 DLL OPERATIONS... 62

10.10.1 DLL on/off mode... 62

10.10.2 DLL-on to DLL-off procedure ... 62

10.10.3 DLL-off to DLL-on Procedure ... 64

11. WRITE LEVELING ... 66

11.1 DRAM SETTING FOR WRITE LEVELING AND DRAM TERMINATION ASSOCIATED ... 67

11.2 PROCEDURE DESCRIPTION ... 67

11.3 WRITE LEVELING MODE EXIT... 69

12. ODT ... 70

12.1 ODT MODE REGISTER AND ODT STABLE TABLE ... 70

12.2 ODT READ DISABLE STATE TABLE ... 71

12.3 SYNCHRONOUS ODT MODE ... 71

12.3.1 ODT latency and posted ODT... 71

12.3.2 Timing parameters ... 72

12.3.3 ODT during reads... 73

12.4 DYNAMIC ODT... 74

12.5 ASYNCHRONOUS ODT MODE... 75

13. DATA MASK ... 77

14. ORDERING INFORMATION... 78

14.1 PACKAGING... 79

14.1 HANDLING AND ASSEMBLY RECOMMENDATIONS... 79

14.1.1 Packing... 79

14.1.2 Handling ... 80

14.1.3 Storage... 80

14.1.4 Board Assembly ... 80

14.1.5 Electrostatic Discharge Sensitivity ... 80

15. REVISION HISTORY ... 81

16. 3D PLUS SALES OFFICES... 81

TABLES

Table 1: Component Type Variants... 10

Table 2: Generic Radiation Data DDR4 module without RIMC DDR4 ... 10

Table 3: Generic Radiation Data DDR4 module with RIMC DDR4 ... 10

Table 4: Temperature Range ... 11

Table 5: Ball Description... 16

Table 6: Absolute Maximum Ratings... 17

Table 7: DC Operating Conditions... 18

Table 8: Input Operating Conditions... 18

Table 9: Output Operating Conditions ... 19

Table 10 : RESET_n, TEN and ALERT_n inputs levels... 20

Table 11 : Command/address input levels ... 20

Table 12 : CT type-A input levels ... 21

Table 13 : CT type-B input levels ... 21

Table 14 : Differential swing requirements for CK, CK_n... 22

Table 15 : Single ended requirement for CK, CK_n ... 22

Table 16 : Cross point voltage for CK differential input signals... 24

Table 17 : Differential input slew rate and input levels for DQS-DQS_n ... 24

Table 18 : Cross point voltage for differential input signals DQS ... 25

Table 19: ADDR, CMD, CNTL overshoot and undershoot specifications ... 26

Table 20: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications ... 26

Table 21: Data, strobe, and mask overshoot and undershoot specifications... 27

Table 22: Pin capacitances ... 28

Table 23: I

DD

limits ... 29

Table 24: Output Operating Conditions ... 30

Table 25: Speed bins... 31

Table 26: Timing parameters ( à refaire pg 260-264)... 37

Table 27 : Default MR settings for power-up and reset initialization ... 40

Table 28: V

DD

slew rate... 42

Table 29 : Address table... 44

Table 30: Address pin mapping ... 44

Table 31: MR0 register definition... 45

Table 32: MR1 address pin mapping... 45

Table 33 : MR1 register definition... 46

Table 34: MR2 address pin mapping... 46

Table 35 : MR2 register definition... 47

Table 36: MR3 address pin mapping... 47

Table 37 : MR3 register definition... 48

Table 38: MR4 address pin mapping... 48

Table 39 : MR4 register definition... 49

Table 40: MR5 address pin mapping... 49

Table 41 : MR5 register definition... 50

Table 42: MR6 address pin mapping... 50

Table 43 : MR6 register definition... 51

Table 44 : V

REFDQ

ranges and levels ... 51

Table 45: Command truth table ... 54

Table 46: CKE Truth Table ... 55

Table 47: MR settings for leveling procedures ... 67

Table 48: DRAM termination function in leveling mode ... 67

Table 49: Termination state table ... 71

Table 50: Read Termination Disable Window ... 71

Table 51: ODT latency per component... 72

Table 52: DM vs. DBI function matrix ... 77

Table 53: Data Mask, DQ Frame Format ... 77

Table 54: Revision history ... 81

FIGURES

Figure 1:Functional Block Diagram ... 9

Figure 2: Simplified State Diagram ... 12

Figure 3:Ball Assignements ... 14

Figure 4: V

REFDQ

Voltage Range ... 19

Figure 5 : Differential signal defintion ... 21

Figure 6 : Single-ended requirement for CK... 22

Figure 7 : Differential input slew rate definition for CK, CK_n ... 23

Figure 8 : V

IX(CK)

definition... 23

Figure 9 : Differential input slew rate and input level definition for DQS – DQS_n ... 24

Figure 10 : V

IX(DQS)

definition ... 25

Figure 11: Address, command, control overshoot and undershoot definition ... 26

Figure 12: CKL overshoot and undershoot definition ... 27

Figure 13: Data, strobe, and mask overshoot and undershoot definition... 27

Figure 14: RESET and initialization sequence at power-on ramping ... 41

Figure 15: Reset procedure at power stable condition... 43

Figure 16: t

RRD

timing ... 56

Figure 17: t

FAW

timing... 57

Figure 18: REFRESH command timing... 58

Figure 19: Postponing REFRESH commands (1X REFRESH mode) ... 58

Figure 20: Pulling in REFRESH commands (1X REFRESH mode)... 59

Figure 21: CAL timing definition ... 60

Figure 22: Command/ Address parity operation... 61

Figure 23: DLL-off mode read timing operation... 62

Figure 24: DLL-switch Sequence from DLL-on to DLL-off ... 63

Figure 25: DLL-switch Sequence from DLL-off to DLL-on ... 65

Figure 26: Write leveling concept, example 1 ... 66

Figure 27: Write leveling concept, example 2 ... 67

Figure 28: Write leveling Sequence (DQS capturing CK low at T1 and CK high at T2) ... 68

Figure 29: Write leveling exit ... 69

Figure 30: Functional representation of ODT ... 70

Figure 31: Synchronous ODT timing with BL8 ... 72

Figure 32: Synchronous ODT timing with BC4... 73

Figure 33: ODT during Reads ... 73

Figure 34: Dynamic ODT (1t

CK

preamble; CL=14, CWL=11, BL=8, AL=0, CRC disabled)... 74

Figure 35: Dynamic overlapped with R

TT_NOM

(CL=14, CWL=11, BL=8, AL=0, CRC disabled) ... 75

Figure 36: Asynchronous ODT timings with DLL off ... 76

Figure 37: Ordering information... 78

Figure 38: 3D4D16G72LB2832 mechanical drawing ... 79

Figure 39: 3D4D16G72LB2832 marking ... 80

1. DOCUMENTS

1.1 APPLICABLE DOCUMENTS

[AD1] 3DPA-8204: Detail Specification 16 Gbit DDR4 SDRAM P/N: 3D4D16G72LB2832 [AD2] 3300-8283: Automatic Assembly Recommendations – BGA modules

[AD3] 3000-1366: Pinout P/N : 3D4D16G72LB2832 [AD4] 3250-0100: Footprint

[AD5] 3200-3770: Step file

1.2 REFERENCE DOCUMENTS

[RD1] 3315-0188: TID & SEE Generic Report [RD2]

[RD3]

[RD4]

1.3 ACRONYMS

ECC Error Correcting Code SEFI Single Event Functional Interrupt

ESD ElectroStatic Discharge SEL Single Event Latch up

HBM Human Body Model SET Single Event Transient

I/O Input/Output SEU Single Event Upset

SEE Single Event Effect TID Total Ionizing Dose

2. GENERAL DESCRIPTION 1.1 INTRODUCTION

The 3D4D16G72LB2832 is an 18 Gbit DDR4 SDRAM module designed for use in Space Flight applications that is organized as 256M x 72 bits. The module is organized as five 256M x 16b devices in parallel, where the uppermost byte lane of the fifth chip is not accessible, yielding a data bus width of 72 bits. Typical application includes but are not limited to, implementing a 64 bit wide user data bus, while allocating the uppermost 8 bits for ECC.

3D PLUS Space Grade DDR4 modules offer the highest bandwidth and total memory density for space applications. 3D4D16G72LB2832 is capable of a maximum data transfer rate of 2400MT/s at a maximum clock frequency of 1200MHz.

In addition to offering increased density and bandwidth in comparison to the previous DDR3 generation, DDR4 permits lower power up consumption. Overall power efficiency can also be increased by using 3DPLUS’s DDR4 Termination Regulator (see below short overview).

The 3D4D16G72LB2832 requires dual power rails: 1.2V for V

DD

and V

DDQ

, and 2.5V for V

PP

DRAM activating Power Supply.

3D PLUS’s DDR4 memory modules are part of a complete DDR4 ecosystem, providing a fully space-qualified memory subsystem solution. This ecosystem includes also:

 DDR4 Termination Regulator is designed for use with this memory module to ensure signal integrity and electrical performances.

 DDR4 Radiation Intelligent Memory Controller (RIMC) IP core provides SEU enhanced protection and mitigation when implemented in the end user application as the memory controller.

1 2

3 4 DQ[15:0] 5

DQ[31:16]

DQ[47:32]

DQ[63:48]

CB[7:0]

A[16:0], BA[1:0], BG0, CKE, RAS_n, CAS_n, WE_n, CK_t,

CK_c, ACT_n, CS_n DQS8_t, DQS8_c, DM8_n, DBI8_n

DQS6_t, DQS6_c, DM6_n, DBI6_n DQS7_t, DQS7_c, DM7_n, DBI7_n DQS4_t, DQS4_c, DM4_n, DBI4_n DQS5_t, DQS5_c, DM5_n, DBI5_n DQS2_t, DQS2_c, DM2_n, DBI2_n DQS3_t, DQS3_c, DM3_n, DBI3_n DQS0_t, DQS0_c, DM0_n, DBI0_n DQS1_t, DQS1_c, DM1_n, DBI1_n

Figure 1:Functional Block Diagram

Note : The 9th byte (device number 5) is not connected in the module.

2.1 TYPE VARIANTS

Variants of the module specified herein, are given in Table 1.

Variant – Part Number Operating

Temperature Range Grade Package Balls Material 3D4D16G72LB2832 CN 0°C to +70°C Commercial BGA 259 balls Sn

10

Pb

90

3D4D16G72LB2832 IB -40°C to +85°C Industrial BGA 259 balls Sn

10

Pb

90

3D4D16G72LB2832 IS -40°C to +85°C Space BGA 259 balls Sn

10

Pb

90

3D4D16G72LB2832 SS -40°C to +105°C Space BGA 259 balls Sn

10

Pb

90

Table 1: Component Type Variants Note:

These variants are suitable for automatic reflow assembly process.

Module assembly on board must follow reflow guidelines as defined in :

http://www.3d-plus.com/technical-documentation.php

2.2 RADIATION PERFORMANCES

The following generic radiation tolerance data are available at 3D PLUS:

Parameter Description

Total Dose Radiation (TID) > 100 krad(Si) Single Event Latchup (SEL) > 62.8 MeV.cm²/mg

Single Event Upset (SEU) Threshold LET > 2.6 MeV.cm

²

/mg

Single Event Functional Interrupt (SEFI) Threshold LET <2.6 MeV.cm

²

/mg Saturated Xsection: 5 10

^-5

cm

²

/device Table 2: Generic Radiation Data DDR4 module without RIMC DDR4

- SEU LET Threshold: > 2.6 MeV.cm²/mg, saturated cross section ≈ 4·10

^-12

cm

^-2

/bit

- WB

TREF = 64 ms

LET Threshold: > 31 MeV.cm²/mg, saturated cross section ≈ 3·10

^-13

cm

^-2

/bit - SEFI LET Threshold: < 2.6 MeV.cm²/mg, saturated cross section ≈ 5·10

^-5

cm²/dev

Parameter Description

Total Dose Radiation (TID) > 100 krad(Si) Single Event Latchup (SEL) > 62.8 MeV.cm²/mg

SEU/SERE/SECE Enhanced Protection with 3DIPMC0815 ECC

Table 3: Generic Radiation Data DDR4 module with RIMC DDR4

3D PLUS offers the Radiation Intelligent Memory Controller (RIMC) IP IDDR4, 3D PLUS part number

3DIPMC0815, in order to provide enhanced protection against radiation effects such as SEU/SEFI.

This added value, besides proposing a high performing and flexible controller, mitigates 3D PLUS DDR4 SEU, allowing designer to get rid of such constraints, and permits him to focus on his application.

3. FUNCTIONAL DESCRIPTION

3D PLUS’s DDR4 SDRAM modules are high-speed, dynamic random access memory modules that use internally configured 8-banks DDR4 SDRAM devices.

To achieve high-speed operation, the double data rate architecture is an 8n-prefetch pipeline architecture with an interface designed to transfer two data words per clock cycle.

The DDR4 SDRAM uses a double data rate architecture corresponding to n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.

For read operations, the differential data strobe (DQS_t, DQS_c) is transmitted externally, along with data, and the read data is edge-aligned to the data strobes. For write operations, the DQS must be center-aligned with the data.

Read and write accesses are burst-oriented, where accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. The ACTIVATE command is used to open (activate) a row in a particular bank for subsequent access. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits that are registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits (including CS_n, BA[1:0], and A[15:0] ) that are registered coincident with the READ or WRITE command are used to select the rank, bank, and starting column location for the burst access.

All the control and address inputs are synchronized with a pair of externally supplied differential clocks.

Inputs are latched at the cross point of differential clocks (CK_t rising and CK_c falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS_t and DQS_c) in a source

synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The data bus inversion (DBI) reduces the power consumption and ground bounce.

3.1 COMMERCIAL, INDUSTRIAL AND SPECIFIC TEMPERATURE

JEDEC 79-4 specifications require the refresh rate to double when T

C

(case temperature) exceeds 85°C; this also requires use of the high-temperature self-refresh option according to Extended Temperature Mode section.

Additionally, ODT resistance, IDD values, some IDD specifications and the input/output impedance must be derated when TC is < 0°C or > 85°C.

TEMPERATURE RANGE RATING

Commercial 0°C ≤ Tcase ≤ 70°C

Industrial -40°C ≤ Tcase ≤ 85°C

Specific -40°C ≤ Tcase ≤ 105°C

Table 4: Temperature Range

3.2 SIMPLIFIED STATE DIAGRAM

Figure 2: Simplified State Diagram

COMMAND DESCRIPTION COMMAND DESCRIPTION

ACT Activate RESET Start reset procedure

PRE Precharge PDE Enter power-down

PREA Precharge all PDX Exit power-down

REF Refresh, fine granularity refresh SRE Self refresh entry

TEN Boundary scan mode enable SRX Self refresh exit

READ RD, RDS4, RDS8 MPR Multipurpose register

READ A RDA, RDAS4, RDAS8 MRS Mode register set

WRITE WR, WRS4, WRS8 with/without CRC

ZQCL ZQ calibration long

WRITE A WRA, WRAS4, WRAS8 with/without CRC

ZQCS ZQ calibration short

4. PINOUT

4.1 BALL ASSIGNMENTS

Figure 3: Ball Assignements

4.2 INPUT/OUTPUT DESCRIPTION

SYMBOL TYPE FUNCTION

CK_t, CK_c Input

Clock: CK_t and CK-c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and the negative

edge of CK_c.

CKE Input

Clock Enable: CKE High activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row

Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh).

CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT, RESET_n and CKE, are disabled during power-down.

Input buffers, excluding CKE and RESET_n, are disabled during Self-Refresh.

CS_n Input

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection on systems with multiple Ranks. CS_n is

considered part of the command code.

ODT Input

On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When enabled, ODT (RTT) is applied to each DQ, DQSU_t,

DQSU_c,DQSL_t, tDQSL_c, DMU_n and DML_n signal.

The ODT pin will be ignored if the mode registers are programmed to disable RTT.

ACT_n Input Activation Command input: ACT_n indicates an ACTIVATE command being entered along with CS_n. The input into WE/A14 will be considered as Row Address A14.

RAS_n / A16 CAS_n / A15 WE_n / A14

Input

Command input: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and ACT_n) define the command and/or address being entered.

For example, for activation with ACT_n Low, A14 becomes valid as an address value. However, for non-activation

commands with ACT_n High, they are Command pins for Read, Write and other command defined in command truth table.

DM0_n –

DM8_n Input

Input data mask: DM_n is an input mask signal for write data. Input data is masked when DM is sampled LOW coincident with that input data during a write access. DM

is sampled on both edges of DQS. The DM and DBI function are enabled by mode register settings. See the Data Mask section.

BA0 – BA1 Input

Bank Address Inputs: BA0 – BA1 define to which bank an Activate, Read, Write, or Precharge command is being applied. Bank address also determines which mode

register is to be accessed during an MRS cycle.

BG0 input

Bank Group Input: BG0 defines to which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is

to be accessed during a MRS cycle.

A0 - A16 Input

Address inputs: Provide the row address for ACTIVATE commands and the column address for READ/WRITE commands to select one location out of the memory array

in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have additional functions, see individual entries in this table.) The address inputs

also provide the op-code during the MODE REGISTER SET command.

A10 / AP Input

Auto precharge: A10 is sampled during READ and WRITE commands to determine whether auto precharge should be performed to the accessed bank after a READ or

WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE

applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be

precharged, the bank is selected by the bank group and bank addresses.

SYMBOL TYPE FUNCTION

A12 / BC_n Input

Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst

chopped). See command truth table for details.

RESET_n Input

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation.

RESET_n is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD.

DQ Input /

Output

Data input/output: Bidirectional data bus. If write CRC is enabled via mode register, the write CRC code is added at the end of data burst.

DBI0_n – DBI8_n Input / Output

DBI input/output: Data bus inversion.

DBI can be configured for both READ (output) and WRITE (input) operations depending on the mode register settings. The DM,DBI, and TDQS functions are

enabled by mode register settings. See the Data Bus Inversion section.

DQS_t, DQS_c Input / Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS_t is paired with differential signals

DQS_c to provide differential pair signaling to the system during reads and writes.

DDR4 SDRAM supports differential data strobe only and does not support single- ended.

PAR Input

Parity for command and address: This function can be enabled or disabled via the mode register. When enabled, the parity signal covers all command and address

inputs, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n, BA[1:0], and BG0. Control pins NOT covered by the parity signal are

CS_n, CKE, and ODT. Command and address inputs will have parity check performed when commands are latched via the rising edge of CK_t and when CS_n

is LOW.

ALERT_n Output

Alert output: This signal allows the DRAM to indicate to the system's memory controller that a specific alert or event has occurred. Alerts will include the command/address parity error and the CRC data error when either of these

functions is enabled in the mode register.

NC No Connect: No internal electrical connection is present.

V

DD

Supply Power Supply: 1.2V ±0.060V.

GND Supply Ground

V

PP

Supply DRAM activating power supply: 2.5V –0.125V/+0.250V V

REFCA

Supply Reference voltage for control, command, and address pins.

Table 5: Ball Description Note:

1. Input only pins (BA0-BA1, BG0, A0-A14, ACT#, RAS#, CAS#, WE#/A14, CS_n, CKE, ODT and RESET_n) do not supply

termination.

5. ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL VALUE UNIT NOTE

Voltage on V

DD

pin relative to V

SS

V

DD

-0.3 ~ 1.5 V 1, 3

Voltage on V

DDQ

pin relative to V

SS

V

DDQ

-0.3 ~ 1.5 V 1, 3

Voltage on V

PP

pin relative to V

SS

V

PP

-0.3 ~ 3.0 V 4

Voltage on any pin except V

REFCA

relative to VSS VIN, VOUT -0.3 ~ 1.5 V 1, 3, 5

Storage temperature T

STG

-55 ~ +150 °C 1, 2

Operating case temperature – Industrial Tc -40 ~ +85 °C 6,7,8,9

Operating case temperature – specific Tc -40 ~ +105 °C 6,7,8,9

Table 6: Absolute Maximum Ratings Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to the JESD51-2 standard.

3. VDD and VDDQ must be within 300 mV of each other at all times; and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV.

4. VPP must be equal or greater than VDD/VDDQ at all times

5. Overshoot area above 1.5 V is specified in “overshoot and undershoot specifications sections.

6. MAX operating case temperature. TC is measured in the center/top side of the package.

7. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.

8. The Auto-Refresh command interval can be kept at normal value t

REFI

= 7.8µs with Tc ≤ 85°C. For operation above 85°C case temperature, Refresh command must be doubled in frequency, therefore reducing the refresh interval t

REFI

to 3.9µs is required.

9. REFRESH command must be issued once every 0.975µs if TC is greater than 105°C, once every 1.95µs if TC is greater than

or equal to 95°C, once every 3.9µs if TC is greater than 85°C, and once every 7.8µs if TC is less than 85°C.

6. ELECTRICAL CHARACTERISTICS

6.1 RECOMMENDED DC OPERATING CONDITIONS

SYMBOL PARAMETER

RATINGS

UNITS NOTES

MIN TYP MAX

V

DD

Supply Voltage 1.14 1.20 1.26 V 1, 2, 3,

V

DDQ

Supply voltage for output 1.14 1.20 1.26 V 1, 2, 3

V

PP

Peak-to Peak Voltage 2.375 2.5 2.75 V 3

Table 7: DC Operating Conditions Notes:

1. Under all conditions V

DDQ

must be less than or equal to V

DD

.

2. V

DDQ

tracks with V

DD

. AC parameters are measured with V

DD

and V

DDQ

tied together.

3. DC bandwith is limited to 20 MHz.

6.2 INPUT AC AND DC OPERATING CONDITIONS

SYMBOL PARAMETER MIN MAX UNITS NOTES

V

IH.CA

(DC75) DC input logic high V

REFCA

+ 0.075 V

DD

V

V

IL.CA

(DC75) DC input logic low V

SS

V

REFCA

- 0.075 V

V

IH.CA

(AC100) AC input logic high V

REF

+ 0.1 Note 2 V 1

V

IL.CA

(AC100) AC input logic low Note 2 V

REF

- 0.1 V 1

V

REFCA

(DC) Reference voltage for ADD, CMD

inputs 0.49 x V

DD

0.51 x V

DD

V 2,3

Table 8: Input Operating Conditions Notes:

1. See “Overshoot and Undershoot specifications”

2. The AC peak noise on V

REFCA

may not allow V

REFCA

to deviate from V

REFCA

(DC) by more than +/- 1% V

DD

(for reference:

approximatively +/-12 mV.

3. For reference approx. VDD/2 +/- 12 mV.

6.2.1 VREF V

REFCA

The DC-tolerance limits and AC-noise limits for the reference voltages V

REFCA

is illustrated in Figure 4. It shows a valid reference voltage V

REF

(t) as a function of time. (V

REF

stands for V

REFCA

).

V

REF

(DC) is the linear average of V

REF

(t) over a very long period of time (e.g., 1 sec). This average has to

meet the min/max requirement in Table 18. Furthermore V

REF

(t) may temporarily deviate from V

REF

(DC) by

no more than ± 1% VDD for the AC-noise limit.

Figure 4: V

REFDQ

Voltage Range

The voltage levels for setup and hold time measurements V

IH

(AC), V

IH

(DC), V

IL

(AC), and V

IL

(DC), are dependent on V

REF

. " V

REF

" shall be understood as V

REF

(DC), as defined in Figure above.

This clarifies, that DC-variations of V

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for V

REF

(DC) deviations from the optimum position within the data-eye of the input signals.

The voltage levels for setup and hold time measurements are dependent on V

REF

. V

REF

is understood as V

REF

(DC), as defined in the above figure. This clarifies the DC-variations of VREF, affect the absolute voltage a signal has to reach to achieve a valid HIGH or LOW level, and therefore, the time to which setup and hold is measured.

System timing and voltage budgets need to account for V

REF

(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/ hold specification and derating values need to include time and voltage associated with V

REF

AC-noise. Timing and voltage effects due to AC-noise on V

REF

up to the specified limit (+/- 1 % of V

DD

) are included in DRAM timings and their associated deratings.

V

REFDC

The device internally generates its own V

REFDQ

, DRAM internal VREFDQ specification parameters: voltage range, step size, VREF step time, VREF full step time and VREF valid level are used to help provide estimated values for the internal VREFDQ and are not pass/ fail limits. The voltage operating range specifies the minimum required range for DDR4 SDRAM devices. The minimum range is defined by VREFDQmin and VREFDQmax.

A calibration sequence should be performed by the DRAM controller to adjust VREFDQ and optimize the timing and voltage margin of the DRAM data input receivers.

PARAMETER SYMBOL MIN TYP MAX UNIT NOTES

Range 1 V

REFDQ

operating points V

REFDQ

R1 60% - 92% V

DDQ

1,2

Range 2 V

REFDQ

operating points V

REFDQ

R2 45% 77% V

DDQ

1,2

V

REF

step size V

REF, step

0.5% 0.65% 0.8% V

DDQ

3

V

REF

set tolerance V

REF, set_tol

-1.625% 0% 1.625% V

DDQ

4,5,6

-0.15% 0% 0.15% V

DDQ

4,7,8

V

REF

step time V

REF, time

- - 150 ns 9,10,11

V

REF

valid tolerance V

RE_val_tol

-0.15% 0% 0.15% V

DDQ

12

Table 9: Output Operating Conditions

Notes:

1. V

REFDQ

voltage is referenced to VDDQ(DC). VDDQ(DC) is 1.2V.

2. DRAM range 1 or range 2 is set by the MRS6[6]6.

3. V

REF

step size increment/ decrement range. V

REF

at DC level.

4. V

REF

,new = VREF,old ±n × V

REF

,step; n = number of steps. If increment, use “+,” if decrement,use “-.”

5. For n >4, the minimum value of V

REF

setting tolerance = V

REF

,new - 1.625% × VDDQ. The maximum value of V

REF

setting tolerance = V

REF

,new + 1.625% × VDDQ.

6. Measured by recording the MIN and MAX values of the V

REF

output over the range, drawing a straight line between those points, and comparing all other V

REF

output settings to that line.

7. For n <4, the minimum value of V

REF

setting tolerance = V

REF

,new - 0.15% × VDDQ. The Maximum value of V

REF

setting tolerance = V

REF

,new + 0.15% × VDDQ.

8. Measured by recording the MIN and MAX values of the V

REF

output across four consecutive steps (n = 4), drawing a straight line between those points, and comparing all V

REF

output settings to that line.

9. Time from MRS command to increment or decrement one step size for V

REF

.

10. Time from MRS command to increment or decrement more than one step size up to the full range of V

REF

. 11. If the V

REF

monitor is enabled, V

REF

must be derated by +10ns if DQ bus load is 0pF and an additional +15 ns/pF

of DQ bus loading.

12. Only applicable for DRAM component-level test/ characterization purposes. Note applicable for normal mode of operation. V

REF

valid qualifies the step times, which will be characterized at the component level.

6.2.2 Single ended inputs measurements levels

SYMBOL PARAMETER MIN MAX UNIT

VIH(AC) AC Input High Voltage 0.8*V

DD

V

DD

V

VIH(DC) DC Input High Voltage 0.7*V

DD

V

DD

V

VIL(DC) DC Input Low Voltage V

SS

0.3* V

DD

V

VIL(AC) AC Input Low Voltage V

SS

0.2* V

DD

V

Table 10 : RESET_n, TEN and ALERT_n inputs levels

SYMBOL PARAMETER MIN MAX UNIT

VIH(AC) AC Input High Voltage V

REF

+ 0.1 Note 1 V

VIH(DC) DC Input High Voltage V

REFCA

+ 0.0075 V

DD

V

VIL(DC) DC Input Low Voltage V

SS

V

REFCA

– 0.0075 V

VIL(AC) AC Input Low Voltage Note 1 V

REF

– 0.1 V

VREFCA(DC) Ref voltage for ADD,

CMD inputs 0.49* V

DD

0.51* V

DD

Table 11 : Command/address input levels

Note 1: The ac peak noise on VREF may not allow VREF to deviate from V

REFCA(DC)

by more than ±1% V

DD

SYMBOL PARAMETER MIN MAX UNIT

VIH(AC) AC Input High Voltage V

REFCA

+ 0.2 Note 1 V

VIH(DC) DC Input High Voltage V

REFCA

+ 0.15 V

DD

V

VIL(DC) DC Input Low Voltage V

SS

V

REFCA

- 0.15 V

VIL(AC) AC Input Low Voltage Note 1 V

REFCA

- 0.2 V

Table 12 : CT type-A input levels

Note 1: Refer to undershoot/overshoot specifications

Note 2: CT type-A inputs: CS_n, BG0, BA0, BA1, A0-A9, A10, A11, A12, A13, A14, A15, A16, CKE, ACT_n, ODT, CK, CK_n, PAR

SYMBOL PARAMETER MIN MAX UNIT

VIH(AC) AC Input High Voltage V

REFDQ

+ 0.3 Note 1 V

VIH(DC) DC Input High Voltage V

REFDQ

+ 0.2 V

DD

V

VIL(DC) DC Input Low Voltage V

SS

V

REFDQ

- 0.2 V

VIL(AC) AC Input Low Voltage Note 1 V

REFDQ

- 0.3 V

Table 13 : CT type-B input levels

Note 1: Refer to undershoot/overshoot specifications

Note 2: CT type-B inputs: DM_n, DBI_n, LDM_n, LDBI_n, UDM_n, UDBI_n Note 3: V

REFDQ

should be ½ V

DD

6.3 AC AND DC LEVELS FOR DIFFERENTIAL SIGNALS 6.3.1 Differential signal definition

Figure 5 : Differential signal defintion 6.3.2 Differential input swing requirements for CK-CK_n

SYMBOL PARAMETER MIN MAX UNIT NOTE

V

IHdiff

Differential input high 0.135 Note 3 V 1

V

ILdiff

Differential input low Note 3 -0.135 V 1

V

IHdiff (AC)

Differential input high ac 2*(V

IH(AC

) – V

REF

) Note 3 V 2 V

ILdiff (AC)

Differential input low ac Note 3 2*(V

IL(AC

) – V

REF

) V 2

Table 14 : Differential swing requirements for CK, CK_n

Note 1 : Used to define a differential signal slew-rate.

Note 2 : For CK and CK_n use V

IH(AC

) and V

IL(AC)

of ADD/CMD and V

REFCA

.

Note 3 : These values are not defined; however, the differential signals (CK, CK_n) need to be within the respective limits, V

IH(DC) max

and V

IL(DC) min

for single-ended signals as well as the limitations for overshoot and undershoot

6.3.3 Single-ended requirements for CK differential signals

Each individual component of a differential signal (CK, CK_n) has also to comply with certain requirements for single-ended signals. CK and CK_n have to reach approximately V

SEHmin

/ V

SELmax

, approximately equal to the ac-levels V

IH(AC)

and V

IL(AC

) for ADD/CMD signals in every half-cycle. For example., if a value other than 100mV is used for ADD/CMD V

IH(AC)

and V

IL(AC

) signals, then these ac-levels apply also for the single-ended signals CK and CK_n.

While ADD/CMD signal requirements are with respect to V

REFCA

, the single-ended components of differential signals have a requirement with respect to V

DD

/ 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach V

SELmax

, V

SEHmin

has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.

Figure 6 : Single-ended requirement for CK

SYMBOL PARAMETER MIN MAX UNIT NOTE

V

SEH

Single-ended high-level for

CK, CK_n (V

DD

/2) + 0.095 Note 3 V 1,2

V

SEL

Single-ended low-level for

CK, CK_n Note 3 (V

DD

/2) - 0.095 V 1,2

Table 15 : Single ended requirement for CK, CK_n

Note 1 : For CK and CK_n use V

IH(AC

) and V

IL(AC)

of ADD/CMD and V

REFCA

. Note 2 : ADD/CMD V

IH(AC

) and V

IL(AC)

based on V

REFCA

.

Note 3 : These values are not defined; however, the differential signals (CK, CK_n) need to be within the respective limits, V

IH(DC) max

and

V

IL(DC) min

for single-ended signals as well as the limitations for overshoot and undershoot

6.3.4 Slew rate definition for CK differential input signal

Figure 7 : Differential input slew rate definition for CK, CK_n

6.3.5 CK differential input cross point voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signal CK, CK_n must meet the requirements shown below. The differential input cross point voltage V

IX(CK)

is measured from the actual cross point of true and complement signals to the midlevel between V

DD

and V

SS

.

Figure 8 : V

IX(CK)

definition

*

SYMBOL PARAMETER INPUT LEVEL CONDITION MIN MAX

V

IX(CK)

Differential input cross point voltage relative

to V

DD

/2 for CK_t, CK_c

If V

SEH

> V

DD

/2 + 145 mV -- 120 mV

If V

DD

/2 + 100 mV <= V

SEH

<=

V

DD

/2 + 145 mV -- (V

SEH

– V

DD

/2) – 25

mV If V

DD

/2 + 145 mV <= V

SEL

<=

V

DD

/2 - 100 mV

(V

DD

/2 - V

SEH

) + 25

mV --

If V

SEL

< V

DD

/2 + 145 mV -120 mV --

Table 16 : Cross point voltage for CK differential input signals

Note 1 : Extended range for V

IX(CK)

is only allowed if single-ended clock input signals CK and CK are monotonic with a single-ended swing V

SEL

/V

SEH

of at least V

DD

/2 ±250mV, and when the differential slew rate of CK – CK_n is larger than 4V/ns.

Note 2 : The relation between V

IX(CK)

Min/Max and V

SEL

/V

SEH

should satisfy following:

(V

DD

/2) + V

IX(CK) Min

) - V

SEL

=> 25mV V

SEH

- ((V

DD

/2) + V

IX(CK) Max

) => 25mV

6.3.6 Slew rate definitions for DQS differential input signals

Figure 9 : Differential input slew rate and input level definition for DQS – DQS_n

SYMBOL PARAMETER MIN MAX UNIT

V

IHDiff_DQS

Differential input high 130 mV

V

ILDiff_DQS

Differential input low -130 mV

V

IHDiff_Peak

V

IH

diff. peak voltage 160 V

DDQ

mV

V

ILDiff_Peak

V

IL

diff peak voltage V

SSQ

-160 mV

SR

Idiff

Differential input slew rate 3 18 V/ns

Table 17 : Differential input slew rate and input levels for DQS-DQS_n 6.3.7 DQS differential input cross point voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signal DQS, DQS_n must meet the requirements shown below.

The differential input cross point voltage V

IX(DQS)

is measured from the actual cross point of true and

complement signals to the midlevel between V

DD

and V

SS

.

Figure 10 : V

IX(DQS)

definition

SYMBOL PARAMETER MIN MAX UNIT NOTE

V

IX_DQS_ratio

DQS differential input cross point

voltage ratio -- 25 % 1, 2

V

DQSmid_to Vcent

V

DQSmid

offset relative to V

cent_DQ

(midpoint) -- Min(V

IHdiff

, 50) mV 3, 4, 5

Table 18 : Cross point voltage for differential input signals DQS

Note 1 : V

IX_DQS_ratio

is DQS VIX crossing (V

IX_DQS_FR

or V

IX_DQS_RF

) divided by V

DQS_trans

. V

DQS_trans

is the difference between the lowest horizontal tangent above V

DQSmid

of the transitioning DQS signals and the highest horizontal tangent below V

DQSmid

of the transitioning DQS signals.

Note 2: V

DQSmid

will be similar to the V

REFDQ

internal setting value obtained during Vref training if the DQS and DQ drivers and paths are matched.

Note 3: The maximum limit shall not exceed the smaller of V

IHdiff

minimum limit or 50 mV

Note 4: VIX measurements are only applicable for transitioning DQS and DQS_n signals when toggling data, preamble and high-z states are not applicable conditions.

Note 5: The parameter V

DQSmid

is defined for simulation and ATE testing purposes, it is not expected to be tested in a system.

6.4 OVERSHOOT AND UNDERSHOOT SPECIFICATIONS 6.4.1 Address, commands and controls

DESCRIPTION SYMBOL MAX UNITS

A[0:13],A17, BG0, BA[1:0], ACT_n, RAS_n, CAS_n/A15, CS_n, WE_n, CKE, ODT, C2-C0

Maximum peak amplitude above V

AOS

V

AOSP

0.06 V

Upper boundary of overshoot area A

AOS1

V

AOS

V

DD

+ 0.24 V

Maximum peak amplitude allowed for undershoot V

AUS

0.30 V

Maximum overshoot area per 1t

CK

above V

AOS

A

AOS2

0.0055 V/ns

Maximum overshoot area per 1t

CK

between V

DD

and V

AOS

A

AOS1

0.1699 V/ns

Maximum undershoot area per 1t

CK

below V

SS

A

AUS

0.1762 V/ns

Table 19: ADDR, CMD, CNTL overshoot and undershoot specifications

Figure 11: Address, command, control overshoot and undershoot definition Note:

1. The value of V

AOS

matches VDD absolute max as defined in Table 6“Absolute Maximum DC Ratings” if VDD equals VDD max as defined in Table 9: “Recommended DC Operating Conditions” . If V

DD

is above the recommended operating conditions, V

AOS

remains at V

DD

. 6.4.2 Clock

DESCRIPTION SYMBOL MAX UNITS

CLK_t, CLK_n

Maximum peak amplitude above V

COS

V

COSP

0.06 V

Upper boundary of overshoot area V

COS1

V

COS

V

DD

+ 0.24 V

Maximum peak amplitude allowed for undershoot V

CUS

0.30 V

Maximum overshoot area per 1UI above V

COS

A

COS2

0.0025 V/ns

Maximum overshoot area per 1UI between V

DD

and V

AOS

A

COS1

0.0750 V/ns

Maximum undershoot area per 1UI below V

SS

A

CUS

0.0762 V/ns

Table 20: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications

Figure 12: CKL overshoot and undershoot definition Note:

1. The value of V

COS

matches V

DD

absolute max as defined in Table 6 Absolute Maximum DC Ratings if V

DD

equals V

DD

max as defined in Table 9: Recommended DC Operating Conditions. If V

DD

is above the recommended operating conditions, V

COS

remains at V

DD

absolute max.

6.4.3 Data, strobe and mask

DESCRIPTION SYMBOL MAX UNITS NOTES

DQS_t, DQS_c, DQ[0:71], DM/DBI

Maximum peak amplitude above V

DOS

V

DOSP

0.16 V

Upper boundary of overshoot area A

DOS1

V

DOS

V

DDQ

+0.24 V 1

Lower boundary of overshoot area A

DUS1

V

DUS

0.30 V 2

Maximum peak amplitude below V

DUS

V

DUSP

0.10 V

Maximum overshoot area per 1UI above V

DOS

A

DOS2

0.0100 V/ns

Maximum overshoot area per 1UI between V

DDQ

and V

DOS

A

DOS1

0.0700 V/ns Maximum undershoot area per 1UI below V

SSQ

and V

DUS1

A

DUS1

0.0700 V/ns

Maximum undershoot area per 1UI below V

DUS

V

DUS2

0.0100 V/ns

Table 21: Data, strobe, and mask overshoot and undershoot specifications

Figure 13: Data, strobe, and mask overshoot and undershoot definition Note:

1. The value of V

DOS

matches (V

IN

, V

OUT

) max as defined in Table 4 Absolute Maximum DC Ratings if V

DDQ

equals V

DDQ

max as defined in Table 9:”Recommended DC Operating Conditions. If V

DDQ

is above the recommended operating conditions, V

DOS

remains at (V

IN

, V

OUT

) max.

2. The value of V

DUS

matches (V

IN

, V

OUT

) min as defined in Table 6:”Absolute Maximum DC Ratings”.

6.5 MODULE CAPACITANCE

SYMBOL PARAMETER MIN MAX UNITS NOTES

C

IO

Input/output capacitance (DQ, DM, DQS_t, DQS_c) 2.75 5.75 pF 1, 2

C

CK

Input capacitance, CK_t and CK_c 1 3.5 pF 2

C

DCK

Input capacitance delta, CK_t and CK_c 0 0.25 pF 2, 5

C

DDQS

Input capacitance delta DQS_t and DQS_c 0 0.25 pF 2, 4

C

I

Input capacitance, (CTRL, ADD, CMD input-only pins) 1 3.5 pF 2, 3, 6 C

DI_CTRL

Input capacitance delta, (All CTRL input-only pins) -0.5 0.5 pF 2, 7, 8 C

DI_ADD_CMD

Input capacitance delta, (All ADD/CMD input-only pins) -0.5 0.5 pF 1, 2, 9, 10

C

ALERT

Input/output capacitance ALERT pin 2.5 7.5 pF 2

C

DIO

Input/output capacitance delta (DQ, DM, DQS_t, DQS_c) -0.5 0.5 pF 1, 2, 3 Table 22: Pin capacitances

Notes:

1. Although the DMx pins have different functions, the loading matches DQ, DQS

2. This parameter is not subject to a production test; it is verified by design and characterization. V

DD

, V

DDQ

, V

SS

, V

SSQ

applied and all other pins (except the pin under test) floating. V

DD

= V

DDQ

= 1.2V, V

BIAS

=V

DD

/2 and on-die termination off

3. C

DIO

= C

IO

(DQ, DM) - 0.5 × (C

IO

(DQS_t) + C

IO

(DQS_c)).

4. Absolute value of CIO (DQS_t), CIO (DQS_c) 5. Absolute value of CCK_t, CCK_c

6. C

I

applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0, RAS_n, CAS_n, ACT_n, PAR and WE_n.

7. CDI_CTRL applies to ODT, CS_n, and CKE.

8. CDI_CTRL = C

I

(CTRL) - 0.5 × (C

I

(CLK_t) + C

I

(CLK_c)).

9. CDI_ADD_CMD applies to A[17:0], BA1:0], BG0, RAS_n, CAS_n, ACT_n, PAR and WE_n.

10. CDI_ADD_CMD = CI(ADD_CMD) - 0.5 × (CI(CLK_t) + CI(CLK_c)).

6.6 CURRENT SPECIFICATION LIMITS

I

DD

and I

PP

values are for typical operating range of voltage and temperature unless otherwise noted.

SYMBOL PARAMETER VALUE UNIT

I

DD0

Operating One Bank Activate-to-Precharge Current (AL=0) 131 mA

I

PP0

Operating One Bank Activate-to-Precharge Current 10 mA

I

DD1

Operating One Bank Active-Read-Precharge Current (AL=0) 187 mA

I

DD2P

Precharge Power-Down Current 58 mA

I

DD2Q

Precharge Quiet standby Current 94 mA

I

DD2N

Precharge Standby Current 100 mA

I

DD2NT

Precharge Standby ODT Current 176 mA

I

DD3P

Active Power-Down Current 92 mA

I

DD3N

Active Standby Current 120 mA

I

PP3N

Active Standby IPP Current 2 mA

I

DD4W

Operating Burst Write Current 333 mA

I

DD4R

Operating Burst Read Current 365 mA

I

DD6E

Self Refresh Current 40 mA

I

PP6

Auto Self Resfresh IPP Current 5 mA

I

DD7

Operating Bank Interleave Read Current 375 mA

I

PP7

Operating Bank Interleave Read IPP Current 50 mA

I

DD8

Maximum Power-down current 24 mA

Table 23: I

DD

limits for a single embedded component

Notes: When Tc < 0°C, or Tc > 95°C, I

DD

values require derating by up to 20%.

6.7 OUTPUT AC AND DC OPERATING CONDITIONS

SYMBOL PARAMETER MIN UNITS

V

OH(DC)

DC output high measurement level (for IV curve linearity) 1.1 x V

DDQ

V

V

OM(DC)

DC output middle measurement level (for IV curve linearity) 0.8 x V

DDQ

V

V

OL(DC)

DC output low measurement level (for IV curve linearity) 0.5 x V

DDQ

V

V

OH(AC)

AC output high measurement level (for output Slew Rate) (0.7 + 0.15) x V

DDQ

V

V

OL(AC)1

AC output low measurement level (for output Slew Rate) (0.7 - 0.15) x V

DDQ

V

V

OHdiff(AC)2

AC differential output high measurement level (for output SR) +0.3 x V

DDQ

V

SYMBOL PARAMETER MIN UNITS V

OLdiff(AC)2

AC differential output low measurement level (for output SR) -0.3 x V

DDQ

V

V

OH(DC)

DC output high measurement level (for IV curve linearity) 1.1 x V

DDQ

V V

OM(DC)

DC output middle measurement level (for IV curve linearity) 0.8 x V

DDQ

V V

OL(DC)

DC output low measurement level (for IV curve linearity) 0.5 x V

DDQ

V V

OB(DC)

DC output below measurement level (for IV curve linearity) 0.2 x V

DDQ

V V

OL(AC)1

AC output low measurement level (for output Slew Rate) V

TT

+ 0.1 x V

DDQ

V V

OH(AC)1

AC differential output high measurement level (for output SR) V

TT

- 0.1 x V

DDQ

V

Table 24: Output Operating Conditions Notes:

1. The swing of ±0.15 × V

DDQ

is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of R

ZQ

/7 Ω and an effective test load of 50Ω to V

TT

= V

DDQ

.

2. The swing of ± 0.3 × V

DDQ

is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of R

ZQ

/7 Ω and an effective test load of 50Ω to V

TT

= V

DDQ

at each of the differential outputs.

6.8 SPEED BINS

CL-nRCD-nRP 17-17-17

UNITS NOTES

PARAMETER SYMBOL MIN MAX

Internal read command to first data t

AA

13.32 19.00 ns 7

Internal READ command to first data

with read DBI enabled t

AA_DBI

t

AA

(MIN) + 3nCK t

AA

(MAX) +

3nCK ns 7

ACT to internal read or write delay

time t

RCD

13.32 - ns 7

PRE command period t

RP

13.32 - ns 7

ACT to ACT or REF command time t

RC

45.32 9 x t

REFI

ns 7

ACT to PRE command period t

RAS

32 ns 7

Normal Read DBI

CWL = 9

CL = 9 CL = 11 t

CK(AVG)

1.50 1.60 ns 1,2,3,6

CL = 10 CL = 12 t

CK(AVG)

ns 4

CWL = 9,11

CL = 10 CL = 12 t

CK(AVG)

Reserved 4

CL = 11 CL = 13 t

CK(AVG)

1.25 <1.50 ns 1,2,3,4,6

CL = 12 CL = 14 t

CK(AVG)

1.25 <1.50 ns 1,2,3,6

CWL = 10,12

CL = 12 CL = 14 t

CK(AVG)

ns 4

CL = 13 CL = 15 t

CK(AVG)

1.071 <1.25 ns 1,2,3,4,6

CL = 14 CL = 16 t

CK(AVG)

1.071 <1.25 ns 1,2,3,6

CL-nRCD-nRP 17-17-17

UNITS NOTES

PARAMETER SYMBOL MIN MAX

CWL = 11,14

CL = 14 CL = 17 t

CK(AVG)

ns 4

CL = 15 CL = 18 t

CK(AVG)

0.937 <1.071 ns 1,2,3,6

CL = 16 CL = 19 t

CK(AVG)

0.937 <1.071 ns 1,2,3,6

CWL = 12,16

CL = 15 CL = 18 t

CK(AVG)

Reserved ns 4

CL = 16 CL = 19 t

CK(AVG)

0.833 <0.937 ns 1,2,3

CL = 18 CL = 21 t

CK(AVG)

0.833 <0.937 ns 1,2,3

Supported CL settings 7-9 nCK

Supported CL Settings with read DBI 8,9 nCK

Supported CWL settings 7,8,9 nCK

Table 25: Speed bins Note:

1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.

2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calculated from tAA following rounding algorithm defined in Section 13.5.

3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e., 1.5ns or 1.25ns or 1.071 ns or 0.937 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Any combination of the ‘optional’ CL’s is supported. The associated ‘optional’ tAA, tRCD, tRP, and tRC values must be adjusted based upon the CL combination supported. Refer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported.

6. Any device speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

7. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.

8. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min), tRCD(min), tRP(min), and tRC(min).

9. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC compliant.

JEDEC compliance does not require support for all speed bins within a given speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.

10. The values defined with above-mentioned table are DLL ON case

11. DDR4-2400 Speed Bin Table is valid only when Geardown Mode is disabled

6.9 AC TIMING PARAMETERS

Table described below is applicable for the basic component embedded in the module.

PARAMETER SYMBOL DDR4-2400

UNITS NOTES

MIN MAX

Clock Timing Minimum Clock Cycle Time (DLL off

mode) t

CK

(DLL_OFF) 8 20 ns

Average Clock Period t

CK

(avg) 0.833 1.9 ns 35,36

Average high pulse width t

CH

(avg) 0.48 0.52 t

CK

(avg)

Average low pulse width t

CL

(avg) 0.48 0.52 t

CK

(avg)

Absolute Clock Period t

CK

(abs)

t

CK

(avg)min + t

JIT

(per)min_tot

t

CK

(avg)max + t

JIT

(per)max_tot

t

CK

(avg)

Absolute clock HIGH pulse width t

CH

(abs) 0.45 - t

CK

(avg) 23

Absolute clock LOW pulse width t

CL

(abs) 0.45 - t

CK

(avg) 24

Clock Period Jitter- total JIT(per)_tot -42 42 ps 25

Clock Period Jitter- deterministic JIT(per)_dj -21 21 ps 26

Clock Period Jitter during DLL

locking period t

JIT

(per, lck) -33 33 ps

Cycle to Cycle Period Jitter t

JIT

(cc)_total - 83 ps 25

Cycle to Cycle Period Jitter

during DLL locking period t

JIT

(cc, lck) - 67 ps

Cumulative error across 2 cycles t

ERR

(2per) -61 61 ps

Cumulative error across 3 cycles t

ERR

(3per) -73 73 ps

Cumulative error across 4 cycles t

ERR

(4per) -81 81 ps

Cumulative error across 5 cycles t

ERR

(5per) -87 87 ps

Cumulative error across 6 cycles t

ERR

(6per) -92 92 ps

Cumulative error across 7 cycles t

ERR

(7per) -97 97 ps

Cumulative error across 8 cycles t

ERR

(8per) -101 101 ps

Cumulative error across 9 cycles t

ERR

(9per) -104 104 ps

Cumulative error across 10 cycles t

ERR

(10per) -107 107 ps

Cumulative error across 11 cycles t

ERR

(11per) -110 110 ps

Cumulative error across 12 cycles t

ERR

(12per) -112 112 ps

Cumulative error across n = 13,

14 . . . 49, 50 cycles t

ERR

(nper)

t

ERR

(nper)min = ((1 + 0.68ln(n)) * t

JIT

(per)_total min)

t

ERR

(nper)max = ((1 + 0.68ln(n)) * t

JIT

(per)_total max)

ps

DQ input Timing

PARAMETER SYMBOL DDR4-2400

UNITS NOTES

MIN MAX

DQ and DM minimum data pulse

width for each input t

DIPW

0.58 - UI

DQ Output Timing (DLL enabled) DQS, DQS to DQ skew, per group,

per access t

DQSQ

- 0.17 UI 13, 18,

39, 49

DQ output hold time from DQS, DQS t

QH

0.74 - UI

DQ Strobe Input Timing DQS_t, DQS_c rising edge to CK,

CK_n rising edge (1 clock preamble) t

DQSS

-0.27 0.27 tCK(avg) 42

DQS_t, DQS_c rising edge to CK,

CK_n rising edge (2 clock preamble) t

DQSS2

-0.5 0.5 tCK(avg) 43

DQS_t, DQS_c differential input low

pulse width t

DQSL

0.46 0.54 tCK(avg)

DQS_t, DQS_c differential input high

pulse width t

DQSH

0.46 0.54 tCK(avg)

DQS_t, DQS_c falling edge setup time

to CK, CK edge rising

t

DSS

0.18 - tCK(avg)

DQS_t, DQS_c falling edge hold time

from CK, CK rising edge t

DSH

0.18 - tCK(avg)

DQS, DQS differential WRITE (1 tCK

preamble) t

WPRE

0.9 - tCK(avg) 42

DQS, DQS differential WRITE (2 tCK

preamble) t

WPRE2

1.8 - tCK(avg) 43

DQS, DQS differential WRITE

Postamble t

WPST

0.33 - tCK(avg)

DQS Strobe Output Timing (DLL enabled) DQS, DQS differential output high

time t

QSH

0.4 - CK 21, 39

DQS, DQS differential output low time t

QSL

0.4 - CK 20, 39

DQS_t, DQS_c low-impedance time

(Referenced from RL-1) t

LZ

(DQS) -330 175 ps

DQS, DQS high-impedance time

(Referenced from RL+BL/2) t

HZ

(DQS) - 175 ps

DQS, DQS differential READ

Preamble(1 clock preamble) t

RPRE

0.9 Note 44 tCK(avg) 37, 40

DQS, DQS differential READ

Preamble(2 clock preamble) t

RPRE2

1.8 Note 44 tCK(avg) 39, 41

DQS, DQS differential READ

Postamble t

RPST

0.33 Note 45- tCK(avg) 39

Command and Address Timing

DLL locking time t

DLLK

768 - nCK

Command and Address setup time to CK_t, CK_c referenced to V

IH

(ac) and V

IL

(ac) levels

t

IS

(base) 62 - ps

Command and Address setup time to

CK_t, CK_c referenced to

VREF

levels t

IS

(V

REF

) 162 - ps