V850E2/FG4. Data Sheet. 32-bit Single-Chip Microcontroller. µpd70f3550. µpd70f4002. Cover. Renesas Electronics

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V850E2/FG4

32-bit Single-Chip Microcontroller

µPD70F3548

µPD70F3549

µPD70F3550

µPD70F4000

µPD70F4001

µPD70F4002

dfgdfg

Dat

a

Sheet

32 Cover

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Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

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• Availability of related technical literature

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In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

Visit

http://www.renesas.com

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Notes for CMOS Devices

(1) Precaution against ESD for semiconductors

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All text and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

(2) Handling of unused input pins for CMOS

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

(3) Status before initialization of MOS devices

Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

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Chapter 1 Overview

. . . 9

1.1 Naming. . . 9

1.1.1 Alternative function pins . . . 9

1.1.2 Power supply pins . . . 9

1.2 Pin Groups. . . 10

1.3 General measurement conditions . . . 10

1.3.1 AC characteristic measurement condition. . . 10

Chapter 2 Absolute maximum ratings

. . . 11

2.1 Supply voltages. . . 11

2.2 Port voltages . . . 12

2.3 Port current . . . 13

2.4 Capacitance . . . 13

2.5 Thermal characteristics . . . 14

Chapter 3 Power supply specification

. . . 15

3.1 Requirements for external power supply connections . . . 15

3.2 Power area definitions . . . 15

3.3 Power supply groups . . . 16

3.4 Supply voltages. . . 17

3.4.1 AWO Regulator characteristics . . . 18

3.4.2 ISO0/ISO1 Regulator characteristics (M1 products) . . . 19

3.4.3 Amplifier characteristics (M2 products) . . . 19

3.4.4 POC characteristics . . . 21

3.4.5 Voltage Comparator characteristics . . . 21

3.5 Power-up/-down sequence of external supply voltages . . . 22

3.5.1 External FLMDn Resistors . . . 22

3.5.2 Condition 1 . . . 22

3.5.3 Condition 2 . . . 23

3.5.4 Condition 5 . . . 24

3.5.5 Condition 6 . . . 25

Chapter 4 Clock generators

. . . 26

4.1 CPU clock. . . 26 4.2 Peripheral clock. . . 26 4.3 Oscillator characteristics . . . 26 4.3.1 Main oscillator . . . 26 4.3.2 Sub-oscillator . . . 27 4.3.3 Internal oscillator . . . 28 4.4 PLL Characteristics. . . 29

Chapter 5 I/O specification

. . . 30

5.1 Port Characteristics . . . 30

5.1.1 Condition settings . . . 30

5.1.2 PgE0 . . . 31

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5.1.4 PgB0 . . . 33

5.1.5 PgA0 . . . 33

Chapter 6 Supply current specification

. . . 34

6.1 Supply current of µPDF70F4000 / µPDF70F4001 / µPDF70F4002. . . 34

6.2 Supply current of µPDF70F3548 / µPDF70F3549 / µPDF70F3550. . . 35

Chapter 7 Peripherals specification

. . . 36

7.1 Reset timing. . . 36 7.2 NMI timing . . . 36 7.3 INTP timing. . . 37 7.4 FLMD0 timing. . . 37 7.5 _DCUTRST timing . . . 37 7.6 Timer timing. . . 38 7.7 CSI timing. . . 40 7.7.1 Master modes . . . 40 7.7.2 Slave mode . . . 46 7.8 UART timing. . . 49 7.9 FCN timing. . . 50 7.10 FlexRay timing. . . 51 7.11 IIC timing . . . 53

7.12 Frequency Output Function (FOUT) . . . 55

7.13 VLVI characteristics . . . 55

7.14 Voltage comparator characteristics. . . 56

7.15 LVI characteristics. . . 57

7.16 A/D Converter characteristics . . . 58

7.16.1 12bit A/D (for ADC channels without S/H functionality) . . . 58

7.16.2 12bit A/D (For channel ADCA0I0-5 when the S/H function is not used) . . . . 59

7.16.3 12bit A/D (When channel S/H function is used) . . . 60

7.16.4 10bit A/D (for ADC channels without S/H functionality) . . . 61

7.16.5 10bit A/D (For channel ADCA0I0-5 when the S/H function is not used) . . . . 62

7.16.6 10bit A/D (When channel S/H function is used) . . . 63

7.16.7 Equivalent circuit . . . 64

7.16.8 ADTRG timing . . . 64

7.17 Key Return. . . 65

Chapter 8 Memory specification

. . . 66

8.1 Code flash specification. . . 66

8.2 Data flash specification . . . 66

8.3 Serial write operation specification. . . 66

Chapter 9 Pinning and package specification

. . . 67

9.1 Pinning specification . . . 67

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Chapter 1 Overview

1.1 Naming

1.1.1 Alternative function pins

Example:

– TAUB0I0, TAUB1I5

– URTE0TX, URTE0RX, URTE1TX, URTE1RX – CSIG0SO, CSIG0SI, CSIG0SC, CSIG0RY

1.1.2 Power supply pins

Example:

– E0VDDn, REG0VSS

If not mentioned otherwise this document neglects suffixes for power supply pins with same functions that can be treated as equal.

Peripheral Prefix Function

name Suffix

Short-cut of macro name

Consecutive number for same peripheral modulea

a) _{This is an option that can be omitted if meaning is obvious} Peripheral Macro pin naming

Consecutive number for same pin namesa

Function Prefix Kind of

supply Suffix

Symbol Consecutive number for _{different functions}a

a) _{This is an option that can be omitted if meaning is obvious} VDD or VSS

Consecutive number for different pins with

same meaninga

Table 1-1 Selection for Functions

Function Explanation

C Core supply

REG Internal regulator supply OSC Oscillator supply

F Flash module supply

E Standard buffer supply (mainly 5V or up to 40Mhz) B Standard buffer supply (mainly 3.3V or beyond 40Mhz) A Analog module supply (e.g. ADC)

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1.2 Pin Groups

1.3 General measurement conditions

1.3.1 AC characteristic measurement condition

AC test input waveform

AC test output waveform

Standard AC test condition is 70%/30% of the applied IO supply voltage (XmVDD) if not otherwise stated in the according AC timing specification of an interface.

AC Test Condition: Ext. Capacitive Load

Symbol Pin group supplied by Related pins / ports

PgE0 E0VDD / E0VSS JP0, P0, _RESET, FLMD0, WAKE, VCPC0IN

PgE1 E1VDD / E1VSS P1, P3, P4

PgB0 B0VDD / B0VSS n.a.

PgOSC OSCVDD / OSCVSS X1, X2

PgA0 A0VDD / A0VSS P10, P11, ADCA0Im

xVSS xVDD .FBTVSFNFOU 7*) NJO 7*- NBY 7*) NJO 7*- NBY xVSS xVDD .FBTVSFNFOU 70) NJO 70- NBY 70) NJO 70- NBY

DUT

Load on test:

C

L

= 50pF

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Chapter 2 Absolute maximum ratings

2.1 Supply voltages

Table 2-1 VDD Data

Parameter Symbol Condition Ratings Unit

System CVDD M2 products only -0.5 ~ 1.6 V

System FVDD -0.5 ~ 6.0 V OSCVDD -0.5 ~ 6.0 V REG0VDD -0.5 ~ 6.0 V REG1VDD -0.5 ~ 6.0 V REG2VDD -0.5 ~ 6.0 V REG3VDD - V Ports E0VDD -0.5 ~ 6.0 V E1VDD -0.5 ~ 6.0 V Port B0VDD n.a. V

ADCA0 A0VREFP -0.3 ~ A0VDD+0.3_-0.3~6.0 V

ADCA0 A0VDD -0.5 ~ 6.0 V

ADCA1 A1VDD n.a. V

A1VREFP n.a. V

Table 2-2 VSS Data

System CVSS M2 products only -0.5 ~0.5 V

System FVSS -0.5 ~0.5 V OSCVSS -0.5 ~0.5 V REG0VSS -0.5 ~0.5 V REG1VSS -0.5 ~0.5 V REG2VSS -0.5 ~0.5 V REG3VSS - V E0VSS -0.5 ~0.5 V Ports E1VSS -0.5 ~0.5 V B0VSS V ADC0 A0VSS -0.5 ~0.5 V A0VREFM -0.3 ~ A0VDD+0.3_-0.3~6.0 V

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2.2 Port voltages

Table 2-3 Port Input voltage

Parameter Pin Group Symbola

a) _{The symbols reflect all supplies within the device series. Therefore not every symbol is available for each} product.

Condition Ratings Unit

Input voltageb

b) _{The characteristics of the alternative-function pins are the same as those of the port pins unless otherwise} specified.

PgE0 V_I0 E0VDD≤5.5 -0.5 ~ E0VDD+0.5 V

PgE1 V_I1 E1VDD≤5.5 -0.5 ~ E1VDD+0.5 V

PgB0 V_I2 B0VDD≤5.5 n.a. V

PgOSC V_I5 OSCVDD≤5.5 -0.5 ~ OSCVDD+0.5 V

PgA0 V_I3 A0VDD+0.3 V

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2.3 Port current

2.4 Capacitance

Table 2-4 High level port output current

Parameter Pin Groupa

a) _{The column reflects all supplies within the device series. Therefore not each pin group is available for each} product.

Symbol Condition Max. spec Unit

High level output current

PgE0

IOH

1 pin of PgE0 -10

mA Power supply of PgE0 -50

PgE1 1 pin of PgE1 -10

Power supply of PgE1 -100

PgA0 1 pin of PgA0 -10

Power supply of PgA0 -25 High level output

current PgA1 IOH

1 pin of PgA1 n.a.

mA Power supply of PgA1 n.a.

High level output

current PgB0 IOH

1 pin of PgB0 n.a.

mA Power supply of PgB0 n.a.

Table 2-5 Low level port output current

Parameter Pin Groupa Symbol Condition Max. spec Unit

Low level output current

PgE0

IOL

1 pin of PgE0 10

mA Power supply of PgE0 50

PgE1 1 pin of PgE1 10

Power supply of PgE1 100

PgA0 1 pin of PgA0 10

Power supply of PgA0 25 Low level output

current PgA1 IOL

1 pin of PgA1 n.a.

mA Power supply of PgA1 n.a.

Low level output

current PgB0 IOL

1 pin of PgB0 n.a.

mA Power supply of PgB0 n.a.

a) _{The column reflects all supplies within the device series. Therefore not each pin group is available for each} product.

Parameter Symbol Condition Max. spec Unit

Input capacitance C_I

f = 1 MHz

0V for non measurement pins

15 pF

Input/Output capacitance C_IO 15 pF

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2.5 Thermal characteristics

This section specifies the absolute maximum limitation of operating and storage temperature.

The device’s functions are not guaranteed outside of the specified maximum temperature ratings.

Table 2-6 Thermal characteristics

Storage temperature T_STG -65 ~150

°C Operating ambient

temperature Ta

(A) grade products -40 ~85

(A1) grade products -40 ~110 (A2) grade products -40 ~125

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Chapter 3 Power supply specification

3.1 Requirements for external power supply

connections

The user has to ensure a low resistive connection of all VSS pins on the PCB. This specification denotes ground supply pins as:

• VSS = OSCVSS = REGnVSS = EnVSS = AnVSS = AnVREM = CVSS = 0V in the further text.

With

• EnVSS = E0VSS = E1VSS

• REGnVSS = REG0VSS = REG1VSS • AnVSS = A0VSS AnVREFM = A0VREFM

The user has to ensure a low resistive connection of all VDD pins to the related power supply. This specification denotes power supply pins as:

• EnVDD, FVDD, REGnVDD, OSCVDDCVDD, AnVDD and AnVREFP. in the further text.

With

• EnVDD = E0VDD = E1VDD

• REGnVDD = REG0VDD = REG1VDD. • AnVDD = A0VDD

• AnVREFP = A0VREFP

• I/OVDD = AnVDD, EnVDD, FVDD, OSCVDD

3.2 Power area definitions

The device consists of the following power areas: • AWO (Always On area)

• ISO0 (Isolated area 0) • ISO1 (Isolated area 1)

The table below lists the related core and port voltage supply of each power area:

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3.3 Power supply groups

For each of the following power supply groups the same voltage must by supplied:

Table 3-1 Power areas supply voltages

Power

Area Supply voltage Related pins

AWO

Core supply REG0VDD, REG0VSS, REG0C

Port Supply E0VDD, E0VSS

Other OSCVDD, OSCVSS_FVDD0

ISO0

Core supply

REG1VDD, REG1VSS, REG1C REG2VDD, REG2VSS, REG2C

Port Supply E1VDD, E1VSS

Other A0VREFP, A0VREFM_{A0VDD, A0VSS}

ISO1

Core supply

REG1VDD, REG1VSS, REG1C REG2VDD, REG2VSS, REG2C CVDD, CVSS

Port Supply n.a.

Other n.a.

Table 3-2 Power supply groups

Power supply

group Related pins

#1 REG0VDD, REG1VDD, FVDD, OSCVDD, E0VDD, E1VDD #4 M1 products: n.a._{M2 products: CVDD}

#5 A0VDD, A0VREFP

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3.4 Supply voltages

Table 3-3 VDD Data

Min Typ Max

System supply voltage FVDD VPOC - 5.5 V

System supply voltage OSCVDD VPOC - 5.5 V

System supply voltage REG0VDD

REG0VDD = REG1VDD

VPOC - 5.5 V

System supply voltage REG1VDD VPOC - 5.5 V

System supply voltage REG2VDD - - - V

System supply voltage REG3VDD - - - V

System supply voltage CVDD M2 products only 1.1 - 1.3 V System supply voltage

slopes AIVS

M2 products;

REG1VDD = 3.0V to 5.5V - - 5.6 V/ms

Port supply voltages E0VDD VPOC - 5.5 V

Port supply voltages E1VDD VPOC - 5.5 V

ADC supply voltages A0VDD 12bit resolution 4.5 - 5.5 V ADC supply voltages A0VDD 10bit resolution VPOC - 5.5 V

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3.4.1 AWO Regulator characteristics

Table 3-4 AWO Regulator characteristics

Min Typ Max

Regulator Output

voltage VRO 1.1 1.2 1.3 V

System supply voltage

slope RAVS 0V to 3.0V - - 1800 V/ms

Capacitance on

REG0C REG0C 3.29 4.7 6.11 µF

Output voltage

stabilization time TRAA

After REG0VDD reaches 3.0V - - 1 ms

After DeepStop mode - - 0.5 ms

REG0VDD _VPOC RAVS TRAA VROMIN VRO REG0VDDVPOC to 5.5V TRAA VROMIN VRO DeepStop Release timing During power-up sequence

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3.4.2 ISO0/ISO1 Regulator characteristics (M1 products)

Table 3-5 ISO0/ISO1 regulator characteristics

Note n=1

3.4.3 Amplifier characteristics (M2 products)

Min Typ Max

Output voltage VROI 1.1 1.2 1.3 V

Capacitance on REGnC REGnC 3.29 4.7 6.11 µF

Voltage slope RIVS 0V to 5.5V - - 5600 V/s

Output voltage

stabilization time TRAI

After REGnVDD reaches 3.0V - - 1 ms

REGnVDD _3.0V

RIVS

TRAI

VROIMIN

VROI

During power-up sequence

REGnVDDVPOC to 5.5V TRAI VROIMIN VROI DeepStop Release timing After DeepStop mode

Min Typ Max

System supply voltage REG1VDD VPOC 5.5 V

Capacitance on CVDD CVDDC For each CVDDa _3.29 _4.7 _6.11 _µF

Voltage slope AIVS 3.0V to 5.5V - - 5.6 V/ms

PTCTL1 stabilization

time TRAI

After REG1VDD reaches 3.0V - - 1 ms

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a) _{Required when using an external power transistor such as 2SD1584 (base connected to PTCTL1)} REG1VDD _3.0V AIVS TRAI PTCTL1 REG1VDDVPOC to 5.5V TRAI PTCTL1 DeepStop Release timing During power-up sequence

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3.4.4 POC characteristics

Table 3-6 POC characteristics

3.4.5 Voltage Comparator characteristics

Table 3-7 VCMP characteristics

Note VDD: REG0VDD

Min Typ Max

Detection voltage VPOC 2.8 2.9 3.0 V

Voltage slope 1 PVS1 0.18 - 1800 V/ms

Voltage slope 2 PVS2 0.0018 - 1800 V/ms

Response time 1 tPTHD

From detect voltage to release of reset signal.

Voltage slope = PVS1, PVS2

- - 2 ms

Response time 2 tPD

From detect voltage to occurence of reset signal

Voltage slope = PVS2

- - 2 ms

VDD minimum width tPW 0.2 - - ms

Min Typ Max

Input voltage range of VCPCnIN VICMP REG0VSS - REG0VDD V

VDD tPW D etect voltage(MAX.) D etect voltage(TYP.) D etect voltage(MIN.) tPTHD tPTHD tPD Pvs1 Pvs2

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3.5 Power-up/-down sequence of external supply

voltages

3.5.1 External FLMDn Resistors

Valid for all conditions described in the following

3.5.2 Condition 1

M1products: RESET is not used

M2 products: RESET, WAKE and PTCTL1 are not used Normal operating mode

Note IOVDD: AnVDD, B0VDD, EnVDD, FVDD, OSCVDD

Min Typ Max

FLMD0 external pull-down resistor R1 82 - - kΩ

FLMD1 external pull-down resistor R2 - 10 - kΩ

Min Typ Max

REG0VDD, REG1VDD, IOVDD (rise) to

CVDD (rise) tR0CON 1 - 10 ms

REG0VDD, IOVDD (rise) to

FLMD0,1(≤VIL) hold time tR0MDH 2 - - ms

FLMD0,1 (≤VIL) to REG0VDD, IOVDD

(fall) tMDR0OF 0 - - ms

CVDD (0V) to REG0VDD, IOVDD (fall) tCR0OF 0 - - ms

REGnVDD IOVDD CVDD (M2) FLMD0 P0_1/FLMD1 3.0V tROCON tROMDH VIL 1.1V tROCOF tMDR0OF VIL 3.0V

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3.5.3 Condition 2

M1products: RESET is used

M2 products: RESET is used; WAKE and PTCTL1 are not used Normal operating mode / Serial programming mode

Note There is no specification for _RESET rise and fall times.

Min Typ Max

REGnVDD, IOVDD (rise) to CVDD (0V)

hold time tR0CH 1 - - ms

CVDD (rise) to _RESET (rise) tCRR 0 - - ms

FLMD0,1 (≥VIH or VIL1) a to

_RESET(≤VIL) (rise) tMDRR 1 - - ms

_RESET (rise) to FLMD0,1(≥VIH or ≤VIL)

hold time tRMDH 1 - - ms

FLMD0,1,MODE0,1(≤VIL) to _RESET

(≥VIH) (fall) setup time tMDRF 0 - - ms

_RESET (fall) to CVDD (fall) tRCF 0 - - ms

CVDD (0V) to REGnVDD, IOVDD (fall) tCR0OF 0 - - ms

_RESET (≤VIL) (fall) to REGnVDD,

IOVDD (fall) hold time tRR0OF 0 - - ms

a) _{In case of BSCAN mode set also the MODE0,1 pins.}

REGnVDD IOVDD CVDD (M2) FLMD0 P0_1/FLMD1 3.0V tMDRR tROMDH VIL 1.1V tCROOF VIL 3.0V _RESET 1.1V VIL tRCF tCRR tR0CH tRMDH VIH VIH tMDRF tRR0OF

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3.5.4 Condition 5

M2 products only. RESET is not used; PTCTL1 is used Normal operating mode

Min Typ Max

PTCTL1 (rise) setup time tR1PTON - - 1 ms

CVDD (rise) byPTCTL1 (rise) tR0CON 1 - 10 ms

FLMD0,1 (≤VIL) to REG0VDD,

REG1VDD, IOVDD (fall) tMDR0OF 0 - - ms

REG0VDD, REG1VDD, IOVDD (fall) to

PTCTL1 (fall) tR1PTOF - - 1 ms

PTCTL1 (fall) to CVDD (fall) tPTCOF 0 - 8 ms

REG0VDD REG1VDD IOVDD CVDD FLMD0 P0_1/FLMD1 3.0V VIL VIL tR0CON 1.1V PTCTL1 tR0MDH tR1PTON 3.0V tPTCOF tMDR0OF tR1PTOF

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3.5.5 Condition 6

M2 products only. RESET is used; PTCTL1 is used

Normal operating mode / Serial programming mode / BSCAN mode

Note There is no specification for _RESET rise and fall times.

Min Typ Max

CVDD (0V) hold time tR0CH - - 1 ms

REG1VDD (rise) to PTCTL1 (rise) setup

time tR1PTON - - 1 ms

REG0VDD, IOVDD (rise) to FLMD0,1

(≤VIL) hold time tR0MDH 1 - - ms

CVDD (rise) to _RESET (rise) tCRR 0 - - ms

FLMD0,1 (VIH or VIL) a to _RESET (rise) tMDRR 1 - - ms

_RESET (rise) to FLMD0,1 (VIH or VIL)

hold time tRMDH 1 - - ms

FLMD0,1,MODE0,1 (≤VIL) a to _RESET

(fall) tMDRF 0 - - ms

_RESET (fall) to REG0VDD, IOVDD (fall) tRR0OF 0 - - ms

REG1VDD (fall) to PTCTL1 (fall) tR1PTOF - - 1 ms

PTCTL1 (fall) to CVDD (fall) tPTCOF 0 - 8 ms

a) _{In case of BSCAN mode set also the MODE0,1 pins.}

REG0VDD REG1VDD IOVDD CVDD FLMD0 P0_1/FLMD1 3.0V VIL VIL 1.1V PTCTL1 tR0MDH tR1PTON 3.0V tPTCOF tR1PTOF _RESET tRR0OF tMDRF tCRR tR0CH VIH VIH tMDRR tRMDH

(26)

Chapter 4 Clock generators

4.1 CPU clock

Table 4-1 CPU clock frequency

4.2 Peripheral clock

Table 4-2 Peripheral clock frequency

4.3 Oscillator characteristics

4.3.1 Main oscillator

A ceramic or crystal resonator can be connected to the main clock input pins as shown in figure 4-1 “Recommended Main Oscillator Circuit”

.

Figure 4-1 Recommended Main Oscillator Circuit

Caution Values of C , C and R and the best setting for MOSCC.AMPSEL[1:0]

Min Typ Max

CPU clock frequency fCPU PLL based - - 80 MHz

SSCG based - - 88.32 MHz

Min Typ Max

Peripheral clock

frequency fPERI - - 48a

a) _{Some peripherals can be operated at 80MHz. Refer to the chapter ‘Clock Selection’ in the UM for} details. MHz X1 X2 C1 C2 Rd internal external

(27)

The main oscillator amplifier gain for the external resonator can be selected by MOSCC.MOSCCAMPSEL[1:0]. Thereby it can be adjusted to support a wide range of frequencies to cope with different external resonators and their external circuitry.

As an example a typical setting for quartz crystals is shown in Table 4-3 “Typical setting of MOSCC.AMPSEL[1:0] for different quartz crystals frequencies”.

Note For details to the setting of MOSCC.MOSCCAMPSEL[1:0] please refer to the

user manual.

(1) Main oscillator charactrisitics

Table 4-4 Main oscillator characteristics

Cautions 1. External clock input is prohibited. 2. General guidance for PCB layout:

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route this circuit close to a signal line with high fluctuating current flow.

• Always make the ground point of the oscillator capacitor the same

potential as REG0VSS and OSCVSS.

• Do not ground the capacitor to a ground pattern with high current flow.

• Do not tap signals from the oscillator.

4.3.2 Sub-oscillator

A crystal resonator can be connected to the sub clock input pins as shown in figure 4-2 “Recommended Sub Oscillator Circuit”

Table 4-3 Typical setting of MOSCC.AMPSEL[1:0] for different quartz crystals frequencies

MOSCC.AMPSEL[ 1:0]

Amplification gain

Typical condition for quartz crystals

00 high 16 < f_MOSC ≤20 MHz

01 medium 8 < f_MOSC ≤ 16 MHz

10 low 4 < f_MOSC≤ 8 MHz

11 very low 4 MHz

Min Typ Max

(28)

.

Figure 4-2 Recommended Sub Oscillator Circuit

Caution Values of C_1s, C_2s and R_ds depend on the used crystal and must be specified

in cooperation with crystal manufacturer.

(1) Sub-oscillator characteristics

4.3.3 Internal oscillator

Table 4-5 Internal oscillator characteristics

XT1 XT2

C1s C2s

Rds internal

external

Min Typ Max

Lowspeed OSC frequency

fRL

• Other than DeepStop mode • DeepStop mode with

PSC0.REGSTP = 0

220.8 240 259.2 kHz

fRLLP • DeepStop mode with _{PSC0.REGSTP = 1} 216 240 264 kHz

Highspeed OSC frequency

fRH

• Other than DeepStop mode • DeepStop mode with

PSC0.REGSTP = 0

7.2 8.0 8.8 MHz

fRHLP • DeepStop mode with _{PSC0.REGSTP = 1} 6.64 8.0 8.8 MHz Highspeed OSC

(29)

4.4 PLL Characteristics

Table 4-6 PLL characteristics

Min Typ Max

Input frequency fxn PLL mode and SSCG mode 4 - 20 MHz

Output frequency fxxn PLL mode 25 - 80 MHz

SSCG mode 22.40 - 88.32 MHz

Lock time TLCKPn PLL mode - - 650 µs

TLCKSn SSCG mode - - 1300 µs

Period jittera

a) _{Not tested in production. Specified by design.} tPJn

Peak to peak, fixed frequency mode, Pr=2

-150 - 150 ps

Long term jittera tLTJn

PLL mode, Peak to peak, term=1µs

f_VCOOUT=160MHz (Pr=2)

(30)

Chapter 5 I/O specification

5.1 Port Characteristics

5.1.1 Condition settings

Some of the conditions mentioned in this chapter can be selected by software. The related register settings are described below:

(1) Input characteristic

The input characteristics can be selected by the registers PIS and PISE with the following coding:

Table 5-1 Input characteristic selection

PISE PIS Reference in

UserManual

Electrical characteristic

0 0 Type 1 CMOSa

a) _{Default setting after reset}

0 1 Type 2 Schmitt2

1 0 Type 3 Schmitt1

(31)

5.1.2 PgE0

Table 5-2 PgE0 characteristics

Min Typ Max

High level input voltage VIH

CMOS 0.7·E0VDD - E0VDD+0.3

V

Schmitt1 0.7·E0VDD - E0VDD+0.3

Schmitt4 (E0VDD=VPOC~3.0) 0.84·E0VDD - E0VDD+0.3 Schmitt4 (E0VDD=3.0~5.5) 0.8·E0VDD - E0VDD+0.3

Low level input voltage VIL

CMOS -0.5 - 0.3·E0VDD

V

Schmitt1 -0.5 - 0.3·E0VDD

Schmitt4 (E0VDD=VPOC~3.0) -0.5 - 0.4·E0VDD Schmitt4 (E0VDD=3.0~5.5) -0.5 - 0.5·E0VDD

High level output voltage VOH IOH = -5mA E0VDD-1.0 - V

IOH = -100µA E0VDD-0.5

-Low level output voltage VOL IOL = 5mA - - 0.4 V

IOL = 100µA - - 0.4

Input hysteresis of Schmit VH

Schmitt1 0.3

-V

Schmitt2 0.3

-Schmitt4 0.1

-Internal pull-up resistor RU 20 40 100 kΩ

Internal pull-down resistor RD 20 40 100 kΩ

High level port output

current IOH Power supply of PgE0 - - -20 mA

Low level port output

current IOL Power supply of PgE0 - - 20 mA

High level input leakage

current ILIH VI = E0VDD - - 0.5 µA

Low level input leakage

current ILIL VI = 0V - - -0.5 µA

High level output leakage

current ILOH VO = E0VDD - - 0.5 µA

Low level output leakage

current ILOL VO = 0V - - -0.5 µA

Output frequency fO Slow mode - - 25 MHz

Fast mode - - 40

Rise time (output) tKRP Slow mode - - 15 ns

Fast mode - - 8 ns

Fall time (output) tKFP Slow mode - - 15 ns

(32)

5.1.3 PgE1

Table 5-3 PgE1 characteristics

Min Typ Max

High level input voltage VIH

CMOS 0.7·E1VDD - E1VDD+0.3

V

Schmitt4 (E1VDD=VPOC~3.0) 0.84·E1VDD - E1VDD+0.3 Schmitt4 (E1VDD=3.0~5.5) 0.8·E1VDD - E1VDD+0.3

Low level input voltage VIL

CMOS -0.5 - 0.3·E1VDD

V

Schmitt4 (E1VDD=VPOC~3.0) -0.5 - 0.4·E1VDD Schmitt4 (E1VDD=3.0~5.5) -0.5 - 0.5·E1VDD High level output voltage VOH IOH = -5mA

a

a)

E1VDD-1.0

-V

IOH = -100µA E1VDD-0.5

-Low level output voltage VOL IOL = 5mA

a _- _- _0.4

V

IOL = 100µA - - 0.4

Input hysteresis of Schmit VH

Schmitt1 0.3

-V

Schmitt2 0.3

-Schmitt4 0.1

-Internal pull-up resistor RU 20 40 100 kΩ

Internal pull-down resistor RD 20 40 100 kΩ

current IOH Power supply of PgE1 - - -150 mA

current IOL Power supply of PgE1 - - 150 mA

current ILIH VI = E1VDD - - 0.5 µA

current ILOH VO = E1VDD - - 0.5 µA

Output frequency fO Slow mode - - 25 MHz

Fast mode - - 40

Rise time (output) tKRP Slow mode - - 15 ns

Fast mode - - 8 ns

Fall time (output) tKFP Slow mode - - 15 ns

(33)

5.1.4 PgB0

PgB0 is not available on V850E2/FG4

5.1.5 PgA0

Table 5-4 PgA0 characteristics

Min Typ Max

High level input voltage VIH CMOS 0.7·AnVDD - AnVDD+0.3 V

Low level input voltage VIL CMOS -0.5 - 0.3·AnVDD V

High level output voltage VOH IOH = -1mA AnVDD-1.0 - - V

IOH = -100µA AnVDD-0.5 -

-Low level output voltage VOL IOL = 1mA - - 0.4 V

IOL = 100µA - - 0.4

current IOH Power supply of PgA0 - - -20 mA

current IOL Power supply of PgA0 - - 20 mA

current ILIH VI = AnVDD - - 0.2 µA

current ILOH VO = AnVDD - - 0.2 µA

Output frequency fO - - 25 MHz

Rise time (output) tKRP - - 15 ns

(34)

(35)

Chapter 6 Supply current specification

6.1 Supply current of µPDF70F4000 / µPDF70F4001 /

µPDF70F4002

Notes 1. The above currents do not include port buffer currents or ADC currents. 2. The currents in run mode include currents for self-programming and

EEPROM emulation.

3. The current of FlexRay is not included in case of CPU frequency = 8MHz. 4. The ‘typical’ specification is for reference only and not a guaranteed value.

The ‘typical’ specification is applicable under the following conditions:

• Ta = 25°C • REGnVDD=FVDD=OSCVDD=EmVDD=AmVDD=AmVREFP=5.0V (n=0-3, m=0-1). • M2 products: CVDD = 1.2V • REGnVSS=OSCVSS=EmVSS=AmVSS=AmVREFM=0V (n=0-3, m=0-1) Item

Powera Conditionb Specification

Unit ISO0 ISO1 8MHz intOSC Main OSC PLL CPU

Freq Peripherals Min. Typ. (A) (A1) (A2)

RUN

mode ON ON ON ON ON 80 WORKING - 91 122 123 124 mA ON ON ON ON ON 80 STOPPED - 53 - - - mA ON ON ON OFF OFF 8 WORKING - 20 38 38 38 mA ON ON ON OFF OFF 8 STOPPED - 16 - - - mA ON OFF ON ON ON 80 WORKING - 75 103 104 105 mA ON OFF ON ON ON 80 STOPPED - 52 - - - mA ON OFF ON OFF OFF 8 WORKING - 18 36 36 36 mA ON OFF ON OFF OFF 8 STOPPED - 16 - - - mA HALT

mode ON ON ON ON ON 80 WORKING - 86 117 118 119 mA ON ON ON ON ON 80 STOPPED - 52 - - - mA ON ON ON OFF OFF 8 WORKING - 19 38 38 38 mA ON ON ON OFF OFF 8 STOPPED - 16 - - - mA STOP

mode ON ON OFF OFF OFF - STOPPED - 0.7 19 20 22 mA ON OFF OFF OFF OFF - STOPPED - 0.6 19 19 21 mA DEEPSTOP

mode OFF OFF OFF OFF OFF - STOPPED - 0.06 0.86 0.88 1.1 mA OFF OFF ON OFF OFF - STOPPED - 0.60 2.1 2.3 2.5 mA

a) _{The AWO is always ON.} b) _{The 240kHz IntOSC is always ON.}

(36)

6.2 Supply current of µPDF70F3548 / µPDF70F3549 /

µPDF70F3550

Notes 1. The above currents do not include port buffer currents or ADC currents.

2. The currents in run mode include currents for self-programming and EEPROM emulation.

3. The ‘typical’ specification is for reference only and not a guaranteed value. The ‘typical’ specification is applicable under the following conditions:

• Ta = 25°C • REGnVDD=FVDD=OSCVDD=EmVDD=AmVDD=AmVREFP=5.0V (n=0-3, m=0-1). • M2 products: CVDD = 1.2V • REGnVSS=OSCVSS=EmVSS=AmVSS=AmVREFM=0V (n=0-3, m=0-1) Item

Powera Conditionb Specification

Unit ISO0 ISO1 8MHz intOSC Main OSC PLL CPU

Freq Peripherals Min. Typ. (A) (A1) (A2)

RUN

mode ON ON ON ON ON 80 WORKING 75 103 104 105 mA ON ON ON ON ON 80 STOPPED 50 - - - mA ON ON ON OFF OFF 8 WORKING 20 38 38 38 mA ON ON ON OFF OFF 8 STOPPED 16 - - - mA ON OFF ON ON ON 80 WORKING 66 93 93 94 mA ON OFF ON ON ON 80 STOPPED 49 - - - mA ON OFF ON OFF OFF 8 WORKING 18 36 36 36 mA ON OFF ON OFF OFF 8 STOPPED 16 - - - mA HALT

mode ON ON ON ON ON 80 WORKING 70 97 98 99 mA ON ON ON ON ON 80 STOPPED 48 - - - mA ON ON ON OFF OFF 8 WORKING 19 38 38 38 mA ON ON ON OFF OFF 8 STOPPED 16 - - - mA STOP

mode ON ON OFF OFF OFF - STOPPED 0.7 19 20 22 mA ON OFF OFF OFF OFF - STOPPED 0.6 19 19 21 mA DEEPSTOP

mode OFF OFF OFF OFF OFF - STOPPED 0.06 0.86 0.88 1.1 mA OFF OFF ON OFF OFF - STOPPED 0.60 2.1 2.3 2.5 mA

a) _{The AWO is always ON.} b) _{The 240kHz IntOSC is always ON.}

(37)

Chapter 7 Peripherals specification

7.1 Reset timing

7.2 NMI timing

Min Typ Max

RESET input High level width tWRSH Highspeed OSC is operating 450 - - ns Highspeed OSC is stopped 4.7 - - µs RESET input Low level width tWRSL Highspeed OSC is operating 450 - - ns Highspeed OSC is stopped 4.7 - - µs

Min Typ Max

NMI input High level width tWNIH 300 - - ns

NMI input Low level width tWNIL 300 - - ns

tWRSH tWRSL

_RESET

tWKRH tWKRL

(38)

7.3 INTP timing

7.4 FLMD0 timing

7.5 _DCUTRST timing

Min Typ Max

INTPn input High level width tWITH 300 - - ns

INTPn input Low level width tWITL 300 - - ns

Min Typ Max

FLMD0 input High level width tWMDH 300 - - ns

FLMD0 input Low level width tWMDL 300 - - ns

FLMD0 external pull down resistor R_FLMD0 82 - - kΩ

tWITH tWITL

INTPn

tWMDH tWMDL

FLMD0

Min Typ Max

_DCUTRST input High level width tWRH 450 - - ns

_DCUTRST input Low level width tWTRL 450 - - ns

(39)

7.6 Timer timing

Table 7-1 Timer timing

Min Typ Max

TAUAnI input High level

width tTAIH n=0 a,b - - ns

TAUAnI input Low level

width tTAIL n=0 a,b - - ns

TAUBnI input High level

width tTBIH n=1 a,b

a) _{With digital noise filter enabled: 2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in Noise} filter macro. More than 1 PCLK width of Timer macro must be kept regarding DNF pass through pulse width. b) _{With digital noise filter disabled: 1xtSYNC+20 ( tSYNC: 1 PCLK of Timer macro)}

- - ns

TAUBnI input Low level

width tTBIL n=0 a,b - - ns

TAUJnI input High level

width tTJIH n=0,1 300 - - ns

width tTJIH 4.7 - - µs

width tTJIH b - - ns

TAUJnI input Low level

width tTJIL n=0,1 300 - - ns

width tTJIL 4.7 - - µs

width tTJIL b - - ns

TAUAnO output cycle tTACYK n=0 - - 20 MHz

TAUBnO output cycle tTBCYK n=1 - - 20 MHz

TAUCnO output cycle tTCCYK n=2-7 - - 20 MHz

TAUJnO output cycle tTJCYK n=0,1 - - 20 MHz

TAPAnESO input High level

width tWESH n=0 300 - - ns

TAPAnESO input Low level

width tWESL n=0 300 - - ns

ENCAnTmIN high level

width tWENmH n=0, m=A,B,Z a,b - - ns

ENCAnTmIN low level width tWENmL n=0, m=A,B,Z a,b - - ns

ENCAnTINm high level

width tWENmH n=0, m=0-1 a,b - - ns

(40)

TAUAnI tTAIH tTAIL TAUBnI tTACYK TAUJnI tWESH tWESL TAPAnESO tTBIH tTBIL tTJIH tTJIL tTBCYK tTCC YK tTJCYK TAUAnO TAUBnO TAUJnO TAUCnO tWENmH tWENmL ENCAnTmIN ENCAnTINm

(41)

7.7 CSI timing

7.7.1 Master modes

(1) CSIG timing

Table 7-2 CSIG timing (Master mode)

Note n: Number of macro instances. Refer to the User Manual for the detailed

specification.

Min Typ Max

Macro Operation clock cycle

time tKCYGn 20.8 - - ns

CSIGnSC cycle time tKCYMGn 100 - - ns

CSIGnSC high level width tKWHMGn 0.5 · tKCYMGn-10 - - ns

CSIGnSC low level width tKWLMGn 0.5 · tKCYMGn-10 - - ns

CSIGnSI setup time

(vs. CSIGnSC ) tSSIMGn CSIGnSC@PDSC=1 30 - - ns

CSIGnSI setup time

(vs. CSIGnSC ) tSSIMGn CSIGnSC@PDSC=0 38 - - ns

CSIGnSI hold time

(vs. CSIGnSC) tHSIMGn 0 - - ns

CSIGnSO output delay

(vs. CSIGnSC) tDSOMGn - - 7 ns

CSIGnRYI setup time

(vs. CSIGnSC) tSRYIGn

CSIGnCTL1.CSIGnSIT=x

CSIGnCTL1.CSIGnHSE=1 2 · tKCYGn+25 - - ns CSIGnRYI High level width tWRYIGn CSIGnCTL1.CSIGnHSE=1 tKCYGn- 5.0 - - ns

(42)

(2) CSIH timing master mode

Table 7-3 CSIH timing (Master mode)

Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed

specification.

2. CSSETUP: Value of CSIHnCFG0-7.CSIHnSP0-7[3:0]

3. CSHOLD: Value of CSIHnCFG0-7.CSIHnHD0-7[3:0]

4. CSIDLE: Value of CSIHnCFG0-7.CSIHnID0-7[2:0]

Min Typ Max

time tKCYHn 20.8 - - ns

CSIHnSC cycle time tKCYMHn 100 - - ns

CSIHnSC high level width tKWHMHn 0.5 · tKCYMHn-10 - - ns

CSIHnSC low level width tKWLMHn 0.5 · tKCYMHn-10 - - ns

CSIHnSI setup time

(vs. CSIHnSC ) tSSIMHn

CSIHnSC@PDSC=1 30 - - ns

CSIHnSC@PDSC=0 38 - - ns

CSIHnSI hold time

(vs. CSIHnSC) tHSIMHn 0 - - ns

CSIHnSO output delay

(vs. CSIHnSC) tDSOMHn - - 7 ns

CSIHnRYI setup time

(vs. CSIHnSC) tSRYIHn

CSIHnCTL1.CSIHnSIT=x

CSIHnCTL1.CSIHnHSE=1 2 · tKCYHn+25 - - ns CSIHnRYI High level width tWRYIHn CSIHnCTL1.CSIHnHSE=1 tKCYHn- 5.0 - - ns CSIHnCSS0-7 inactive

width tWSCSBHn

CSIDLE ×

tKCYMHn - 5.0 - - ns CSIHnCSS0-7 setup time

( vs. CSIHnSC )

tSSCSBHn0 CSIHnCTL1.CSIHnDAP=0 _tKCYMHn-5.0CSSETUP × - - ns tSSCSBHn1 CSIHnCTL1.CSIHnDAP=1 (CSSETUP + 0.5 ) ×_tKCYMHn-5.0 - - ns

CSIHnCSS0-7 hold time ( vs. CSIHnSC )

tHSCSBHn0 CSIHnCTL1.CSIHnSIT=0 _tKCYMHn-10.0CSHOLD × - - ns tHSCSBHn1 CSIHnCTL1.CSIHnSIT=1 (CSSHOLD + 0.5) ×_tKCYMHn-5.0 - - ns

(43)

(3) Timing diagrams

SCKO / SI / SO

CSIG ( CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0 / 0 or 1 / 1 ) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0 /0 or 1/1 )

CSIG( CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1 / 0 or 0 / 1) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/ 0 or 0/ 1 )

tKCYGn tKCYMGn tKWLMGn tKWLMHn Clock CSIGnSC CSIGnSI CSIGnSO tKCYHn tKCYMHn tKW HMGn tKW HMHn tD SOMGn tD SOMHn tHSIMGn tHSIMHn tSSIMGn tSSIMHn CSIHnSC CSIHnSO CSIHnSI tKCYGn tKCYMGn tKWHMGn tKWHMHn Clock CSIGnSC CSIGnSI CSIGnSO tKCYHn tKCYMHn tKW LMGn tKW LMHn tDSOMGn tDSOMHn tHSIMGn tHSIMHn tSSIMGn tSSIMHn CSIHnSC CSIHnSO CSIHnSI

(44)

RYI

CSIGnCTL1 : CSIGnHSE=1, CSIGnCTL1 : CSIGnSIT = 0 ) CSIHnCTL1 : CSIHnHSE=1, CSIHnCTL1 : CSIHnSIT = 0 )

CSIG (CSIGnCTL1 :CSIGnCKR= 0) CSIH (CSIHnCFGm:CSIHnCKPm= 0)

CSIG (CSIGnCTL1 :CSIGnCKR= 1) CSIH (CSIHnCFGm:CSIHnCKPm= 1) tKCYGn tSRYIGn Clock CSIGnSC CSIGnRYI tKCYHn tSRYIHn CSIHnSC CSIHnRYI tWRYIGn tWRYIHn Clock CSIGnSC CSIGnRYI CSIHnSC CSIHnRYI tKCYGn tKCYHn tSRYIGn tSRYIHn tWRYIGn tWRYIHn

(45)

CSSn CSIHnCFGm:CSIHnCKPm= 0,CSIHnCFGm:CHIHnDAPm= 0 CSIHnCFGm:CSIHnCKPm= 0,CSIHnCFGm:CHIHnDAPm= 1 Clock tKCYHn CSIHnSC CSIHnCSS0-7 tSSCSBHn0 CSIHnSO Clock tKCYHn CSIHnSC CSIHnCSS0-7 tSSCSBHn1 CSIHnSO tKCYMHn CSSETUP x 0.5x tKCYMHn

(46)

CSIHnCTL1 : CSIHnSIT=0, CSIHnCFGm: CSIHnCKPm= 0,CSIHnCFGm: CHIHnDAPm= 0

CSIHnCTL1 : CSIHnSIT=1, CSIHnCFGm: CSIHnCKPm= 0,CSIHnCFGm: CHIHnDAPm= 0 Clock tKCYHn CSIHnSC CSHnCSS0-7 tHSCSBHn0 Clock tKCYHn CSIHnSC CSHnCSS0-7 tHSCSBHn1 tKCYMHn CSHOLD x tKCYMHn 0.5 x

(47)

7.7.2 Slave mode

(1) CSIG timing slave mode

Table 7-4 CSIG timing (Slave mode)

Note n: Number of macro instances. Refer to the User Manual for the detailed

specification.

(2) CSIH timing slave mode

Table 7-5 CSIH timing (Slave mode)

Note n: Number of macro instances. Refer to the User Manual for the detailed specification.

Min Typ Max

time tKCYGn 20.8 - - ns

CSIGnSC cycle time tKCYSGn 200 - - ns

CSIGnSC high level width tKWHSGn 0.5 · tKCYSGn-10 - - ns

CSIGnSC low level width tKWLSGn 0.5 · tKCYSGn-10 - - ns

CSIGnSI setup time

(vs. CSIGnSC ) tSSISGn 20 - - ns

CSIGnSI hold time

(vs. CSIGnSC) tHSISGn tKCYGn+5.0 - - ns

SO output delay (vs SCKI) tDSOSGn - - 35 ns

CSIGnRYO output delay tSRYOGn - - 35 ns

_CSIGnSSI setup time (vs

CSIGnSC) tSSSISGn 0.5 · tKCYSn-5.0 - - ns

_CSIGnSSI hold time (vs

CSIGnSC) tHSSISGn tKCY+5.0 - - ns

Min Typ Max

time tKCYHn 20.8 - - ns

CSIHnSC cycle time tKCYSHn 200 - - ns

CSIHnSC high level width tKWHSHn 0.5 · tKCYSHn-10 - - ns

CSIHnSC low level width tKWLSHn 0.5 · tKCYSHn-10 - - ns

CSIHnSI setup time

(vs. CSIHnSC ) tSSISHn 20 - - ns

CSIHnSI hold time

(vs. CSIHnSC) tHSISHn tKCYHn+5.0 - - ns

SO output delay (vs SCKI) tDSOSHn - - 35 ns

CSIHnRYO output delay tSRYOHn - - 35 ns

CSIHnSSI setup time

(vs. CSIHnSC) tSSSISHn 0.5 · tKCYSn-5:0 - - ns

CSIHnSSI hold time

(48)

(3) Timing diagrams

SCKO / SI / SO

CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/0 or 1/1) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/0 or 1/1)

CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/0 or 0/1) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/0 or 0/1)

tKCYGn tKCYSGn tKWLSGn tKWLSHn Clock CSIGnSC CSIGnSI CSIGnSO tKCYHn tKCYSHn tKWHSGn tKWHSHn tD SO SG n tD SO SHn tHSISGn tHSISHn tSSISGn tSSISHn CSIHnSC CSIHnSO CSIHnSI tKCYGn tKCYSGn tKWHSGn tKWHSHn Clock CSIGnSC CSIGnSI CSIGnSO tKCYHn tKCYSHn tKWLSGn tKWLSHn tD SO SG n tD SO SHn tHSISGn tHSISHn tSSISGn tSSISHn CSIHnSC CSIHnSO CSIHnSI

(49)

RYO

CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/0) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/0)

CSIGnSC CSIGnRYO CSIHnSC CSIHnRYO tSRYOGn tSRYOHn CSIGnSC CSIGnRYO CSIHnSC CSIHnRYO tSRYOGn tSRYOHn CSIGnSC CSIGnRYO CSIHnSC CSIHnRYO CSIHnTIC tSRYOGn tSRYOHn CSIGnSC CSIGnRYO CSIHnSC CSIHnRYO tSRYOGn tSRYOHn

(50)

SSI:

CSIG (CSIGnCTL1 :CSIGnSSE=1, CSIGnCTL1 : CSIGnCKR,/ CSIGnCFG0 : CHIGnDAP0 = 0/0 or 1/1)

CSIH (CSIHnCTL1 : CSIHnSSE=1, CSIHnCFGm : CSIHnCKPm / CSIHnCFGm : CHIHnDAPm = 0/0 or 1/1)

CSIG (CSIGnCTL1 :CSIGnSSE=1, CSIGnCTL1 : CSIGnCKR,/ CSIGnCFG0 : CHIGnDAP0 = 1/0 or 0/1 ) n=0, 4

CSIH (CSIHnCTL1 : CSIHnSSE=1, CSIHnCFGm : CSIHnCKPm / CSIHnCFGm : CHIHnDAPm = 1/0 or 0/1)

7.8 UART timing

CSIGnSC

CSIGnSO

tSSSISGn

tSSSISHn t_tHSSISHnHSSISGn

CSIHnSC CSIHnSO _CSIGnSSI _CSIHnSSI Hi-Z CSIGnSC CSIGnSO tSSSISGn tSSSISHn tHSSI SGn tHSSI SHn CSIHnSC CSIHnSO _CSIGnSSI _CSIHnSSI Hi-Z

(51)

7.9 FCN timing

Min Typ Max

Transfer rate - - 1 Mbps

Internal delay time tINTDEL - - 37.5 ns

CAN Node delay time tNODE tCYCLE = 62.5ns - - 100 ns

FCnRX pin ( Receive data ) FCnTX pin ( Transfer data ) FCnTX pin FCnRX pin

Image of Internal delay time

Output delay time (tOUTPUT)

Input gate delay time (tGATE)

t

output

V850E2/Fx4

t

GATE

CAN node delay time (tNODE) = INPUT delay time (tinput) + Output delay time (toutput)

Internal delay time (tINTDEL) = Internal gate delay time (tGATE) + Output delay time (toutput)

t

CYCLE

t

INPUT

= t

GATE

+ t

CYCLE

CAN macro

Input delay time (tINPUT)

(52)

7.10 FlexRay timing

Min Typ Max

Transfer rate - - 10 Mbps

Node Output Delay tOUTPUT FLX0TXDA, FLX0TXDB, - - 25 ns

FLX0TXENA, FLX0TXENB -

-Node Input Delay tINPUT FLX0RXDA, FLX0RXDB - - 10 ns

I/O Port I/O Buf

I/O Port I/O Buf Pxx/TXDx

Pxx/RXDx FRTXDx

FRRXDx eray_sclk

(internal system clock)

Node Input Delay D Q

D Q FlexRay macro uCOM device with FlexRay macro

Node Output Delay

TXDx* FRSCLK (internal clock) FRTXDx (macro output) (chip output) RXDx* (chip input) FRRXDx tinput touput

(53)

Port Name Condition Ratings Unit

Min Typ Max

FLX0TXENA FLX0TXENB

dTxEN_RISE-FALL Cload=25pF, measured at 20-80% E1VDD - - 9 ns

dCCTxEN01 - - 25 ns

dCCTxEN10 - - 25 ns

FLX0TXDA FLX0TXDB

dCCTxAsym measured at 50% E1VDD - - 2.45 ns

dCCTxDRISE25 + dCCTxDFALL25

Cload=25pF, measured at 20-80% E1VDD - - 9 ns

Cload=10pF, measured at 20-80% E1VDD

at the end of a 50ohm, 1ns microstripline - - 9 ns

dCCTxD01 - - - 25 ns dCCTxD10 - - - 25 ns FLX0RXDA FLX0RXDB dCCRxAsmAccept measured at 50% of E1VDD

Input signal: Cload=25pF, 6.5ns (20-80% E1VDD) - - 5.5 ns C_CCRxD - - - 10 pf uLogic_1 - 35 - 70 % uLogic_0 - 30 - 65 % dCCRxD01 - - - 10 ns dCCRxD10 - - - 10 ns

(54)

7.11 IIC timing

Table 7-6 Normal mode

Min Typ Max

SCL clock period fCLK 0 100 kHz

Bus free time (between stop condition

and start condition) tBUF 4.7 - - µs

Start/Restart Hold time (New clock pulse

is generated after this hold time as a master.)

tHD:STA 4 - - µs

SCL clock low state hold time tLOW 4.7 - - µs

SCL clock high state hold time tHIGH 4 - - µs

Setup time for start/restart condition tSU:STA 4.7 - - µs

Data hold time tHD:DAT CBUS compatible 5 - - µs

IIC bus 0 - - µs

Data setup time tSU:DAT 250 - - ns

Rising transition time of SDA or SCL tR - - 1000 ns

Falling transition time of SDA or SCL tF - - 300 ns

Setup time of stop condition tSU:STO 4 - - µs

(55)

Table 7-7 Fast mode

Notes 1. P: Stop condition Notes 1. S: Start condition Notes 1. Sr: Restart condition

Min Typ Max

SCL clock period fCLK 0 - 400 kHz

Bus free time (between stop condition

and start condition) tBUF 1.3 - - µs

Start/Restart Hold time (New clock pulse

is generated after this hold time as a master.)

tHD:STA 0.6 - - µs

SCL clock low state hold time tLOW 1.3 - - µs

SCL clock high state hold time tHIGH 0.6 - - µs

Setup time for start/restart condition tSU:STA 0.6 - - µs

Data hold time tHD:DAT IIC bus 0 - 0.9 µs

Data setup time tSU:DAT 100 - - ns

Rising transition time of SDA or SCL tR 20+0.1Cb - 300 ns

Falling transition time of SDA or SCL tF 20+0.1Cb - 300 ns

Setup time of stop condition tSU:STO 0.6 - - µs

Noise elimination width tSP 0 - 50 ns

Bus capacitance Cb - - 400 pF SCL0 P

t

SU: STA

t

HD: STA

t

LOW

t

HI GH

t

BUF SDA0

t

SP

t

R

t

HD: DAT

t

F

t

SU: DAT S

t

HD: STA Sr P

t

SU: STO

(56)

7.12 Frequency Output Function (FOUT)

Table 7-8 Frequency Output Function (FOUT)

7.13 VLVI characteristics

Table 7-9 VLVI characteristics

Min Typ Max

CSCXFOUTP output cycle tFO 50 - - ns

CSCXFOUTP high level width tWKHFO tFOUT / 2 - 10 - - ns

CSCXFOUTP low level width tWKLFO tFOUT / 2 - 10 - - ns

CSCXFOUTP rise time tKRFO - - 10 ns

CSCXFOUTP fall time tKFFO - - 10 ns

Min Typ Max

Detection voltage VRAMHF 1.8 1.9 2.0 V

Voltage slope1 Rvs1 0.18 - 1800 V/ms

Voltage slope2 Rvs2 0.0018 - 1800 V/ms

Response timea

a) _{From detection voltage to setting of VLVF bit (VLVF.bit0)}

tRAMHD - - 2 ms CSCXFOUT tWKHFO tFO tWKLFO tKRFO tKFFO VDD Detectvoltage(MAX.) Detectvoltage(TYP.) Detectvoltage(MIN.) Rvs1 Rvs2

(57)

7.14 Voltage comparator characteristics

Min Typ Max

VCMP current IVCMP - 100 150 µA

Threshould voltage (rise) VCMPR 1.745 1.780 1.815 V

Threshould voltage (fall) VCMPF 1.645 1.680 1.715 V

Voltage slope VCVS - - 50 mV/µs

Detection time tVCMPD - - 2 µs

Stabilization time tVCMPST VCMP operation readyness after _{VCPC0OEn is set to 1} - - 2 ms

VCPCnIN VCMPF(MIN.) tVCMPD VCMPR (MAX.) tVCMPD VCPCnOUT n=0,1 VCMPR(TYP.) VCMPR(MIN.) VCMPF(TYP.) VCMPF(MAX.)

(58)

7.15 LVI characteristics

Table 7-10 LVI characteristics

Min Typ Max

Detection voltage VLVI0 LVICNT.LVICNT[2:0]=001_B 3.9 4.0 4.1 V VLVI1 LVICNT.LVICNT[2:0]=010_B 3.6 3.7 3.8 V VLVI2 LVICNT.LVICNT[2:0]=011_B 3.4 3.5 3.6 V Voltage slope1 LVS1 0.18 - 1800 V/ms Voltage slope2 LVS2 0.0018 - 1800 V/ms Response time tLD - - 2.0 ms VDD minimum width tLW 2 - - ms

Stabilization time tLVIST LVICNT0,1 is set to 1, then LVI is _{ready to operate} - - 350 µs

VDD tLW D etect voltage(MAX.) D etect voltage(TYP.) D etect voltage(MIN.) tLD tLD LVS1 LVS2

(59)

7.16 A/D Converter characteristics

7.16.1 12bit A/D (for ADC channels without S/H functionality)

Table 7-11 12bit A/D

Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed specification.

2. m: Number of channels. Refer to the User Manual for the detailed specification.

Min Typ Max

Resolution RESn 12 12 12 bit

Total conversion time TCONn 1.5 - 10 µs

Overall errora

a) _{The specification does not include the quantization error.}

TOEn - - ±6.0 LSB

Non-liniarity errora _ILEn _- _- _±2.5 _LSB

Differencial liniarity errora _DLEn _- _- _±1.5 _LSB

Zero scale errora _ZSEn _- _- _±5.0 _LSB

Full scale errora _FSEn _- _- _±5.0 _LSB

Analog input voltagea _VAIN _AnVREFM _AnVREFP _V

Power on stabilization timeb

b) _{‘Power on’ refers to} - setting ADCAnGPS = 1

- - 1 µs

AnVDD current AIDDn

ADAnBPC=0, withDiagnosis

function - 4.0 6.3 mA

ADAnBPC=0, w/o Diagnosis

ADAnBPC=1, with Diagnosis

ADAnBPC=1, w/o Diagnosis

AIDDnPD Power down - 1 - µA

AnVREFP current AIREFn - 650 - µA

Conversion result by Diagnosis functionc

c) _{The values given do not include influence of injected current}

TESHn AnVDD was converted 4015 - 4095 LSB

TESHLn3 2/3 AnVDD was converted 2691 2731 2771 LSB TESHLn2 1/2 AnVDD was converted 2018 2048 2078 LSB TESHLn1 1/3 AnVDD was converted 1325 1365 1405 LSB

(60)

7.16.2 12bit A/D (For channel ADCA0I0-5 when the S/H function is

not used)

Table 7-12 12bit A/D (When channel Sample & Hold function is not used)

Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed

specification.

2. m: Number of channels. Refer to the User Manual for the detailed

specification.

Min Typ Max

Resolution RES0SN 12 12 12 bit

Total conversion time TCON0SN 1.5 - 10 µs

Overall errora

a) _{The specification does not include the quantization error.}

TOE0SN - - ±6.0 LSB

Non-liniarity errora _ILE0SN _- _- _±2.5 _LSB

Differencial liniarity errora _DLE0SN _- _- _±1.5 _LSB

Zero scale errora _ZSE0SN _- _- _±5.0 _LSB

Full scale errora _FSE0SN _- _- _±5.0 _LSB

Analog input voltagea _VAIN0SN _A0VREFM _- _A0VREFP _V

Power on stabilization timeb

b) _{‘Power on’ refers to} - setting ADCAnGPS = 1

- - 1 µs

A0VDD current AIDD0SN

ADA0BPC=0, withDiagnosis

ADA0BPC=0, w/o Diagnosis

ADA0BPC=1, with Diagnosis

ADA0BPC=1, w/o Diagnosis

AIDD0SNPD Power down - 1 - µA

A0VREFP current AIREF0SN - 650 - µA

Conversion result by Diagnosis functionc

c) _{The values given do not include influence of injected current}

TESH0SN A0VDD was converted 4015 - 4095 LSB TESHL0SN3 2/3 A0VDD was converted 2691 2731 2771 LSB TESHL0SN2 1/2 A0VDD was converted 2018 2048 2078 LSB TESHL0SN1 1/3 A0VDD was converted 1325 1365 1405 LSB

V850E2/FG4. Data Sheet. 32-bit Single-Chip Microcontroller. µpd70f3550. µpd70f4002. Cover. Renesas Electronics

V850E2/FG4

32-bit Single-Chip Microcontroller

µPD70F3548

µPD70F3549

µPD70F3550

µPD70F4000

µPD70F4001

µPD70F4002

dfgdfg

Dat

a

Sheet

32

Cover

Notice

Regional Information

Notes for CMOS Devices

Table of contents

Chapter 1

Overview

Chapter 2

Absolute maximum ratings

Chapter 3

Power supply specification

Chapter 4

Clock generators

Chapter 5

I/O specification

Chapter 6

Supply current specification

Chapter 7

Peripherals specification

Chapter 8

Memory specification

Chapter 9

Pinning and package specification

Chapter 1 Overview

1.1 Naming

1.1.1

Alternative function pins

1.1.2

Power supply pins

1.2 Pin Groups

1.3 General measurement conditions

1.3.1

AC characteristic measurement condition

DUT

Load on test:

C

= 50pF

Chapter 2 Absolute maximum ratings

2.1 Supply voltages

2.2 Port voltages

2.3 Port current

2.4 Capacitance

2.5 Thermal characteristics

Chapter 3 Power supply specification

3.1 Requirements for external power supply

connections

3.2 Power area definitions

3.3 Power supply groups

3.4 Supply voltages

3.4.1

AWO Regulator characteristics

3.4.2

ISO0/ISO1 Regulator characteristics (M1 products)

3.4.3

Amplifier characteristics (M2 products)

3.4.4

POC characteristics

3.4.5

Voltage Comparator characteristics

3.5 Power-up/-down sequence of external supply

voltages

3.5.1

External FLMDn Resistors

3.5.2

Condition 1

3.5.3