State of the Art in Microelectronics Miniaturization and Integration

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State of the Art in Microelectronics

Miniaturization and Integration

Microelectronics for

Particle Detectors

A. Marchioro

CERN, Div. PH

1211 Geneva 23, Switzerland

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Overview

Motivations: i.e. the talk’s message:

– Experiments require systems, not chips

Brief intro on technology perspectives

– History

– Technologies for SoC

– Advanced Devices for Billion transistor chips

Opportunities:

– SoCs for gas detectors

– SoCs for trackers

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MOTIVATIONS

-

History of

m

Electronics for HEP vs Commercial

-

Areas with potential for growth

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Microelectronics in HEP

1985 to 1995 - Generation 0 :

– 2u down to 1.0 u

– Proofs of concept

– First dedicated ASICs for strip detectors

» Low-noise charge amplifiers

– First simple digital chips

1995 to 2005 – Generation 1:

– 0.8um down to 130nm

– Front-end ASICs with analog/digital pipelines

» First complex pixel chips

– Radiation issues (a very hard problem!)

– First monolithics (MAPS etc.)

2005 onwards:

– 130 nm and below

– Complex SoC

– Intelligent detectors

» Capable of performing significant local processing » But the brain is in the electronics, sorry…

– System optimized for (integration) cost

– High density interconnect

» Stacks of chips or hybrid chip-detectors

1980

1985

1990

1995

2000

2005

2010

2015

i286, 1.5 um, 130K tr., 6 MHz i386, 1.5 um, 275K tr., 16 MHz i486, 1.0 um, 1.2M tr., 25 MHz PentPro, 0.6 um, 5.5M tr., 200 MHz P4, 0.18 um, 42M tr., 1.5 GHz PentiumD, 65 nm, 291M tr., 3.2 GHz iCore, 32 nm, 1.2B tr., 3.8 GHz …

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Microelectronics in HEP

1985 to 1995 - Generation 0 :

– 2u down to 1.0 u

– Proofs of concept

– First dedicated ASICs for strip detectors

» Low-noise charge amplifiers

– First simple digital chips

1995 to 2005 – Generation 1:

– 0.8um down to 130nm

– Front-end ASICs with analog/digital pipelines

» First complex pixel chips

– Radiation issues (a very hard problem!)

– First monolithics (MAPS etc.)

2005 onwards:

– 130 nm and below

– Complex SoC

– Intelligent detectors

» Capable of performing significant local processing » But the brain is in the electronics, sorry…

– System optimized for (integration) cost

– High density interconnect

» Stacks of chips or hybrid chip-detectors

A. Marchioro - MPGD2013

5 1980

1985

1990

1995

2000

2005

2010

2015

Mobira Senator, analog, 9800 gr

Nokia Technophone 105, analog, 5500gr, Cityman 100, analog, 500 gr 1610, 2210, first GSM 900, 230 gr, 3310, GSM, 130 gr 8800, GMS, WAP, camera, 130 gr

iPhone 7 , 4G, WiFi, GB memories, full OS, camera, email, video, …

Phones Timeline

iPhone 3GS , 3G, WiFi, GB memories, full OS, camera, email, video, …

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System Complexity – ADSL Example

CRC & RS Encoders Interleaver Convolutional Encoders Symbol Mapping IFFT Cyclic Prefix CRC & RS Decoders De-interleaving Viterbi Decoder FFT Equalizer FFT Prefix Remove Time Domain Equalizer Symbol recovery A na log FE A/D D/A POTS Splitter Amp Amp Adapter

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Why do you need microelectronics?

Functionality

– Requirements for new (large) detectors can only be

fulfilled by Application Specific Ics

» Example: no way to buy a ready-made Tracker

RH

– No choice other than advanced or modified tech ASICs

– COTS not easily qualified for usage

Cost:

– HEP instrumentation has not made the transition to

“commodity” detectors, everything is hand-made, design

is for performance and not (really) for cost, systems are

not conceived for manufacturability, just for function

or/and performance

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Potential for improvements

FE: Low

» intrinsic speed or resolution of detectors is not expected to improve dramatically

» FE circuits close to intrinsic noise margins

» CMOS tech evolution is not going to improve analog (actually probably worse, see later)

» Only 3D integration can change the game

A/D Conversion: Medium to Hih

» conversion energy is still being improved, new architectures introduced, digital helps.

Caveat: many companies make ADC IPs, do not design ADC, buy them!

Digital signal processing: High to very high

» Little or no “signal processing” is done today in HEP (shaper is analog)

» Some laudable attempt in the “Altro” project (pedestal correction, tail cancelation etc.)

» Much more to be done

Data Processing (i.e. Feature Extraction): Huge

» Little intelligence in chips: lots of raw (and meaningless!) data shipped out at the cost

embedded BW, power and of expensive links

» Trigger (i.e. pattern recognition) opportunities

» Feature extraction could easily be done now

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WHAT TO EXPECT FROM ADVANCES IN TECHNOLOGY

-

Advanced CMOS

-

A flavor of the problems for making nano-transistors

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How many more generations?

“

The end of the planar FET is close, but perhaps one

or two generations can be added if newer transistors

can be made, for example the ‘FINFET’”

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CMOS Technology Roadmap

Fr

om

ITRS

2

01

1

11 There is no doubt that industry will be well ahead

of the requirements from the HEP community,

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Technologies used in ISSCC papers

0.0% 5.0% 10.0% 15.0% 20.0% 25.0% 30.0% > 0.8 0.5 0.35 0.25 0.18 0.13 90 65 45-38 32-28 24-22 20-18 BCD Tri-Gate Pe rcen ta g e of pa pe rs Technology

Trends 2007/2013

2007 2008 2009 2010 2011 2012 2013

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Some advanced devices

13 20 nm FDSOI from ST

28 nm planar from TSMC

32 nm SOI from IBM

22 nm TriGate from Intel

V

ar

ious s

our

c

es

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16 nm FINFET

Sourc

e:

TSMC

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… and still, devices behave very well

15

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Technology enablers

Lithography

– Solution: turn the problem to work to your advantage!

– OPC

» Correct mask and process distortions by

synthesizing masks and not by introducing shorter

wavelength

– Double and multiple patterning

» Build images by superimposing patterns

New materials

– SOI wafers (reduce parasitic capacitances)

– Si-Ge and channel stress (enhance mobility)

– Gate oxide materials (need to avoid leakage

currents)

– Metal gates (avoid problem of poly depletion),

lower R

16

pe rm is s ion IE E E , S .H . L o e t a l. ,Qu a n tu m -M ec ha nic al M od eli ng … IE E E J S S C 1 8, 5, 1 99 7

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Atomic Scale Variability

17

fr om K . B erns tei n e t al ., IB M J . Res . & Dev . V ol . 50 No. 4 /5, 20 06

Atomistic view of dopants in 50nm transistor

fr om X . W an g et al ., IE DM 20 11 ,

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Some looming difficulties

Device variability

– transistors have atomic dimensions: dopants are in

“countable” number, oxides are few atomic layers thick

Slow lithography

– short wavelength powerful light sources are hard to make

Cost of new foundry

– Sub-20nm fab > 5B$

Design complexity

– number of devices (all must work, both functionally and

physically!)

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IMPORTANT BENEFITS FROM NEW TECHNOLOGIES

130 and 65 nm and Radiation hardness

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Core 130nm NMOS transistors, normal layout

1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

TID (rd) Ile ak ( A) N_10_10 N_10_012 N_088_012 N_053_012 N_028_012 N_016_012 annealing pre-rad 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

TID (rd) Ileak (A) N_10_013 N_04_013 N_024_013 N_018_013 N_014_013 pre-rad 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05

1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

TID (rad) Il e a k (A ) 0.16/0.12 0.32/0.12 0.48/0.12 0.8/0.12 2/0.12 10/1 10/10 ELT annealing pre-rad

Effect on the

leakage current

– Peak in leakage @ TID of 1-5Mrad

– Good recovery, strong indications

that ELT is not needed for regular

digital

Foundry A

Foundry B

Foundry C

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Core devices in 65nm, normal layout

21

Up to ~20mV shift for 200 Mrad

– Some rebound effect visible for narrow devices

– in 130nm: was 150mV

At high doses V_th shift is positive for wide devices, negative for narrow devices

– STI edge oxide traps considerable charge (RINCE)

Subtreshold slope does not change significantly

105 106 107 108 109 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 TID [rad]  Vth [ V ] ELT,148060 nm 12060 nm 24060 nm 36060 nm 48060 nm 60060 nm 100060 nm 101 mm 1010 mm 104 105 106 107 108 109 10-12 10-11 10-10 10-9 TID [rad] Ilea k [ A ] ELT 12060nm 24060nm 36060nm 48060nm 60060nm 100060nm 101mm 1010mm

Less than 10× increase in leakage

for wide devices (W > 360nm)

Narrow devices have up to 2.5

orders of magnitude increase

Fr o m S . B o n a cini e t a l, TW E P P 2 0 1 1

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OTHER BENEFITS FROM NEW TECHNOLOGIES

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Example of 130 nm density potential

12 bit PIC® compatible

microprocessor core

IO cell

Same scale

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Any idea for embedded FE processing?

C om par is on of ARM® c om patible pr oc es s or f rom U niv er s ity of Edi nbur gh, s ee: htt p:/ /gr oups .inf .ed. ac .u k /pas ta /hw _enc or e.ht m l

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Interfacing to the “standard” world

USB 2.0 OTG

– ~ 20-60K Gates

[1]

Ethernet 10-100-1000 MAC

– 20,560 gates

[2]

Notice that:

– 1 mm

2

_{in 130 nm contains ~ 200K gates}

– 1 mm

2

_{in 65 nm contains ~ 800K gates}

…and

– Production cost of 1 mm

2

_{in 130nm < 0.1 $}

– Production cost of 1 mm

2

_{in 65 nm < 0.15 $}

25

______________________________________________________________ [1] http://www.faraday-tech.com/techDocument/FOTG200_ProdBrief_v1.2.pdf [2] http://opencores.org/project,ethernet_tri_mode

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Further advantages at 130 nm and below

More process options useful for detector

integration

– More metal levels:

» shielding, power distribution (pixel chips are often

accessible on one side only), routability i.e. density

– More device types

» Many optimized V

_t

MOSFETs, higher capacitor

density, inductors, varicap, resistor types, fuses

– More substrate options

» NMOS p-well is almost universally available

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65nm

Analog features:

– Device intrinsic gain (= g

_m

* r

₀

): worse than 130nm

– Device max frequency: ~ 2x better than 130nm

– Matching: better than 130nm

– Intrinsic noise: about same as 130 nm or slightly better

Digital features:

– density:

» 4 x 130nm (even with RT devices)

– speed:

» ~ 2x 130 nm (depending on flavor)

– power:

» ½ to ¼ than 130 nm

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Advances in ADCs

28

rtesy o f P rof . B . M u rm a n n , S ta n fo rd Univ e rsi ty

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

10

20

30

40

50

60

70

80

90

100

110

120 P/f

sn y q

[pJ]

SNDR @ Nyquist [dB]

ISSCC 2013 VLSI 2012 ISSCC 1997-2012 VLSI 1997-2011 FOMW=10fJ/conv-step FOMS=170dB

FM

₌

Power

Freq 2 ^ ENOB*

ENOB

₌

(SNDR

-

1.76)

6.02

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Obsolescence?

29

So urce: T SMC f ina n ci a l rep ort

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OPPORTUNITIES:

- Chips for gas detectors

- Chips for trackers

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Chips for gas detectors

31

Fi g u re 5 .1 i n B. G ru b e ’s T h e s is “ T h e T ri g g e r Co n tro l Sy s te m a n d th e Com m o n G EM a n d Si lic o n Rea d o u t fo r t h e CO M PASS Ex p e ri m e n t”

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First complex chip: the “Altro”

S ou rc e L. Mu s a, CE RN -PH

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33 HIGH MULTIPLICITY COSMIC RAYS

Occupancy ~ 50%

• raw samples

• after signal processing

Signal Processing in Altro

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More cluster signal processing

S ou rc e T . A lt, L. Mu s a, CE RN -PH

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“Image” processing on chip

“Image” processing well possible with

current technologies

– Cluster reduction on FE chips

– Intelligent “zero suppression”

» Always collect “halos” around channels above

threshold

– Charge summing for adjacent pixels

» See Medipix3 approach!

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Charge summing in Medipix3

55µm

The winner takes all

• Charge is

summed in every 4

pixel cluster on an

event-by-event

basis

• Full charge is

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(Energy spectra measurements with

Medipix3RX and CdTe: T. Koenig talk

(Detectors and simulations 2))

Measurements (60keV, 110

m

m pitch, 2mm CdTe)

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Local feature extraction for trackers

Level-1 data require local rejection of low-p

_T

tracks

– To reduce the data volume, and simplify track finding @ Level-1

» Threshold of ~ 1÷2 GeV



data reduction of about one order of

magnitude

Design modules with p

_T

discrimination (“p

_T

modules”)

– Correlate signals in two closely-spaced sensors

» Exploit the strong magnetic field of CMS

Level-1 “stubs” are processed in the back-end

– Form Level-1 tracks, p

_T

> 2÷2.5 GeV

» To be used to improve different

trigger channels

39 m

m

F r z

“stub”

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Substrate

~ 48 mm

Simplified cross-section

Z

Strip sensor

Pixel Sensor

MacroPixel ASIC Short Strip ASIC

• One layer of strips + One layer of Strixels

• r-

F

resolution: 100

m

• Z resolution: 1.5 mm

R Cooling

~ 2

m

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MPixel ASIC dataflow

41 MPixel

Event

Store

Intf to GBT

Link

Trigger Logic

CLK Generation

& Cntrl

FE

Strip

from

M

Pix

el

c

olum

n

W in d o w e d p T c o in c id e n c e Po s iti o n d e c o d e r

Strip

Event

Store

Event

Formatter

Config Regs

Clo c k s @ L1 @ each BX W id e c lu s te r e lim in a ti o n

Traditional data path

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MPA: Trigger (stub) generation

A. Marchioro - MPGD2013 42 Pixe lH it R eg S tr ipH it R eg

Column

OR-ing

StripCluster

Elimination

& Centroids

Coi

nc

idenc

e

MatchMask[1:5] ClusterCut[3:0] P ix el O red Hi tReg

F

Shift

(2 of 64 bits) PhiShift[]

Pi

x

el

Hi

t

Reti

mi

ng

Retime[1:0] C ent roi dsR et im e Plus Minus

PixCluster

Elimin &

Centroids

LeftRightOut LeftRightIn <128> <8> <8> <2048> <140> <128> <8> <8> <136> <128> <128> <128> <128> <140> <128> Retime Z Priority Encoder <512> P ix el P ipe Reg1 <512> <512> P ix el P ipe O ut[ 51 1:0 ]

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Conclusions

Development is limited by (lack of) ideas,

not by technology

– … and not even by the “cost” of adv tech

The HEP community has much to learn,

(and to profit from) adopting standards, IP

sharing, and avoiding NIH attitudes

Detectors and microelectronics should be

developed in parallel

– much to be expected from jointly conceived

SoC for detectors

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Core 130nm NMOS transistors, enclosed layout

NMOS ELT min/0.12

1.00E-12 1.00E-11 1.00E-10 1.00E-09 1.00E-08 1.00E-07 1.00E-06 1.00E-05 1.00E-04 1.00E-03 -0.2 0.3 0.8 1.3 Vg (V) Id (A ) Pre-rad 3Mrad 136Mrad 2d HT ann

PMOS ELT min/012

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 -0.2 0.3 0.8 1.3 Vg (V) Id ( A ) _pre-rad 3 Mrd 40 Mrd

S

D

G

45

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Halo Energy recovery for trigger in NA48

E

_Tot

=

E

_j

+

E

_k Neigh

å

>

å

Thres A. Marchioro - MPGD2013

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G ia n o li e t a l., T h e NA4 8 L Kr c a lo ri m e te r re a d o u t e le c tro n ic s , RT C 1 9 9 9

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