COMPUTER-AIDED DESIGN OF
ALGORITHMIC STATE MACHINE
Safaa Sahib Omran
Foundation of Technical Education, Iraq
Saleem M R Taha
University of Baghdad, Iraq
Ahmed Amer Ibraheem
Engineer
ABSTRACT
The Algorithmic State Machine (ASM) is a method used to solve more complex industrial problems. The basic advantage of this method is to convert these problems to simpler circuits which consist only from the basic elements which are AND, OR and NOT gates, which can be implemented easily by using the Programmable Logic Array (PLA) circuits.
The entry variables (number of inputs and states) for such problems are large, this made the theoretical (manual) solution is hard to solve. This research constructs a computer package called (ASM-CAD) to make the entire design using C++ and TC++ programming languages.
Key Words:
Algorithmic State Machine (ASM) method.Programmable Logic Array (PLA) circuit. Quine-McCluskey is a programmable method.
1. Introduction
An approach to logic design of a digital system is to partition the system into two entities: a controller and a controlled
architecture, also called the data processor. Such a partition is given in Fig (1) below [1].
Status Information
Controller (ASM)
Commands Controlled
Architecture (data processor)
External inputs Input data Output data Fig (1), Partitioning of a digital system.
A well-defined procedure consisting of a finite number of steps to the solution of a problem is called an algorithm. Thus, the controller is regarded as a hardware algorithm and, consequently, it is referred to us an Algorithmic State Machine, or, simply, ASM.
Although an algorithmic state machine as a controller facilitates the design of larger digital systems incorporating Middle Scale Integration (MSI) components, an algorithmic state machine can also serve as a stand-alone sequential network module. In this case there is no data processor being controlled and the network being modeled is essentially a classical Mealy network or Moore network. Hence, the algorithmic state machine becomes another approach to clocked synchronous sequential network modeling [2].
The ASM or Algorithmic State Machine is another name for a sequential network. This name is often used when the sequential network is used to control a digital system that carries out a step-by-step procedure or algorithm. It is a special type of flowchart so the ASM also called state machine flowchart, the ASM may be used to describe the behavior of a state machine [3].
There are two methods for controlling a digital system, ASM and microcomputer based digital system. There are many differences between these two methods, some of them are:
1. The execution of the circuit by using the ASM is more speed than using the microcomputer.
2. The hardware cost by using the ASM is less expensive than using the microcomputer.
3. The modification of the hardware by using the ASM is more difficult than using the microcomputer.
There are several significant differences between the ASM and the well known flowchart technique used in computer program design. There are several significant differences, but the main one is concerned with the representation of time relationships. The flowchart usually represents a continuous time flow from top to bottom to reflect the sequence of operations performed by the program. The ASM chart, on the other hand, has discontinuities in the time frame and time moves on in quantum steps as control passes from one state to the next. Within the portion of the chart devoted to one state there are no assumed time relationships [4, 5].
2. Design of ASM-CAD
The ASM chart provides a diagrammatical representation of the state-transition functions and output functions of a state machine. It is used as an aid to the design of a state machine for the implementation of an algorithm and on completion becomes part of the design documentation.
Because of the many degrees of freedom in designing an algorithmic state machines, no single procedure can be considered to be the best available. To provide a framework for solving this problem, the task can be divided into a series of steps as follows:
1. Construct an algorithmic state diagram or state table for the state machine. 2. Assign proper states with efficient
codes (using state locus).
3. Construct next state table along with input information for flip-flops.
4. Design flip-flops input forming logic. 5. Design output forming logic.
6. Draw final circuit diagram using Programmable Logic Array (PLA).
For the design of ASM-CAD, the Quine-McCluskey method is used instead of Karnaugh-map since it is easily programmed method [6, 7, 8].
Using the ASM-CAD package to design the example down below:
The desired circuit may be considered to operate due to the following design specifications. Fig (2) shows the process schematic.
3. Problem definition
An assembly line has a picture tube buffer store, which can accommodate up to 30 picture tubes.
A- Monitoring the number of picture tubes:
Two photoelectric barriers (E and H) control the entry of picture tubes to, and their removal from, the buffer store. The light barriers’ impulses are transmitted to a counter. If the buffer store is empty at the beginning of a shift, the counter can be calibrated by pressing a momentary-contact pushbutton.
B- Upper limiting value:
The buffer store is full when it contains 30 picture tubes. Conveyor belt motor Z1 must be stopped immediately.
C- Lower limiting value:
A lamp must indicate that the buffer store contains fewer than 10 picture tubes.
ON
Signal OFF
C
Z2
Calibrate D
H
E
Fig (2), Process schematic of buffer store. E
H
5 4 3 2 1
30 Z1
4. Solution procedure
Firstly, make the following declarations and assumptions:
1. Two barriers (E and H) control the entry and exit from buffer store and the counter up and down, respectively.
2. If G=1 (N=30) then the store is full and Z1 OFF.
3. If F=1 (N<10) then Z2 ON.
E=1 means the tube enter the buffer store.
H=1 means the tube out from the store. C=1 means the operation is ON.
D=1 means the counter is cleared. G=1 means the store is full.
F=1 means the store contain fewer than 10 tubes then Z2 ON.
Z3=1 means the counter is incremented. Z4=1 means the counter is decremented.
Secondly, according to the above assumptions, construct the proposed ASM control circuit as shown in Fig (3) below.
ASM Control
to be
designed
Z3
E H C D F G
Fig (3), Block diagram of buffer store. Compar
ator 2
Compar ator 1
30 10
F=1 if N<10 F=0 if N>=10 G=1 if N=30
G=0 if N<30
Z2
Z1
Z4
D
N
Thirdly, construct the ASM-chart as shown in Fig (4) below.
Fig (4), ASM-chart for the buffer store.
Fourthly, make the state table from the
ASM-chart as shown in Fig (5) below.
0 1
0 1
0 1
0
0 1
C
Z1
Z3
Z4
Z4
Z2 a
b
c
D 1
E
G
H
F H
1 0
Present State
Inputs
C D E F G H
Next
State
Outputs
Z1 Z2 Z3 Z4
a
0 x x x x x
a
0 0 0 0
a
1 0 x x x x
a
0 0 0 0
a
1 1 x x x x
b
0 0 0 0
b
x x 0 0 x 0
b
1 0 0 0
b
x x 0 1 x 0
b
1 1 0 0
b
x x 0 0 x 1
b
1 0 0 1
b
x x 0 1 x 0
b
1 1 0 1
b
x x 1 x 1 x
c
1 0 1 0
b
x x 1 0 0 0
b
1 0 1 0
b
x x 1 1 0 0
b
1 1 1 0
b
x x 1 0 0 1
b
1 0 1 1
b
x x 1 1 0 1
b
1 1 1 1
c
x x x x x 0
c
0 0 0 0
c
x x x x x 1
b
0 0 0 0
Fig (5), State table for the buffer store.
The procedure of how the package works is as follows:
1. The user must enter all the data from the state table that constructed from the ASM-chart (designed by the user) to the ASM-CAD package.
2. The package prints out the original state table as entered on the screen just to make sure from the correctness of the data.
3. The package computes the number of the required flip-flop and prints it out on the screen.
4. The package asks the user to enter the number of assignments.
5. The package asks the user to assign codes to each state.
6. The package computes the state locus and prints it out on the screen. 7. The package print out the assigned
state table for each state locus.
8. The package repeats steps (5, 6 and 7) until reaches the number entered in step (4).
9. The package computes the minimum state locus and prints it out on the screen.
10. The package asks the user to choose one type of a flip-flop.
11. The package computes the next state equations for the flip-flop and the output equations for the circuit.
The Result lists of the Buffer Store will be NEXT STATE EQUATION FOR STAGE A:
B A EG
JA= and KA=HA
NEXT STATE EQUATION FOR STAGE B:
B CD
JB= and KB=0
OUTPUT EQUATION FOR OUTPUT Z1:
B A Z1=
OUTPUT EQUATION FOR OUTPUT Z2: B
A G F F E
Z2=( + )
OUTPUT EQUATION FOR OUTPUT Z3:
B A E Z3=
OUTPUT EQUATION FOR OUTPUT Z4: HA
B A H G H E
Z4=( + ) +
12. Finally, the package draws the PLA circuit diagram for the circuit which satisfies the above equations as shown in Fig (6).
A
B
C
D
E
F
G
H
Z1
Z2
Z3
Z4
JA
KA JB
Logic 0
Clock
5. Conclusion
As the problems becomes more and more complex (large numbers of inputs and outputs), the theoretical solution (the manual) becomes unpractical and need a several hours to make the entire design, so this package is very useful and save time and effort (need only a few seconds to make the entire design), the ASM is a powerful method on a digital system since it gives a simple circuit consist of AND, OR and NOT gate only (PLA elements).
A set of test problems have been performed on all parts of the package, comparing between the results obtained from the computer and the theoretical (manual) results lead to identical, valuable and reliable results. The program gives error-free results if the user constructs the ASM-chart in a proper and correct way. The reason of why using of Quine-McCluskey method instead of using Karnaugh-map is that, for example consider the studied circuit above (Buffer Store), there is three states and 6-inputs this mean needing of 8-variable K-map (2^8=256 squires). By using Quine-McCluskey method, this is also need along time to solve but it is easily programmed method.
References:
[1] Donald D. Givone, “Digital Principles and Design”, Tata McGraw-Hill Publishing Company Limited, 2003.
[2] D. Green, “Modern Logic Design”, Workingham: Addison Wesley, 1986.
[3] Klingman, Edwin E., “Microprocessor System Design”, Prentice - Hill, Englewood Cliffs, N. J., 1982.
[4] Stephen Brown and Z. Vranesic, “Fundamentals of Digital Logic with VHDL Design”, McGraw-Hill, 2000.
[5] Wiatrowski, Claude A. and Charles H. House, “Logic Circuits and Microcomputer Systems”, McGraw-Hill Book Co., New York, 1980.
[6] David J. Comer, “Digital Logic and State Machine Design”, Holt-Saunders International Edition, 1984.
[7] John F. Wakerly, “Digital Design Principles and Practices”, Prentice-Hall, 3rd edition, August 2000.
[8] C. R. Clare, “Designing Logic Systems Using State Machines”, McGraw-Hill Book Company, 1973.
