Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistors by Focused Ion Beam

ABSTRACT

ZHU, WENCONG. Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistors by using Focused Ion Beam. (Under the Dr. John Muth).

Compared with other transparent semiconductors, amorphous indium gallium zinc oxide (α-IGZO) has both good uniformity and high electron mobility, which make it as a good candidate for displays or large-scale transparent circuit. The goal of this research is to fabricate α-IGZO thin film transistor (TFT) with channel milled by focused ion beam (FIB). TFTs with different channel geometries can be achieved by applying different milling strategies, which facilitate modifying complex circuit. Technology Computer-Aided Design (TCAD) was also introduced to understand the effect of trapped charges on the device performance.

The investigation of the trapped charge at IGZO/SiO2 interface was performed on the IGZO TFT on p-Silicon substrate with thermally grown SiO2 as dielectric. The subgap density-of – state model was used for the simulation, which includes conduction band-tail trap states and donor-like state in the subgap. The result shows that the de-trapping and donor-state ionization determine the interface trapped charge density at various gate biases.

Simulation of IGZO TFT with FIB defined channel on the same substrate was also applied. The drain and source were connected intentionally during metal deposition and separated by FIB milling. Based on the simulation, the Ga ions in SiO2 introduced by the ion beam was drifted by gate bias and affects the saturation drain current.

ions and the devices show switch feature. Direct channel shows higher saturation drain current (~10-6 _{A) compared with side channel (~10}-7 _{A) because of its shorter channel length and} wider width, however, it also exhibit higher gate leakage current (>10-7 A) than side channel (<10-7 _{A) due to larger Ga ion implantation and diffusion region in SiO2 after annealing.} Hysteresis window increase and positive VON shift were also observed due to the interface trap density increase and carrier density suppression both by Ga ions.

Laser interference lithography was applied to define the IGZO active region, which gives more flexibility on TFT channel dimension and circuit modification. He-Cd laser with 325 nm wavelength was used to define 2D array of IGZO islands with period of 2.5 μm. Logic gate array was designed and fabricated by combining this 2D array of IGZO islands and FIB direct channel milling. After annealing, device shows on-off feature, but high temperature (400 °C) release more free carrier and results in negative shift of VON.

Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistor by using Focused Ion Beam

by Wencong Zhu

A dissertation submitted to the Graduate Faculty of North Carolina State University

in partial fulfillment of the requirements for the degree of

Doctor of Philosophy

Electrical Engineering

Raleigh, North Carolina 2015

APPROVED BY:

_______________________________ _______________________________ Dr. John Muth Dr.Veena Misra

Committee Chair

DEDICATION

天生我材必有用

Everyone was born for a reason

BIOGRAPHY

Wencong Zhu was born in Jinan, the capital city of Shandong Province, east China. With the purpose of seeing different world and receiving better education, he went to the first university of modern China, Tianjin University (Peiyang University) to pursue his Bachelor’s degree. After graduation, the thirst for knowledge and technology drove him to continue the graduate study in U.S, at Electrical and Computer Engineering Department at North Carolina State University in 2009. Wencong joined Dr. Robert Kolbas’s group in 2010 with the research on AlGaAs quantum well and received his Master’s degree in Electrical Engineering in spring 2011. After deciding pursuing Ph.D. degree, he became the member of Dr. John Muth’s group with the study focusing on AlGaAs LED and IGZO TFT. He graduated from North Carolina State University with his Ph.D. degree in Electrical Engineering in summer 2015.

ACKNOWLEDGMENTS

Obtaining the Ph.D. degree was my biggest dream until my current life, and I want thank everyone that helped me realizing this dream during the past six years at North Carolina State University.

I would like to thank Dr. Muth, who is my most important academic advisor. He has so wide range of knowledge and always inspired me when I came to him. He is also a generous person, and always willing to share ideas, facilities and resources with other people. I cannot realize my dream without his guidance.

I want to thank Dr. Kolbas, who is my first graduate advisor. He is such a nice professor and respected by everyone. He can explain a complicated theory by an easily understanding way and is always willing to discuss and communicate with students. Everyone loves him after taking his classes.

I would like to thank Dr. Misra. She is an expert in semiconductors and gave me a lot of very useful suggestions on my research. Besides, without the ALD tool and characterization facilities in her lab, this work would be mission impossible.

I want to thank Dr. Aspnes for being my committee member. He is expert in physics, especially in the field of my research, thus his advice means a lot to my research. Discussions with him always give me a deeper insight into my research.

I want to express my thanks to Dr. Escuti, and Dr. Komanduri. Dr. Escuti is a brilliant professor in Optics. This work cannot be done without using the optical facilities in his lab. D . Ravi helped me so much for the training on interference lithography and he was always there when I had trouble.

Joe provided the most important help on the training of every facility I used in cleanroom. He helped me out every time I was in trouble, especially during the last crazy busy months of my research. I will miss the time we work together.

I would like to thank all the former and current members in MRC 112. They made my graduate study more interesting and my life more colorful. They are: Haojun Luo, Yan Wang, Yi Lou, Hongguo Zhang, Yifan Wang, David Luo, Xiang Ji, Jong Boem Park, Kanu, Leandra, Abhishek, Benjamin, Sushmit, I want to give special thanks to Haojun for his guidance on IGZO TFT fabrication, Yan for his help in both North Carolina and California, and Leandra for her training on laser interference lithography and PLD.

At last, I want to express my deepest thank to my parents, especially my Mother. She is the best teacher I have ever seen, and set the role of mine. She gave me the best support in my toughest period of research. I want to thank my girlfriend Wei Zhang, who is my soul mate and bring me sunshine every day.

TABLE OF CONTENTS

LIST OF TABLES ··· x

LIST OF FIGURES ··· xi

CHAPTER 1 INTRODUCTION ··· 1

1.1 Overview ··· 1

1.2 Research Objective and Dissertation Organization ··· 3

CHAPTER 2 LITERATURE REVIEW AND BACKGROUND ··· 8

2.1 Thin Film Transistor ··· 8

2.1.1 Background and History ··· 8

2.1.2 Device Structure ··· 10

2.1.3 Basic Device Operation ··· 12

2.2 Electronic Structure of Amorphous Oxide Semiconductor (AOS) ··· 16

2.3 Indium Gallium Zinc Oxide (IGZO) ··· 17

2.4 Modeling and Simulation of α-IGZO TFT ··· 21

2.5 Fundamentals of IGZO TFT ··· 26

2.5.1 Contact Electrode ··· 26

2.5.2 Gate Dielectric Materials ··· 26

2.5.3 Device Stability ··· 27

2.6 Integrated Circuit Based on IGZO ··· 30

2.7 Laser Interference Lithography ··· 34

2.7.1 Basic Theory ··· 35

2.7.2 Two-Beam Interference Arrangements ··· 36

2.7.3 Two Degrees-of-Freedom Lloyd-Mirror Interferometer ··· 39

2.7.4 Multi-Beam Interference Lithography for Nano-Electronics ··· 40

CHAPTER 3 TOOLS FOR SIMULATION, EXPERIMENT AND DEVICE CHARACTERIZATION ··· 42

3.1 TCAD Simulation and Modeling of α-IGZO TFT ··· 42

3.1.1 TCAD Introduction ··· 42

3.1.2 Device Simulation Flow ··· 43

3.2 Pulsed Laser Deposition ··· 46

3.3 Plasma Enhanced Chemical Vapor Deposition ··· 50

3.4 Electron Beam Evaporation ··· 51

3.5 Thin Film Patterning ··· 53

3.5.1 Photolithography ··· 53

3.5.2 Lift-Off Process ··· 55

3.5.3 Etch Process ··· 55

3.6 Focused Ion Beam ··· 56

3.7 Experiment Setup of Laser Interference Lithography ··· 57

3.8 Device Fabrication ··· 59

3.9 Electrical Characterization of Thin Film Transistors ··· 61

3.9.1 Thin Film Transistor Operation Modes ··· 61

3.9.2 DC Current-Voltage Measurement-Output Characteristics ··· 62

3.9.3 DC Current-Voltage Measurement-Transfer Characteristics ··· 63

CHAPTER 4 MODELING AND SIMULATION OF IGZO TFT ··· 71

4.1 Sample Preparation ··· 71

4.2 Simulation Model for α-IGZO ··· 72

4.3 Simulation for α-IGZO TFTs with Long Channel ··· 74

4.3.1 Trapped Charge Density Extracted from Output Characteristics of α-IGZO TFTs with Long Channel ··· 75

4.3.2 Transfer Characteristics Simulation Result of α-IGZO TFTs with Long Channel ··· 77

4.4 Simulation of α-IGZO TFTs with Short Channel Milled by Focused Ion Beam (FIB) ··· 82

4.5 Conclusions ··· 86

CHAPTER 5 SHORT CHANNEL α-IGZO THIN FILM TRANSISTOR FABRICATED BY FOCUSED ION BEAM ··· 88

5.1 Focused Ion Beam (FIB) milling ··· 88

5.1.1 FIB Introduction ··· 88

5.1.2 The Objective of Using FIB ··· 91

5.1.3 Multi-layer Thin Film Milled by FIB ··· 92

5.1.4 Device Modification by FIB Milling ··· 95

5.2 Short Two-Sides-Channel α-IGZO TFTs Milled by FIB ··· 97

5.2.1 Right After FIB Milling ··· 98

5.2.2 Annealing in Air At 200 ºC for 10 min ··· 99

5.2.3 Annealing in Air At 250 ºC for 10 min ··· 102

5.2.4 Annealing in Air At 300 ºC for 10 min ··· 104

5.3 Short One-Side-Channel α-IGZO TFTs Milled by FIB ··· 105

5.3.1 Right After FIB milling ··· 105

5.3.2 Annealing in Air At 200 ºC for 10 min ··· 106

5.3.4 Annealing in Air At 300 ºC for 10 min ··· 109

5.4 Discussion on Side Channel TFTs Milled by FIB ··· 110

5.4.1 Effect of Residual Ions by FIB milling ··· 110

5.4.2 Effect of Side Channel Length on TFTs with Side Channel Milled by FIB ··· 114

5.4.3 Compare Between One-Side Channel and Two-Side Channel TFTs Milled by FIB ··· 116

5.5 Short Direct-Channel α-IGZO TFTs Milled by FIB ··· 118

5.5.1 Right After Milling ··· 120

5.5.2 After Annealing in Air At 200 ºC for 30 min ··· 121

5.5.3 After Annealing in Air At 250 ºC for 30 min ··· 122

5.5.4 After Annealing in Air At 300 ºC for 30 min ··· 124

5.5.5 Discussion ··· 125

5.6 Effect of Channel Dimension on Drain Current and Leakage Current ·· 127

5.7 Conclusions ··· 131

CHAPTER 6 SHORT CHANNEL THIN FILM TRANSISTOR WITH TWO DIMENSIONAL ARRAYS OF α-IGZO ISLANDS PATTERNED BY LASER INTERFERENCE LITHOGRAPHY ··· 133

6.1 Laser Interference Lithography ··· 133

6.2 Device Fabrication ··· 135

6.3 Layout Design of Logic Arrays ··· 138

6.4 Short Direct-Channel TFTs with Laser Interference Lithography Patterned IGZO Active Layer and Milled by FIB ··· 140

6.4.1 Right After Milling ··· 142

6.4.2 After Annealing in O2 At 250 °C for 20 min & At 300°C for 20min ··· 142

6.4.3 After Annealing in O2 At 350 °C for 20 min & 50 min ··· 144

6.4.4 After Annealing in O2 At 400 °C for 10 min ··· 145

6.4.5 Compare of Transfer Characteristics at Different Vr ··· 146

6.5 Conclusions ··· 148

CHAPTER 7 CONCLUSIONS AND FUTURE WORKS ··· 149

7.1 Conclusions ··· 149

7.2 Suggestions for Future Work ··· 151

7.2.1 Different Dielectric Material with Better Quality ··· 152

7.2.2 Further Investigation on the Material ··· 152

7.2.3 Improvement on the Profile of IGZO Islands ··· 152

7.2.4 Better Control of FIB Milling ··· 153

7.2.5 Ultra Short Channel by Using Laser Interference Lithography and FIB milling ··· 155 REFERENCES ··· 156

LIST OF TABLES

Table 1.1. Optional structures that can be fabricated by using FIB milling. ··· 6 Table 2.1. Comparison of several materials used in displays [29]. ··· 19

LIST OF FIGURES

FIG.1.1. Schematic of different milling strategies to modify the effective width of TFTs with IGZO islands patterned by laser interference lithography ··· 7 FIG. 2.1. Schematics of some of the most conventional TFT structures, according to the position of the gate electrode and to the distribution of electrodes relatively to the semiconductor [22] ··· 12 FIG. 2.2. The TFT structure and energy band diagram as viewed through the gate: (a) the cross-section structure of TFT, (b) at equilibrium, VGS=0, (c) accumulation mode, VGS > 0, (d) depletion mode, VGS < 0 ··· 14 FIG. 2.3. Schematic electronic structure of silicon and ionic oxide semiconductors. (a-c) Bandgap formation mechanisms in (a) covalent and (b,c) ionic semiconductors. (d-g) Carrier transport paths in (d) c-Si, (e) α-Si, (f) crystalline oxide and (g) amorphous oxide [23]··· 17 FIG. 2.4. (a) Amorphous formation and (b) electron transport properties of

In2O3-Ga2O3-ZnO thin films. The values in (b) denote the electron Hall mobility (cm2/V s) with density (1018 cm-3) in parentheses [28] ··· 18 FIG. 2.5. (a) (Color) Structure of the InGaZnO4 crystal. The brown, blue and red balls represent In, Zn/Ga and O atoms, respectively. (b) Partial density-of-states (DOS) curves for InGaZnO4 crystal structures. The top of the valence band is located at zero energy and total DOS is also shown in each figure as reference. (After Orita et al., Ref [31]) ··· 20 FIG. 2.6. (a) Hall mobilities of InGaO3(ZnO)m as function of electron density.c-IGZO1 and c-IGZO5 represent crystalline phases with m = 1 and 5, respectively. HQ and LQ denote high-quality and low-quality, respectively. (b) Potential distribution above CBM analyzed based on percolation transport model [33]. (c) Illustration to explain the percolation conduction model [34] ··· 21

FIG. 2.7. (a) Proposed DOS model for α-IGZO. 2. EC and EV are conduction and valence band edge energies, respectively. Solid curves within the bandgap represent the exponentially distributed band-tail states (gCBa, gVBd), while the dash curve near the conduction band edge represents the Gaussian-distributed donorlike OV states (gGd). (b) and (c) Transfer characteristics (W/L=180/30 μ. ( Both experimental (circle) and simulation data (solid line: Schottky contact; +: Ohmic contact) are shown. Extracted threshold voltage (Vth), field-effect mobility (μeff),

and subthreshold swing (S) are also indicated. Inset of (c): the 2D TFT structure used in simulation ··· 23

FIG. 2.8. (a) VTH and on/off ratio as a function of semiconductor thickness for different ND.

Band profile of TFTs with (b) d =150 nm and (c) d = 200nm. The QFL is close to the conduction band edge when high negative voltage is applied to gate electrode for d = 200nm. ··· 25 FIG. 2.9. (a) Typical response to monochromatic light of transfer characteristic of annealed α-IGZO TFT. The photon flux was fixed at ~1×1014 _{photons (cm}-2_s-1_{). The blue} dashed lines correspond to illumination above the band gap (>3.1 eV) and the black solid lines correspond to subgap illumination. (b) Model to explain NBL instability. ··· 28 FIG. 2.10. Temperature dependence of transfer characteristics (VDS=10V, L/W = 10/100 µ): (a) ascending sequence and (b) descending sequence. ··· 29 FIG. 2.11. Temperature dependence of transfer characteristics (VDS=10V, L/W = 10/100 µ): (a) ascending sequence and (b) descending sequence. ··· 31 FIG. 2.12. Schematic diagram and voltage transfer curve of the inverter with a depletion load (a) and enhancement load (b) [69]. ··· 32

FIG. 2.13. Optical microscopic image of dual-gate α-IGZO TFT [45] (a) and NAND, NOR gate using separate devices (b) [71] . ··· 33

FIG. 2.14. (a) Two-beam interference forms s standing wave. (b) A SEM image of 1D interference pattern having a 1 μ periodicity recorded in the negative photoresist SU-8. ··· 36

FIG. 2.15. Two commonly used two-beam IL setups. (a) A Lioyd’s mirror configuration, (b) A two-beam configuration created by a beam splitter. The dotted triangle represents the prism used in liquid immersion lithography [99]. ··· 37 FIG. 2.16. (a) A simulation contour map of an IL pattern formed by a double exposure first in the x-direction and then in the y-direction. (b) A SEM image of a hexagonal structure created by double exposure IL where the substrate was rotated 60° about its normal between exposures. ··· 39 FIG. 2.17. Schematic of Lloyd-mirror interferometer with 2-DOF configuration, the angles x and y are varied independently. ··· 40 FIG. 2.18. (a) Scanning electron microscope image of combining MBIL and

photo-lithography techniques. Two-beam interference photo-lithography is used to define 45nm grid lines and higher spatial frequency modulating pattern was defined by photo-lithography (Copyright 2004, Reprinted with permission of Cambridge University Press [108]). (b) A complex composite pattern is created by two exposures and modulated by photo-lithography (edited with permission from [107]). ··· 41

FIG. 3.1. Typical tool flow with device simulation using Sentaurus Device [112]. ···· 43

FIG. 3.2. Schematic of the pulses laser deposition system in NCSU. ··· 48 FIG. 3.3. (a) Laser interference lithography setups for p polarized light. (b) Demonstration of power adjustment by using paper. ··· 59 FIG. 3.4. Process flow of IGZO TFT device fabrication. ··· 61 FIG. 3.5. (a) ELR method and (b) GMLE method implemented on the ID-Vg

characteristics of the same device measured at VDS = 10 mV. ··· 65 FIG. 4.1. (Color online) Proposed DOS model for α-IGZO. 4. EC and EV are conduction and valence band edge energies, respectively. Solid curves within the bandgap represent the exponentially distributed band-tail states (gCBa), while the dash curve near the conduction band edge represents the Gaussian-distributed donorlike OV states (gGd).··· 74 FIG. 4.2. (a) Cross-section of the α-IGZO TFT structure for simulation and (b) output characteristics (W/L = 100/20 µm). Both experimental (triangle) and simulation data (solid line) are shown. ··· 75 FIG. 4.3. (a) Trapped charge density at IGZO/SiO2 interface and (b) constant mobility as a function of gate bias voltage, extracted from the simulated output characteristics shown in Fig. 3(b). ··· 76 FIG. 4.4. (a) α-IGZO TFT transfer characteristics (W/L = 100/20 µm). Both experimental (circle) and simulation data (solid line) are shown. (b) Trapped charge density at interface as a function of gate voltage for both forward and backward bias sweeping. Arrows indicate the sweeping directions. ··· 78 FIG. 4.5. (a) Band diagram of α-IGZO TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=-4V at forward gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. ··· 79 FIG. 4.6. (a) Band diagram of α-IGZO TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=20V at forward gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. ··· 80 FIG. 4.7. (a) Band diagram of α-IGZO TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=15V at reverse gate bias sweeping.

For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. ··· 80 FIG. 4.8. (a) Band diagram of α-IGZO TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=2V at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. ··· 81 FIG. 4.9. (a) Band diagram of α-IGZO TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=0V at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. ··· 81

FIG. 4.10. (a) Band diagram of α-IGZO TFT at the IGZO/SiO2 interface along the length direction and (b) ionized donor density-of-states compared with donor trap density-of-state in the subgap region, at Vgs=-0.5V at reverse gate bias sweeping. For (a), left side is source and right side is drain. For (b), 3.0eV indicates the conduction band minimum. ··· 82 FIG. 4.11. (a) Output characteristics of short channel α-IGZO TFT by FIB milling, both experimental (triangle) and simulation data (solid line) are shown. (b) The transport of Ga+ induced mobile hole at positive gate bias. ··· 85 FIG. 4.12. (a) Demonstration of hole transport in SiO2. (b) The location of transvers plane with equivalent positive charge distribution as a function of gate bias. 0 µm and 0.1 µm refer to the SiO2/substrate interface and SiO2/IGZO interface separately. ··· 86

FIG. 5.1. (a) FEI Quanta 3D FEG dual beam system from Analytical Instrumentation Facility (AIF) of NCSU (b) Configuration of dual-beam column for ion milling [144]. ··· 90 FIG. 5.2. (a) Schematic diagram illustrating some of the possible ion beam-material interactions [122]. (b) SEM images of the end-edge view of a single pixel width line scan and the trench cross-section profile fitting with a Gaussian function [145]. ··· 90 FIG. 5.3. Devices with different channel dimensions: (a) and (b) shows channels with different length, and (c) presents channel with thinner thickness. ··· 92

FIG. 5.4. The cross-section view of etched trench by FIB with ion beam energy and current of 16keV, 11pA (a) and 30keV, 30pA (b). ··· 93 ··· FIG. 5.5. (a) Plain view of the milled trench with different parameter z depth. From left to

right: z=180nm, 100nm, 150nm, 120nm. The cross-section views are shown in right as (b) for z=180nm, (c) for z=100nm, (d) for z=150nm and (e) for z=120nm. The ion beam energy and current are 30keV and 10pA. ··· 94

FIG. 5.6. The cross-section view of the TFT structure before modification (a) and after modification by FIB (b). ··· 96

FIG. 5.7. (a) Cross-section view of deep trench milled by FIB for side channel TFTs. (b) and (c) demonstrate the current flow for two-sides channel TFTs and one-side channel TFTs separately. The void is formed because of the joint of deposited Pt on upper side wall, which stop the Pt deposition on lower side wall and the bottom of the trench. ··· 97 FIG. 5.8. (a) Illustration of current flow when the device is in on state, Vgs > VT, Vds > 0,(b) Transfer characteristic (Vds = 0.1V and 1V) of α-IGZO two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB. ··· 98 FIG. 5.9. Illustration of the residual Ga ions diffusion before annealing (Left) and after annealing (Right). ··· 100 FIG. 5.10. (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α

-IGZO two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB and annealing at 200 ºC for 10 min. ··· 101 FIG. 5.11. (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α

-IGZO two-side channel TFT with 4um wide metal line and 100nm wide trench milled by FIB and annealing at 250 ºC for another 10 min. ··· 103 FIG. 5.12. (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α

-IGZO two-side channelTFT with 4um wide metal line and 100nm wide trench milled by FIB and annealing at 300 ºC for another 10 min. ··· 104 FIG. 5.13. (a) Illustration of current flow when the device is in on state, VGS > VT, VGS > 0,(b) Transfer characteristic (Vds = 0.1V and 1V) of α-IGZO one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB. ··· 105 FIG. 5.14. (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α

-IGZO one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB and annealing at 200 ºC for another 10 min. ··· 107

FIG. 5.15. (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α -IGZO one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB and annealing at 250 ºC for another 10 min. ··· 108 FIG. 5.16. (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of α

-IGZO one-side channel TFT with 8um wide metal line and 100nm wide trench milled by FIB and annealing at 300 ºC for another 10 min. ··· 110 FIG. 5.17. (a) Schematic of the FIB ion beam with zero incident angles (black solid) and non-zero incident angle (red dashed) to the sample stage. (b) shows the cross-section view of milled trench when the ion beam is tilted to right (top) and tilted to left (bottom). ··· 112 FIG. 5.18. Demonstration of residual Ga ions distribution depends on the ion beam

direction. ··· 113 FIG. 5.19. The transfer characterization of two-side channel TFTs milled by FIB without annealing when the main current occur between drain-source (a), gate-drain (b), and gate-source (c). ··· 114

FIG. 5.20. Illustration of current flow of one-side TFTs mill by FIB with excess trench length of (a) 298.4nm and (b) 708.3nm. ··· 115 FIG. 5.21. Compare of the one-side channel TFTs with different effective channel length, after annealing at 250 ºC in air for 10 min. ··· 116 FIG.5.22. Compare between one-side channel and two-side channel TFTs, after annealing at 250 ºC in air for 10 min. ··· 117 FIG. 5.23. (a) Shows the plain view of milled trenches with different milling depth (z parameter). The cross-section view are shown also shown in (b) for z=85nm, (c) for z=90nm and (d) for z=95nm. ··· 119 FIG. 5.24. Schematic (a), SEM plain view (b) of current flow and transfer characteristic (VDS = 0.1V and 1V) of a direct-channel IGZO TFT (W/L = 4μm/200nm) right after FIB milling. ··· 120 FIG. 5.25. (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of a direct channel IGZO TFT (W/L = 4μm/200nm) after annealing in air at 200 ºC for 30 min. ··· 122 FIG. 5.26. (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of a direct channel IGZO TFT (W/L = 4μm/200nm) after annealing in air at 250 ºC for 30 min. ··· 123

FIG. 5.27. (a) Transfer characteristic (VDS = 0.1V and 1V), (b) output characteristics of a direct channel IGZO TFT (W/L = 4μm/200nm) after annealing in air at 300 ºC for 30 min. ··· 124 FIG. 5.28. Compare of gate leakage current for direct-channel TFTs and side-channel TFTs.

(a) The schematic of cross-section view of side-channel TFT (top) and direct channel TFT (bottom) after FIB milling, (b) the transfer characteristics for devices at VDS = 0.1V and 1V without annealing. ··· 126 FIG. 5.29. Transfer characteristics for direct-channel TFTs (W/L = 4μm/200nm) with thin IGZO (a) and thick IGZO (b) at VDS = 1V, after FIB milling and annealing in air at 300 ºC for 30 min. ··· 126 FIG. 5.30. Simulation result of electron density distribution of IGZO TFTs. The IGZO carrier density is 1.27×1017cm-3, VDS = 3V and VGS = 9V. ··· 128 FIG. 5.31. Compare of transfer characteristics for direct channel TFT (black) and one-side channel TFT (red). The direct channel device has channel thickness of 50 nm and W/L = 4um/200nm, the one-side channel device has channel thickness of 40 nm with W/L = 100nm/600nm. ··· 129 FIG. 5.32. Compare of gate leakage current for one side channel TFT (black) and direct channel TFT (red) without annealing (a) and after 300 ° C annealing in air for 30 min. ··· 131

FIG. 6.1. Schematic of Lloyd-mirror interferometer setup. Blue lines are the light from the laser and purple lines represent the reflected light from the mirror. ··· 134 FIG. 6.2. Images of 2D patterned photoresist arrays under optical microscope (a) and AFM (b). ··· 136 FIG. 6.3. Images of 2D patterned IGZO arrays under optical microscope (a) and AFM (b). ··· 137 FIG. 6.4. Image of color pattern after IGZO wet etching and electron beam evaporation of Titanium. ··· 137 FIG. 6.5. (a) Full layout of logic gate array mask design, including ITO (red), dielectric (yellow) and contact metal (blue). Bottom: (b) layout of inverter (c) layout of NAND (d) layout of NOR. ··· 138

FIG. 6.6. (a) Equivalent circuit schematic of inverter gate pixel and the corresponding SEM picture (b). ··· 140

FIG. 6.7. (a) SEM image of the function TFT of the inverter gate pixel in the array after FIB milling. (b) The cross-section view of the milled trench. ··· 141 FIG. 6.8. Transfer characteristics of the function TFT of inverter gate pixel in the logic gate array at various row selection voltages Vr. ··· 142 FIG. 6.9. Transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O2 at 250 °C for 20 min (a) and annealing in O2 at 300°C for 20min (b). ··· 143 FIG. 6.10. SEM image of the intersection of input line and row selection line. ··· 144 FIG. 6.11. Transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O2 at 350 °C for 20 min (a) and for 50min (b). ··· 145 FIG. 6.12. Transfer characteristics of the function TFT (W/L = 3μm (4μm)/200nm) after a annealing in O2 at 400 °C for 10 min. ··· 146 FIG. 6.13. Transfer characteristics of drain current (a) and gate leakage current (b) at vary row selection voltage Vr. ··· 147 FIG. 7.1. Schematic of isotropic wet etching profile for IGZO islands with larger size (top) and smaller size (bottom). ··· 153 FIG. 7.2. (a) The FIB milling stops in the metal layer. (b) The remaining metal is removed by selective etch. ··· 154

CHAPTER 1

INTRODUCTION

1.1

Overview

Transparent electronics is an emerging science and technology field focused on producing ‘invisible’ electronics circuitry and opto-electronics devices. For example, an automobile windshield could transmits visual information to the driver, such as GPS navigation, or act as the second screen of mobile device. Or imagine a glass including a transparent display displays image or video eliminating a TV or projector.

Two primary technologies are necessary to make transparent electronics and they are transparent conductive oxides (TCOs) and thin-film transistors (TFTs). TCOs must include two physical properties – high optical transparency and high electrical conductivity. The most common TCOs are indium oxide In2O3, tin oxide SnO2, and the alloy indium tin oxide. They are usually used as electrodes and other passive electrical applications.

The thin-film transistor (TFT) is another technology underlying transparent electronics, since it is the bridge between passive electrical and active electronic applications. The first ZnO-based TFT was announce in 1968 (Boesen and Jacobs) and more significant results were published around 2000. However, as ZnO exhibit high carrier density and low characteristic uniformity, people began to find substitutes. Hosono et al. [1, 2] predicted that amorphous oxides composed of heavy metal cations with an electronic configuration (n-1) d10ns0 (n ( 4) are promising candidate for semiconductors. These ns orbitals have larger radii, so that there is a large overlap between the adjacent orbitals, which leads to insensitiveness to the distorted metal-oxygen-metal chemical bonds. Based on above mentioned criteria, α-IGZO were successfully fabricated. High mobility of 7 cm2_{/V s and} high on/off ratio of more than five orders of magnitude were achieved even at room

temperature process. Ooctahedrical bonding of the indium leads to high conductivity. Zink provides chemical stability and incorporating Ga ions is crucial in α-IGZO for suppressing excessive carrier generation via oxygen vacancy. The large radius of the Ga also help the films to be amorphous rather than poly crystalline.

The appearance of α-IGZO also created significant worldwide interest in high-end LCD and AMOLED technology, both in industry and academia, because of its potential for high mobility, excellent uniformity in the device parameters, and good scalability to a large substrate size. Amorphous silicon (α-Si) TFTs, which are widely used a switching device for displays, have the advantages of uniformity and low fabrication cost. Their lower mobility (<1 cm2/V s), however, may be not sufficient to drive large-are AMOLED displays. The magnitude of electron mobility of α-IGZO is one or two orders higher (>10 cm2_{/V s) than} α_{-Si. Besides, the good transparency to visible light makes} α_{-IGZO more} suitable in display applications, thus it has been wildly used in next generation displays.

Transparent electronic device formed on flexible substrate is another emerging technology where silicon-based electronics cannot provide a solution for large area applications. Examples of active flexible applications include paper displays and wearable computers. So far, mainly flexible devices based on hydrogenated amorphous silicon (α -Si:H) and organic semiconductors have been investigated. However, the performance of these devices has been insufficient. Fabricating high-performance devices is challenging owing to trade-off between processing temperature and device performance. However, α -IGZO can be processed at room temperature or below 200 °C and the lower process temperature enable new approaches on a wider variety of substrates. TFTs fabricated on

polyethylene terephthalate sheets exhibit saturation mobility of 6-9 cm2/V s, and device characteristics are stable during repetitive bending of the TFT sheet [3].

In addition to the application in display and flexible electronic devices, other application for oxide TFTs have also been demonstrated. Some oxide semiconductors are sensitive to specific gases, light or humidity, which make them suitable for sensors for multiple applications [4, 5]. TOSs based TFTs have also been applied in solar cell [6], three dimensional integrated circuits and memory elements [7, 8].

1.2

Research Objective and Dissertation Organization

Though the transparent amorphous oxide semiconductor (AOS) have attracted attention as an active layer for next generation TFTs, a strong understanding of AOS physics, material and device processing issues, and especially the stability and reliability of AOS TFTs is needs before any applications can be commercialized. Understanding the mechanism of bias-induced threshold voltage shift is important to make α-IGZO based AOS TFTs more reliable and affordable. However, very limited work has been reported on how the trapped charge density changes with varying bias voltage and subgap density-of-states (DOSs). This dissertation combines the model of subgap density-of-density-of-states and interface or bulk trapped charge density to simulate the electrical characteristics of both long channel and short channel α-IGZO. This is provided to gain better understanding of the device stability.

The second objective of this dissertation is to fabricate submicron α-IGZO based TFTs using a new method, focused ion beam (FIB) milling. This is a quick, mask free approach that can be used to fabricate simple circuits. Proper milling strategies will be explored to create TFTs with desired channel dimensions.

One challenge in investigating small devices is to make small features. Electron beam is very time intensive lithography. For small samples, stepper is not suitable. Thus the third goal is to process the α-IGZO active layer for TFTs by using laser interference lithography to define the two dimensional active layer patterns for logic gate arrays. Patterning of the active layer is critical for fabricating short channel TFTs and compared with photolithography, laser interference lithography is potentially inexpensive.

The structure of this thesis is organized by the following.

Chapter 2 gives the brief review of literature related to amorphous oxide semiconductors, including development history of AOSs based TFTs, physical properties of α-IGZO and current AOS based devices and circuits. Description of thin film transistor device physics and laser interference lithography will be discussed to provide background knowledge for both simulation and experimental work presented in this dissertation.

Chapter 3 provides the description of technology computer aided design (TCAD) tools for simulation and experimental facilities used in process flow to make AOS TFTs, including thin film deposition, laser interference lithography and photolithography, reactive ion etching (RIE), focused ion beam, followed by a discussion on the electrical TFT characterization methodology and figures-of-merit.

Chapter 4 discuss the simulation results for both long channel α-IGZO TFTs and short channel device milled by focused ion beam (FIB) based on subgap density-of-states model, and compare it with the experimental results. A changing trend of trapped charge in both dielectric and at IGZO/SiO2 interface along with gate bias was extracted from the fitting of simulation to experiment result. It also simulates the moving mechanism of implanted ions from FIB milling.

Chapter 5 introduces the FIB technology used to modify device structure. It also presents the electrical characterizations of side-channel TFTs milled by FIB at different annealing temperature. Devices with different channel widths are demonstrated. The effects of beam quality and annealing temperature on the leakage current are also discussed. FIB milling provides a more flexible method to define TFTs with different structures. Table 1.1 shows the optional TFT structure that can be fabricated by using FIB milling. Structure (a) and (b) show that only side channel exist if IGZO pattern is wider than metal line and the FIB milling removes all the IGZO between drain and source. Structure (c) and (d) demonstrate that if IGZO pattern is narrower than metal line but FIB milling stops inside IGZO, only direct channel exist, and the channel thickness depends on the milling time. Structure (e) and (f) show that if IGZO is wider than metal line on one side and FIB milling stops in IGZO, both direct channel and one-side channel are created. Structure (g) and (h) presents that if IGZO is wider than metal line on both sides and FIB milling stops in IGZO, both direct channel and two-sides channel are created. In this work, structure (a) (b) (c) and (d) are fabricated and discussed.

Chapter 6 presents the laser interference lithography which explores ways to replaces the conventional photolithography or electron beam photolithography to define the α-IGZO active pattern as a step towards making a circuit using the focused ion beam method. The process flow of the inverter gate pixel is presented with device electrical characteristics demonstrated.

Table 1.1. Optional structures that can be fabricated by using FIB milling

The 2D array of IGZO islands patterned by laser interference lithography gives more flexibility to define the channel width by FIB milling. Strategies of channel milling are demonstrated in Figure 1.1. The metal covers five IGZO islands in vertical direction, if the milling path is along the dashed line as shown in Figure 1.1 (a) and (b), only three IGZO islands are included to form the channel. Assume the width of one IGZO island is W, the effective overall channel width can be 1W,2W,3W,4W and 5W based on the milling path, which provide high diversity in W/L ratio for TFTs. The second strategy are demonstrated in Figure 1.1 (c) and (d). The original milling cut five IGZO islands in a column as shown by dashed line, followed by a square milling which remove the center island and its surround metal, and the result channel length is 4W. This is good method for the post modification.

Chapter 7 summarizes the major achievements presented in this dissertation and discusses the suggestions for future work.

FIG.1.1. Schematic of different milling strategies to modify the effective width of TFTs with IGZO islands patterned by laser interference lithography.

CHAPTER 2

LITERATURE REVIEW AND

BACKGROUND

This chapter reviews the fundamentals of α-IGZO devices. Basic device structure and operation of TFTs are introduced, followed by a discussion of amorphous oxide semiconductors. The potential for α-IGZO TFTs integrated circuit is also explored. Since device stability is important, the subgap density-of-states model is discussed. The final part of this chapter presents the basic of laser interference lithography, which is used to facilitate the patterning of α-IGZO active layer without conventional photolithography or electron beam lithography.

2.1

Thin Film Transistor

2.1.1 Background and History

The TFT was invented in 1925 and patented in 1930 by J.E. Lilienfeld [9-11]and O. Heil [12]. However, the first TFT was produced after one more decade by Weimer at the RCA Laboratories in 1962 [13-15] when semiconductor and the vacuum techniques necessary for the thin film deposition were developed. These initial n-type TFTs used a top-gate staggered structure with microcrystalline CdS deposited by evaporation as the channel layer. Thermally evaporated SiO was used as the gate dielectric and gold was applied for gate electrode and drain and source contacts. With the channel length of 5 to 50 μ was used as the gate field-effect mobilities on the order of 1.1 cm2/Vs and drain current on/off ratio of 101. The early TFT were also made of CdSe with high field effect mobility, µeff, e.g., > 40 cm2_{/Vs, and the CdSe TFT LCD was first demonstrated in 1973 [16].}

However, due to difficulties in controlling the compound semiconductor thin film material properties and device reliability over large area, this technology was never mass produced. These reliability issue was resolved when the first functional TFT with hydrogenated amorphous silicon (α-Si:H) as the channel layer was made in 1979 [17]. The simple fabrication process made it suitable device for mass production, and it is still the most dominant TFT technology currently. However, α-Si the mobility is too low for high-speed or large-current applications, such as the driving circuit of the display or the driving pixel in the organic light emitting diode (OLED) displays. Α Si:H is a photoconductor at visible wavelengths, the TFT has large leakage current under light exposure.

Amorphous and crystalline metal oxide TFTs (oxide TFTs) have attracted tremendous attention recently due to the high mobilities. The oxide semiconductor TFT dates back to the mid-1960s [18, 19] and only poor electrical performances were obtained from TFT device based on SnO2 [20], until reports on ZnO TFTs by Hoffman et al, Carcia et al. and Masuda et al appeared in 2003. Hoffman and Carcia reported fully transparent devices with performance comparable and even better in some aspects than the α-Si: H and organic TFTs. The single-crystal ZnO shows large Hall mobility as high as 200 cm2/Vs. The later work from Carcia et al. even demonstrated the availability of ZnO by using r.f. magnetron sputtering.

However, the channel of ZnO TFTs is polycrystalline if deposited at room temperature, and, therefore, the long-term stability and uniformity suffer from grain-boundary problems, which is also the common issue for polycrystalline silicon (p-Si). Another critical issue of ZnO and other oxide semiconductor is their high concentration of mobile electrons

(typically >> 1018 cm-3) which make the control of threshold voltage and off-current difficult.

To solve these problems, Nomura et al. suggested in 2003 to use a complex InGaO3(ZnO)5 (or IGZO) single-crystalline semiconductor layer in a TFT [21]. Though a very high temperature of 1400 ° Cwas needed, it showed high mobility of 80 cm2/V s and high on/off ratio of 106, and made the high-performance oxide semiconductor-based TFT possible. In the following year, they improved the work by depositing amorphous IGZO as channel layer through PLD at near-room temperature. Though the mobility of 9 cm2/V s and on/ off ratio of 103 _{were far from the single-crystalline TFTs, the amorphous TFT is} an impressive achievement because its low sensitivity to crystal structure disorder and better uniformity than crystalline oxide semiconductor over large areas.

2.1.2 Device Structure

Figure 2.1 illustrates typical device structures used for TFTs. Based on the stacking order of the gate electrodes, channel layer and source/drain electrodes, the TFT structures and be classified into top/bottom gate and top/bottom contact. The top-gate structure is employed when it is difficult to form a bottom electrode. This structure has other advantages. For example, it only require two patterning mask steps at minimum, and the top gate electrode and insulator layer can also act as passivation layer that protect the channel layer from water/oxygen absorption and desorption due to atmospheric exposure. Bottom-gate structures are common in laboratory research because commercially available oxide/substrate wafer can be used as the insulator and bottom gate electrode. Furthermore, usually insulator layer is deposited at high temperature; depositing insulator layer first will not affect the semiconductor channel layer. But the disadvantage of this structure is also

apparent. First, the top-channel is exposed to the atmosphere and causes the instability in device characteristics. Second, the overlap between bottom gate electrodes and source/drain electrodes are very large, and the charge and discharge process takes long time due to the large parasitic capacitance and lower the device working frequency. Based on the relative location between source/drain contact and semiconductor/insulator interface, the structure can be classified into planar structures and staggered structures. In the co-planar structure, the source/drain contacts are on the same level with semiconductor/insulator interface where conducting channel forms. This structure benefits the lower resistance because the source/drain electrodes directly contact with the induced conducting channel. For stagger structures, source/drain contacts and semiconductor/insulator interface lay on the opposite sides of semiconductor film. For this structure, current from electrodes needs to go through the resistive film vertically to reach the induced channel. The staggered structure also provides a large contact area for charge injection.

FIG. 2.1. Schematics of some of the most conventional TFT structures, according to the position of the gate electrode and to the distribution of electrodes relatively to the semiconductor [22].

2.1.3 Basic Device Operation

TFTs are three terminal field-effect devices, whose working principle relies on the conducting channel modulation by a gate electrode with the modulated current flowing in the channel between source and drain contacts. TFTs work similarly to other field-effect device such as metal–oxide–semiconductor field-effect transistor (MOSFETs). In MOSFETS, a doped silicon wafer acts as both the substrate and the active semiconductor. An inversion region is formed close to the dielectric/semiconductor interface, i.e., a n-type conductive layer is created in a p-type silicon substrate. TFTs can use an insulating substrate, normally glass, and the conductance of the semiconductor is achieved by an accumulation layer. In this section, a TFT with n-type semiconductor is used to explain the device operation principle under n channel accumulation mode.

Figure 2.2 shows the cross-section view of the TFT structure and the energy band diagram of the device at different gate biases. Some assumptions are made before the discussion. In this example, the semiconductor is slightly n type. A similar discussion is also available for p type TFTs. There is no charge trapped in dielectric and semiconductor or at dielectric/semiconductor interface. The semiconductor and gate electrode have the same work function, which guarantee that no accumulation or depletion is appeared at 0 gate bias.

Figure 2.2 (b) shows the energy band diagram at equilibrium, where no external voltage is applied on the gate electrode. As the work function of semiconductor and gate electrode are equal, Fermi level of semiconductor is aligned with gate electrode work function, the energy band is not bent.

When a positive gate bias is applied, the external electric field attracts mobile electrons inside the semiconductor to accumulate at the dielectric/semiconductor interface, which acts as the conducting channel layer. This can also be explained by the band diagram of Figure 2.2 (c), where a positive gate voltage lower the gate electrode energy band relative to semiconductor, which bends semiconductor the conduction band downward more close to the Fermi level. The smaller space between conduction band minimum and Fermi level at the interface region demonstrates that more electrons are accumulated above conduction band. This corresponds to the “on” state of the device.

On the other hand, when a negative gate bias is applied on the gate electrode, electric field pushes the mobile electrons away from the dielectric/semiconductor interface and forms a thin layer of depletion region. From the view of band diagram, negative external electric field by gate bias higher the gate electrode work function relative to the

semiconductor energy band, which bends the semiconductor conduction band upward away from the Fermi level. This larger space between conduction band minimum and Fermi level in semiconductor at the interface region means less mobile electrons exist, leaving only ionized donor and positive space charges. The width of the depletion region increases along with the rising magnitude of the negative gate bias, and the entire semiconductor layer can be fully depleted. In this case, no conduction channel layer exist between drain and source contacts and the device is in “off” state.

Enhancement mode transistor is always desired in the circuit design, which is always in off state with zero gate bias. To make the TFTs in enhancement mode, a relatively low carrier concentration and thin channel are necessary, as a very negative gate voltage is needed to fully depleted the channel and turn off the device if the carrier concentration is high, or the channel is too thick.

(a) (b) (c) (d)

FIG. 2.2. The TFT structure and energy band diagram as viewed through the gate: (a) the cross-section structure of TFT, (b) at equilibrium, VGS=0, (c) accumulation mode, VGS > 0, (d)

depletion mode, VGS < 0.

The operation of enhancement mode TFT can be separated into two different modes, depending on the voltages at the terminals. When the gate bias is high enough to establish the accumulation layer and turn on the device, a positive voltage between drain and source (VDS>0) creates current flow. When the drain voltage is small compared with gate voltage, the channel charge density is fairly uniform from the source to the drain, and the drain current increases linearly with respect to VDS at a given VGS, so this is the so called “linear” region. This is the TFT operates like a resistor, and the resistance depends on the channel charge density, which is a function of the gate bias (VGS). In the linear region (VDS<VGS-Vth), the current from drain to source is modeled as below:

𝐼𝐼

=

𝜇𝜇

𝐶𝐶

�

(

𝑉𝑉

− 𝑉𝑉

)

𝑉𝑉

−

2

2

�

Where μFE is the charge-carrier effective mobility, W is the gate width, L is the gate

length and Cox is the gate oxide capacitance per unit area. When VDS is very small, the

second term in the parenthesis can be neglected, and the drain current is linearly proportional to VDS at a given gate voltage VGS.

As VDS increases, the accumulation-layer charge density at the drain end of the channel is reduced; therefore, drain current does not increase linearly with VDS. When VDS reaches VGS-Vth, the channel is “pinched off” at the drain end, and drain current ID saturates. Further increase in drain voltage does not result in higher drain current, and the device is operating in “saturation” region. In the saturation region (VDS>VGS-Vth), ID is described by

𝐼𝐼

=

𝜇𝜇

𝐶𝐶

(

𝑉𝑉

− 𝑉𝑉

)

For saturation mode, 𝜇𝜇_{𝑠𝑠𝑠𝑠𝑡𝑡} represents the average of the carrier mobility including both the accumulation region and pinch off region. The two equations above are only available

for ideal TFTs, in real cases, μsat and μsat always depend on VGS because of other factors such as interface traps or Coulomb scattering.

2.2

Electronic Structure of Amorphous Oxide Semiconductor (AOS)

Amorphous semiconductors are preferred over crystalline or polycrystalline semiconductors as active layers mainly because the low processing temperature and uniformity of the device characteristics. However, the carrier mobility of α-Si:H is limited to ~1 cm2_{/V s, which is lower by two or three orders of magnitude than that of} single-crystalline Si (~200cm2/V s for carrier concentration ~1019 cm-3). In silicon, the conduction band minimum (CBM) and valence band maximum (VBM) are made of the anti-boding (sp3σ_{*) and bonding (sp}3σ_{) states of Si sp}3 _{hybridized orbitals, and the band gap is formed} by the splitting of these two energy levels (Figure 2.3 (a)). The sp3 orbitals have strong spatial directivity, thus in amorphous silicon, even small fluctuation in the chemical bounds results in high-density tail localized states in the forbidden band, which trap carriers (Figure 2.3 (e)). The carrier transport controlled by hoping between localized tail-states and band conduction is not achieved, which cause the low mobility in α-Si. By contrast, amorphous oxide semiconductors have strong ionicity and the electrons transfer from the s orbitals of metal atoms to 2p orbitals of oxygen atoms (Figure 2.3 (b)). The Madelung potential formed by these ions raises the energy levels in cations and lower the levels in anions and creates the VBM by unoccupied s orbitals in metal cations and CBM by fully occupied 2p orbitals in oxygen anions (Figure 2.3 (c)). The unoccupied s orbital metal cations are spherically extended and can easily overlap with another s orbital from the neighboring metal cations (Figure 2.3 (f)). The spherical orbital is not direction sensitive and the electron transport is not effected by the local structure disorder.

FIG. 2.3. Schematic electronic structure of silicon and ionic oxide semiconductors. (a-c) Bandgap formation mechanisms in (a) covalent and (b,c) ionic semiconductors. (d-g) Carrier transport paths in (d) c-Si, (e) α-Si , (f) crystalline oxide and (g) amorphous oxide [23].

2.3

Indium Gallium Zinc Oxide (IGZO)

As discussed in section 2.2, amorphous oxide semiconductor is the ideal candidate for active layer with high mobility and excellent large-area uniformity. However, Figure 2.4(a) shows that for binary oxide materials, such as pure ZnO and In2O3, only crystalline films can be formed even when deposited at room temperature. One of the principles of forming amorphous materials is mixing multi-components with different crystal structures. For example, In2O3 and ZnO have bixbyite and wurtzite structures, respectively, this allow

Zn-Oxide (ZO) to have an amorphous phase. Oregon State University and Hewlett-Packard have reported the fabrication of a-Zn-Sn-O (a-ZTO) TFTs [24] and Zn-In-O (a-ZIO) TFTs [25] with very high mobility up to 55 cm2/V s.

Even though a-IZO meet the requirement of excellent uniformity and large mobility, one crucial issues with this material is that it exhibits a high carrier concentration of >1017cm-3, which can lead to large off-current and small on-off ratios [26, 27]. The high carrier density origin from the oxygen vacancy in semiconductors, thus incorporating ions with high ionic potential to form strong chemical bond with oxygen ions and suppress the formation of oxygen vacancies should be the solution. Nomura et al. inserted Ga into IZO and demonstrated that the carrier concentration of α-IGZO can be lowered below <1017cm -3 _{while contain high electron mobility (~10 cm}2_{/V s). Figure 2.4(b) shows that} α _-IZO (bottom of the pyramid) has higher electron mobilities than α-IGZO (top of the pyramid). Thus, incorporating certain portion of Ga3+ is critical to reduce the carrier concentration. Besides, Ga also helps keep the film in amorphous states due to its large atom radius.

(a) (b)

FIG. 2.4. (a) Amorphous formation and (b) electron transport properties of In2O3-Ga2O3-ZnO thin

films. The values in (b) denote the electron Hall mobility (cm2_{/V s) with density (10}18 _cm-3_{) in}

parentheses [28].

Table 2.1 summarizes the current TFT technologies, and shows that α-IGZO is the only candidate that can achieve the balance between high mobility, low carrier concentration and large area uniformity. This implies a good choice to replace α-Si for future generation displays.

Table 2.1. Comparison of several materials used in displays [29].

Figure 2.5 (a) shows the crystal structure of InGaZnO4 and Figure 2.5 (b) shows the calculated density-of-states (DOS) distribution of InGaZnO4. As the VBM is located at zero energy level, the valence band is mainly formed by Zn-3d and O-2p orbitals and the conduction band (peak at lower energy level above 0) contains the s orbital of In, Ga and Zn ions. The location of In-5s orbital energy is lower than the other two ions, thus the CBM origins from the In ions. Nomura et al. subsequently confirmed this conclusion by calculating α-IGZO electronic structure through pseudopotential and plane wave method at the local-density approximation (LDA) level [30].

(a) (b)

FIG. 2.5. (a) (Color) Structure of the InGaZnO4 crystal. The brown, blue and red balls represent In,

Zn/Ga and O atoms, respectively. (b) Partial density-of-states (DOS) curves for InGaZnO4 crystal

structures. The top of the valence band is located at zero energy and total DOS is also shown in each figure as reference. (After Orita et al., Ref [31])

IGZO also exhibits unusual carrier transport properties as shown in Figure 2.6 (a) compared with other crystalline semiconductors: The maximum Hall mobility is similar for crystalline IGZO and α-IGZO a and its electron mobility increase with increasing free-electron density. The first property is explained earlier that as the CBM is formed by s orbital of metal cations which are insensitive to the structure disorder, thus the amorphous phase of IGZO will not affect the overlap of orbitals between neighboring metal cations. Second property is explained by a percolation conduction model [32] as shown in Figure 2.6. It assumes that carrier transport is controlled by distributed potential barrier above CBM with the average height of Ecenter and the energy distribution of ΔE. These values are

summarized in Figure 2.6 (b), showing that Ecenter are 30-100 meV and ΔE are 5-20 meV. As illustrated in Figure 2.6(c), electrons take shorter transport path at high temperature even if these paths have high potential barrier (path (i) in Figure 2.6 (c)). They tend to take longer path (ii) with lower barrier at lower temperatures because the kinetic energy is not sufficient to pass though the higher barriers.

(a) (b) (c)

FIG. 2.6. (a) Hall mobilities of InGaO3(ZnO)m as function of electron density.IGZO1 and

c-IGZO5 represent crystalline phases with m = 1 and 5, respectively. HQ and LQ denote high-quality and low-quality, respectively. (b) Potential distribution above CBM analyzed based on percolation transport model [33]. (c) Illustration to explain the percolation conduction model [34].

2.4

Modeling and Simulation of

α

-IGZO TFT

Although the fundamental transport properties and electronic structures of α-IGZO has been studied, the subgap density of states (DOSs) also plays important role in amorphous semiconductor. Recently, published papers have proposed technology computer-aided design (TCAD) device simulators to reproduce the measured current-voltage characteristics by modeling subgap density of states with proper fitting parameters [35-37].

The subgap Density of states-based Amorphous Oxide TFT Simulator (DeAOTS) is proposed [36] based on previous work on the α Si:H TFT model[38-42]. The model contains two components: the acceptorlike conduction band-tail states (gCBa) and the acceptorlike deep-gap states (gDa). Such tail states is formed by the structural disorder within an amorphous material which can induce electron scattering and localize the wave function [43, 44]. In α-IGZO , this band-tail states origins from the disorder of metal ion s-orbitals, while the ionized oxygen p-orbitals behaves as the valence band-tail states (gVBd). The deep states in α-IGZO is formed by the oxygen vacancy (OV). It has been pointed out that OV can act like a donor and locates close to the conduction band minimum (CBM) if post-thermal annealing or propr film growth process is applied. It also has a Gaussian distributed states gGd. The three types of subgap states, conduction band-tail states (gCBa), the valence band-tail states (gVBd) and OV donor-like deep states (gGd) are given by the following expressions [45]:

𝑔𝑔

=

𝑔𝑔

exp[(

𝐸𝐸 − 𝐸𝐸

)/

𝐸𝐸

],

𝑔𝑔

=

𝑔𝑔

exp[(

𝐸𝐸

− 𝐸𝐸

)/

𝐸𝐸

]

,

𝑔𝑔

=

𝑔𝑔

exp[

−

(

𝐸𝐸 − λ

)

/

𝜎𝜎

],

densities of acceptor- and donorlike states at E=EC and E=EV, respectively, Ea and Ed are

characteristic slope of conduction and valence band-tail states, respectively, and gd, λ and

𝜎𝜎 are the peak value, the mean energy, and the standard deviation of states, respectively. Figure 2.7 (a) shows the proposed density of states (DOS) model for α-IGZO. By fitting the parameters from experiment, simulated result shows good consistency with experiment result as shown in Figure 2.7 (b) (c). Reports [46]also indicate that the location of donorlike

states is important. If the location of donorlike states is much higher than the intrinsic Fermi-level, then all donorlike states are ionized and induced electrons by gate voltage need to fulfill the ionized donorlike states before entering the subthreshold region to fill the band-tail state. Thus wider or higher donorlike states distribution will shift the threshold voltage. While for band-tail states, higher DOS results in lower current but no change to the threshold voltage. This suggests that both the energy locations of OV states and DOSs of band-tail states and donorlike states should be properly controlled to achieve a high performance α-IGZO TFT.

FIG. 2.7. (a) Proposed DOS model for α-IGZO. 2. EC and EV are conduction and valence band edge

energies, respectively. Solid curves within the bandgap represent the exponentially distributed band-tail states (gCBa, gVBd), while the dash curve near the conduction band edge represents the

Gaussian-distributed donorlike OV states (gGd). (b) and (c) Transfer characteristics (W/L=180/30

μ. ( Both experimental (circle) and simulation data (solid line: Schottky contact; +: Ohmic contact)

are shown. Extracted threshold voltage (Vth), field-effect mobility (μeff), and subthreshold swing (S)

are also indicated. Inset of (c): the 2D TFT structure used in simulation.

Based on this model, Jeong and Hong [47] examined the Debye length and active layer thickness-dependent performance variations of α-IGZO TFT. Figure 2.8(a) shows the threshold voltage Vth and on/off ration as function of semiconductor thickness for different free carrier density ND. For the depletion mode TFT (ND = 1016 cm-3), Vth is shifting to

positive direction slightly with increasing thickness as more ionized donorlike states (electron trap) need to be filled by induced electrons before free electrons can form a conducting layer. For enhancement mode TFT (ND > 1016 _cm-3_{), intrinsic free carrier} density is high, which makes increase the off current and lower the on/off ratio. Besides, larger negative gate voltage is needed to deplete the free electrons from the active layer, which shift the Vth to negative direction. Figure 2.8(b) and (c) shows the compare of band profile of TFT between active layers with thickness d=150 nm and d = 200 nm. When free carrier density is high, to deplete the electrons through the whole semiconductor, Fermi level needs to be pull down away from the conduction band. However, due to the existence of donorlike states, Fermi level is pinned near the envelope of donorlike deep states.

FIG. 2.8. (a) VTH and on/off ratio as a function of semiconductor thickness for different ND. Band

profile of TFTs with (b) d =150 nm and (c) d = 200nm. The QFL is close to the conduction band edge when high negative voltage is applied to gate electrode for d = 200nm.

In fact, this threshold thickness dTH is closely related to Debye length lD because lD determines the maximum potential transfer length through the semiconductor layer when bias is applied. Since the Debye length is a function of both free carrier density ND and the

average amount of donorlike deep sates NS, qualitative calculation is performed to relate

dTH to ND and NS:

𝑑𝑑

∝ 𝑙𝑙

=

�

𝐷𝐷+𝑁𝑁𝐷𝐷_{𝑘𝑘𝑘𝑘}�

(2.6)

All simulated results indicate that the active layer thinner than dTH is essential for high-performance α-IGZO TFTs. To achieve that goal, intrinsic free carrier density as well as donorlike deep states should be carefully optimized.

2.5

Fundamentals of IGZO TFT

For this section, we overview the fundamental issues in IGZO TFT performance and fabrication process.

2.5.1 Contact Electrode

In order to reduce the response time of the circuit, the resistance of source/drain electrodes should be minimized. Y. Shimura et al. measured and compared the contact resistance between IGZO and various metallic electrodes, including Ag, Au, In, Pt, Ti, ITO, and IZO [48]. All the materials except Au and Pt exhibited a linear relation of current-voltage characteristics, while Au and Pt resulted in Schottky contacts. Among these materials, Ti and ITO are the best electrodes. The contact resistance also strongly depends on the carrier density of the channel surface, therefore, treatments such as Ar plasma treatment [49] have been employed to improve the contacts. Multilayer electrodes structures such as Ti/Au and Ti/AL/Ti are also used for electrodes, Au layer protects the bottom reactive contacting metal while Ti layer improves the adhesion of the whole contact and reduces the resistivity.

2.5.2 Gate Dielectric Materials

The effects of gate dielectric in contact with the semiconductor are also important. Silicon oxide and silicon nitride have been most widely used as gate dielectric for both oxide semiconductor TFTs and conventional Si-based transistors. Α-IGZO TFTs with SiOx gate dielectric shows better threshold voltage stability compared with SiNx due to the higher hydrogen content in SiNx films providing more charge trap sites, which would produce a high shallow hydrogen-related states. Besides, the valence offset between the