Architetture di bus per
Architetture di bus per
System
System
-
-
On
On
-
-
Chip
Chip
Massimo Bocchi
Massimo Bocchi
Corso di Architettura dei Sistemi Integrati
A.A. 2002/2003
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
System
System
-
-
on
on
-
-
chip motivations
chip motivations
Growing transistor count
Growing transistor count
on a single chip
on a single chip
Implementation of a
Implementation of a
greater number of
greater number of
functionalities
functionalities
New technologies
New technologies
integrated on the same
integrated on the same
chip
chip
98 00 02 04 06 08 10 Logic SRAM E-DRAM CMOS RF FPGA FRAM MEMS Chemical sensors Electro-optical Electro-biological Flash Transistors (Millions)/Chip 19971999 2001 2003 2005 2007 0 400 200 300 100 2009 Technology (nm)Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
Intellectual property reuse
Intellectual property reuse
Design complexity
Design complexity
–
–
High number of components
High number of components
–
–
Integration of different
Integration of different
technologies
technologies
Critical
Critical
Time
Time
-
-
to
to
-
-
market
market
Low cost design
Low cost design
“
“
Semiconductor intellectual
Semiconductor intellectual
-
-
property designers strive to ensure
property designers strive to ensure
their IP can be used by the widest possible range of application
their IP can be used by the widest possible range of application
s to
s to
ensure maximum return on their engineering investment.”
ensure maximum return on their engineering investment.”
Ed Smith (Sonics Inc.), 2002
Intellectual
Intellectual
-
-
property (IP)
property (IP)
Reuse, among other
Reuse, among other
design technologies, has
design technologies, has
generated the higher
generated the higher
productivity increase.
productivity increase.
IP
IP
-
-
Reuse evolution
Reuse evolution
Small blocks reuse
Small blocks reuse
(registers, multiplexer, adders,
(registers, multiplexer, adders,
multipliers, shifters, …)
multipliers, shifters, …)
Large blocks reuse
Large blocks reuse
(embedded processors, memory controllers,
(embedded processors, memory controllers,
I/O interfaces, DMA controllers, …)
I/O interfaces, DMA controllers, …)
System reuse
System reuse
(suitable for multiprocessor systems development,
(suitable for multiprocessor systems development,
networks
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
IP vs. IC
IP vs. IC
IP
IP
-
-
based design
based design
IC
IC
-
-
based design
based design
The whole system is
The whole system is
implemented on a single chip
implemented on a single chip
All the components are placed on
a board
All the components are placed on
a board
The basic components are
The basic components are
described using a hardware
described using a hardware
description language (HDL)
description language (HDL)
The basic components consist of
The basic components consist of
several integrated circuits
several integrated circuits
The components are collected
The components are collected
into IP
into IP
-
-
libraries
libraries
The components are collected
into IC
The components are collected
into IC
-
-
libraries
libraries
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
Bus architectures
Bus architectures
A bus architecture specification provides:
A bus architecture specification provides:
interfaces for the components placed on
interfaces for the components placed on
the bus
the bus
protocols for on-
protocols for on
-chip communication and
chip communication and
signals transmission
signals transmission
architectural description of the hardware
architectural description of the hardware
connections between the peripherals
connections between the peripherals
included into the system
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
Bus architectures
Bus architectures
How bus architectures can improve SoC design:
How bus architectures can improve SoC design:
Standard interfaces support IP
Standard interfaces support IP
-
-
Reuse
Reuse
methodology allowing the creation of
methodology allowing the creation of
Plug and
Plug and
Play
Play
cores
cores
SoC designs are more reliable if based on a
SoC designs are more reliable if based on a
standard bus architecture
standard bus architecture
Test methodologies can be improved and
Test methodologies can be improved and
supported by standard test interfaces
supported by standard test interfaces
Cost reduction for verification tasks
Cost reduction for verification tasks
Bus
Bus
architectures
architectures
comparison
comparison
WISHBONE
WISHBONE
AMBA
AMBA
CoreConnect
CoreConnect
System and
System and
peripheral
peripheral
bus
bus
–
–
Power
Power
consumption
consumption
reduction
reduction
–
–
Performance
Performance
increase
increase
De facto
De facto
standard
standard
for
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
AMBA
AMBA
specification
specification
AMBA is
AMBA
is
an
an
open standard
open standard developed
developed
by
by
ARM
ARM Ltd
Ltd.
.
(
(
www.arm.com
www.arm.com
)
)
A typical AMBA-
A typical AMBA
-based SoC consists of a high
based SoC consists of a high
performance system bus (AHB) and peripheral bus (APB)
performance system bus (AHB) and peripheral bus (APB)
A standard test methodology
A standard test
methodology
is
is
included
included
in the AMBA
in the AMBA
specification
specification
The full AHB specification is contained in the AMBA 2.0
The full AHB specification is contained in the AMBA 2.0
documentation
documentation
AHB-
AHB
-Lite is a subset to the full AHB specification
Lite is a subset to the full AHB specification
Multi-
Multi
-layer AHB is an
layer AHB is an extension
extension
to
to
the AHB
the AHB protocol
protocol,
,
providing
providing
parallel
parallel
communication
communication
paths
paths
between
between
masters
masters
and
and slaves
slaves
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
A typical AMBA
A typical AMBA
-
-
based SoC
based SoC
Massimo Bocchi Massimo Bocchi High performance processor High Bandwidth On-chip Memory interface DMA bus master B R I D G E High Bandwidth On-chip Memory interface
Timer
Timer
UART
UART
AHB bus
APB bus
Arbiter
Display
Display
controllers
controllers
Test InterfaceMassimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
AMBA AHB
AMBA AHB
main
main
features
features
Pipelined
Pipelined
operation
operation
Multiple bus masters
Multiple bus
masters
Burst
Burst
transfers
transfers
Split transactions
Split
transactions
Non-
Non
-tristate implementation
tristate implementation
Wide data bus configurations (up to 128
Wide data bus configurations (up to 128
bits
bits)
)
AMBA APB
AMBA APB
main
main
features
features
Low
Low
power consumption
power
consumption
Simple
Simple
interface
interface
Latched address
Latched
address
and control
and control
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
AHB single transfer
AHB single transfer
HREADY
HREADY
HCLK
HCLK
HADDR &
HADDR &
Control
Control
HRDATA
HRDATA
A
Data (A)
Data (A)
HWDATA
HWDATA
The
The addressed
addressed
slave can
slave can insert
insert
one or more wait
one or more
wait
cycles
cycles
if
if
the
the
data
data phase
phase
has
has
to
to
be
be
delayed
delayed
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
AHB
AHB
masters
masters
states
states
IDLE
NONSEQ
SEQ
BUSY
no no transferstransfers oror busybusybusbus new
new burstburstor single transferor single transfer
no no transferstransfers burst burst transfer transfer single single transfer transfer burst burst transfer transfer no no transfers transfers ready
readyforfortransfertransfer
not
notreadyreadyforfortransfertransfer
single single transfer transfer
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
AHB
AHB
slaves
slaves
responses
responses
OKAY
OKAY
: the transfer
: the transfer
has
has
been
been
completed
completed
successfully
successfully
ERROR
ERROR
:
:
there
there
was
was
an
an
error
error
during
during
the transfer;
the transfer;
the master
the master
should
should
reinitiate
reinitiate
the transfer
the transfer
RETRY
RETRY
:
:
the slave
the slave
has
has
not
not
yet
yet
completed
completed
the
the
transfer; the master
transfer; the master
should
should
retry
retry
a new transfer
a new transfer
SPLIT
SPLIT
:
:
the slave cannot complete the transfer
the slave cannot complete the transfer
immediately;
immediately;
another
another
higher
higher
-
-
priority
priority
master can
master can
get
get
access
access
to
to
the bus and the
the bus and the
current
current
transfer
transfer
will
will
be
be
completed
completed
later
later
Burst
Burst
transfers
transfers
16-beat incrementing burst
INCR16
16-beat wrapping burst
WRAP16
8-beat incrementing burst
INCR8
8-beat wrapping burst
WRAP8
4-beat incrementing burst
INCR4
4-beat wrapping burst
WRAP4
Incrementing burst of unspecified length
INCR
Single transfer
SINGLE
Description
Description
Type
Type
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
AHB bus interconnection
AHB bus interconnection
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
APB
APB
transfers
transfers
The BRIDGE operates
The BRIDGE
operates
signal
signal
conversions
conversions
from
from
the AHB protocol
the AHB
protocol
to
to
the APB one
the APB one
APB features a very simple communication
APB features a very simple communication
protocol
protocol
APB slaves cannot insert any wait cycle;
APB slaves cannot insert any wait cycle;
the duration of transfers
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
APB state
APB state
diagram
diagram
IDLE
SETUP
ENABLE
no no transfer transfer transfer transfer transfer transfer no no transfer transferAHB
AHB
-
-
Lite
Lite
specification
specification
Only
Only
one bus master
one bus master
is
is
supported
supported
The resulting system can be:
The resulting system can be:
–
–
a simple system containing only one bus master
a simple system containing only one bus master
–
–
a Multi
a Multi-
-layer AHB system containing only one bus
layer AHB system containing only one bus
master per layer
master per layer
AHB
AHB
-
-
Lite simplifies the full AHB
Lite simplifies the full AHB
specification
specification
:
:
–
–
no arbitration is required, since the Request/
no arbitration is required, since the Request/Grant
Grant
protocol
protocol
is
is
not
not
used
used
–
–
the AHB
the AHB slaves
slaves
don’
don’t
t have
have
to
to
support
support
Split/Retry
Split/
Retry
responses
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
Multi
Multi
-
-
layer
layer
AHB
AHB
specification
specification
Parallel
Parallel
paths
paths
connecting
connecting
more
more
than
than
one
one
master/slave
master/slave
Each layer can use a simplified architecture
Each layer can use a simplified architecture
based
based
on the
on the
AHB
AHB
-
-
Lite
Lite
protocol
protocol
Arbitration is distributed in each slave that can
Arbitration is distributed in each slave that can
be accessed by more than one master
be accessed by more than one master
simultaneously
simultaneously
An interconnect matrix is implemented using
An interconnect matrix is implemented using
several multiplexer to select
several multiplexer to select
only
only
one master
one master
input
input
for
for
each
each
slave
slave
Massimo Bocchi,
Massimo Bocchi, 07/02/200307/02/2003 ARCES ARCES --University of BolognaUniversity of Bologna
