REDUCTION OF TIME PERIOD IN ROM USING CONSTANT DELAY LOGIC STYLE TECHNIQUE

REDUCTION OF TIME PERIOD IN ROM USING

CONSTANT DELAY LOGIC STYLE TECHNIQUE

T.ARVEEND1 NARESH SURABU2 SURESH H. BALLALA3 1

M.tech IInd year student, ECE, Sri Indu Institute of Engineering and Technology

2

Assistant professor, Department of ECE, Sri Indu Institute of Engineering and Technology

3

HOD, Department of ECE, Sri Indu Institute of Engineering and Technology

ABSTRACT: A constant delay (CD) logic style is proposed in this paper, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. In VLSI, depending on the necessity and requirement various technologies have been invented and are used accordingly. The most used is CMOS logic style is the one by which the all the basic and important constraints are traded off. But later the uses and necessities have improved in the research field. For example in some industries power is not the basic constraint and only speed is the major objective, there the technology which may consume more power and is also may not be economical, but if speed is acquired with less delay that I enough.

Due to such conditions various other technologies have been invented based on various needs such as pseudo nMOS logic, dynamic domino logic etc. A new logic style named constant delay logic style has been invented only to reduce the delay between the input and output thus increasing the speed of the circuit. This logic style is implemented on logic gates and adders. It has shown a drastic reduction in delay, that is increase in speed. This logic style is further implemented in designing ROM a storage device using two 3*8 decoders. ROM is designed in three logic styles namely static CMOS, Dynamic domino and CD logic styles respectively. In all possible combinations the delay is tabulated and normalized. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speed up of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates39% speedup and 64% (22%) energy-delay product (EDP)reduction from static logic at 100% (10%) data activity in32-bit carry look ahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% ED Prediction across all data activities. Then the delay is compared between three logic styles and results note that CD logic style is 48% faster than dynamic domino and 82% faster than CMOS logic style.

1. Introduction:

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC makers add all of these into one chip. The present challenges in the VLSI networks are area, power and speed. The area and power constraints are mainly over-comed by CMOS logic style. Even though majority usage makes the power consumption a main constraint, there are also areas where speed is the sole objective. Hence to achieve that new logic styles have been invented to increase the speed in the VLSI circuits and also overcome many disadvantages. But here power is not a major constraint; the new logic styles consume large power than CMOS logic style.

1.1 Working:

There are two 3*8 Decoders where each decoder has three inputs and eight outputs. Eight input combinations are possible for each decoder. For each input combination one output pin will be enabled. Same is the process for second decoder also. The eight pins of first decoder and eight pins of second decoder are overlapped but not interconnected. After overlapping there are 64 pins and they are programmed according to our own wish using switches or nMOS transistors. Here the programming is done using the nMOS transistors. The output position according to the two decoder combinations where we want Logic1 can be left alone without any transistor connections. Where ever we want the pin combination to be programmed Logic0 there we have to connect transistor. The output wire from first decoder goes as input to the transistor. The output pin at the following pin will act as supply to that nMOS transistor. Such that here when the two wires at this pin position are enabled by decoders with suitable input combination, the nMOS transistor gets supply from second decoder and input as Logic1 from first decoder. Since nMOS will be ON for Logic1, it is Switched ON and discharges the supply and gives output as Logic0.So in this way the outputs in ROM are programmed as 1‟s and 0‟s accordingly using two decoders and nMOS transistors.

1.2 Tools Used:

1.2.1 LT spice IV:

1.2.2 Microwind 2.6a:

MICROWIND is truly integrated EDA software encompassing IC designs from concept to completion, enabling chip designers to design beyond their imagination. MICROWIND integrates traditionally separated front-end and back-end chip design into an integrated flow, accelerating the design cycle and reduced design complexities. It tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing an innovative education initiative to help individuals to develop the skills needed for design positions in virtually every domain of IC industry.

1.2.3 180nm Spice Model:

The supporting spice model file used for implementing the circuit in 180nm technology. There are two different spice model files used for MICROWIND and LTspice.

2.Classification Of Various Logic styles:

In this paper, we shall use simple analytical models for MOS transistors. We use a sign convention according to which, voltage and current symbols associated with the pMOS transistor (such as VTp) have positive values. Then, the n channel formulae can be used for both transistors and we shall assign signs to quantities explicitly.

Figure 2.1: Drain Voltage Vs Current for CMOS Logic

It is assumed that the current increases linearly in the saturation region. All linear characteristics in saturation can be produced backwards towards negative drain voltages and will intersect the drain voltage axis at a single point at -VE. (This is, at best, an approximation). Because the conductance in saturation is now non zero, the onset of saturation has to be redefined, so that the current and its derivative are continuous at the boundary of linear and saturation regimes. While accurate modeling of the output conductance is essential for linear design, the simpler model assuming constant Id in saturation is often adequate for preliminary digital design. In any case, final designs will have to be validated with detailed simulations. Here simple model for MOS devices have been used to keep the algebra simple.

2.1 Static CMOS Logic Design:

made of n channel transistors. The networks are so designed that the pull up and pull down networks are never „on‟ simultaneously. This ensures that there is no static power consumption.

2.2 Dynamic logic:

. Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher toggle rate than static logic but the capacitative loads being toggled are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design. Dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic circuits. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed. The static/dynamic terminology used to refer to combinatorial circuits should not be confused with how the same adjectives are used to distinguish memory devices, e.g. static RAM from dynamic RAM as shown below.

Example 1: Static logic example

vdd

Vi V0

Gnd

Figure 2.2: static NOT gate

Static logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use. Also, the output is only valid for part of each clock cycle, so the device connected to it must sample it synchronously during the time that it is valid.

Example 2: Dynamic logic Example :

Figure 2.3: The dynamic 2-input Nand gate

2.3 Domino Logic:

By the late 1970s complementary metal oxide semiconductor (CMOS) started to become the process of choice for digital semiconductor designs. CMOS had originally been proposed by Frank Wanlass in 1963 as a low standby power technology, since CMOS logic gates dissipate almost no power when the inputs to the gate do not change. This follows as CMOS contains both PMOS field effect transistors (FETs), which can efficiently drive a high voltage, or logic one value, and NMOS transistors, which are good at driving a zero voltage. The presence of complementary transistors allows CMOS logic gates to be implemented so that the output voltage level is connected to the power or ground line, but not both. This ability to avoid contention ensures that if the inputs are not changing, then no power is dissipated. This was a major advantage of CMOS over the other manufacturing processes then available, which dissipated constant leakage or bias currents. In Figure 2.3 the schematic representation of a CMOS static NAND logic gate is shown.

The logic gate has two inputs A and B. A high logic value at inputs A and B turns on transistors MN1 and MN2, while turning off transistors MP1 and MP2. This causes the output Z to be low. When either input A or B is off, however, the path to the ground line is ruptured, with a path to the power supply (by convention called Vdd) being established. This causes Z to rise. While a NAND gate represents a simple function, it does show how contention between the power and ground supplies can be avoided in CMOS circuits. This lack of contention means that when the inputs to a CMOS circuit do not change, often called a standby or idle state, almost no power dissipation occurs, except for a small leakage current which flows through the transistors due to the imperfect manner in which a MOSFET acts as a switch (due to the relentless scaling in the physical dimensions of CMOS processes, driven by the cost advantages of having a smaller silicon area for digital functions, MOS transistors have become less perfect switches, leading to greater leakage current).

.

This conceptual resistor is actually implemented by a depletion mode NMOS transistor. The NMOS NAND gate output is at Vdd, or a logic one value, when either of the inputs, A or B, is low. When input A and input B are both high, the output is driven low. The current-driving ability of pull-down NMOS transistors must be much greater than that of the pull-up resistor. This ensures that the output can be driven to a low voltage at the cost of higher power dissipation. In addition to the standby power dissipation, NMOS circuits tend to be slower than equivalent CMOS circuits. This is due to the need for a weak pull-up resistor, which results in very slow low-to-high transitions.

Figure 2.4: An NMOS two-input NAND cell.

While these disadvantages may make NMOS appear to be unappealing, NMOS designs are more compact than CMOS circuits. Figure 2.6 uses only two transistors and a resistor,compared with the four transistors needed by a CMOS design. Since the pull-up resistor is implemented by another NMOS MOSFET, the NMOS design uses fewer transistors and a simpler process than the CMOS design. The need to move to CMOS therefore arose only when the integration level on integrated circuits (ICs) made the large standby power on the NMOS design unacceptable. For Intel this transition occurred in 1978, when the 8088/8086 family of microprocessors was introduced (the designs were almost identical to the 8088, having an 8-bit bus while the 8086 has a 16-bit bus).

2.4 FTL Design Methodology:

In this section some of the basic aspects of design methodologies are discussed, and guidelines are provided to the approach that might be pursued. The best results however can be obtained by mixing of various techniques. Since FTL gates are fully compatible with DCFL they are included in a DCFL standard library

Figure 2.4: (b) DFTL blocks

2.5 Evolution Of CD Logic:

2.5.1 FTL Operation:

FTL logic in CMOS technology was first introduced ii. Its basic operation is as follows: when CLK is high, the predischarge period begins and Out is pulled down to GND through M2. When CLK becomes low, M1 is on, M2 is off, and the gate enters the evaluation period. If inputs (IN) are logic “1,” Out enters the contention mode where M1 and transistors in the nMOS pull-down network (PDN) are conducting current simultaneously. If PDN is off, then the output quickly rises to logic “1.” In this case, FTL‟s critical path is always a single PMOS transistor.Despite its performance advantage, FTL suffers from reduced noise margin, excess direct path current, and nonzero nominal low output voltage, which are all caused by the contention between M1 and nMOS PDN during the evaluation period. Furthermore, cascading multiple FTL stages together to perform complicated logic evaluations is not practical. Consider a chain of inverters implemented in FTL cascaded together and driven by the same clock, as shown in Fig. 2.10 When CLK is low, M1 of every stage turns on, and the output of every stage begins to rise.

Figure 2.5: Simulated unwanted glitch at different logic depths in a chain of inverters implemented with FTL

2.5.2 CD Logic:

To mitigate the above-mentioned problems, CD logic is proposed with a schematic shown in Figure 2.11(a). Timing block (TB) creates an adjustable window period to reduce the static power dissipation. Logic Block (LB) helps to reduce the unwanted glitch and also makes cascading CD logic feasible. A buffer implemented in CD logic with schematics of TB and LB is shown.

2.5.3 CD Logic Operation:

The Predischarge Mode of CD Logic style depicts the corresponding CD logic timing diagram and flowchart in Figure 2.12 as shown below. For simplicity, we assume that IN come from dynamic domino logic gates. When CLK is high, CD logic predischarges both X and Y to GND. When CLK is low, CD logic enters the evaluation period and three scenarios can take place: namely, the contention, C–Q delay, and D–Q delay modes.The contention mode happens when CLK is low while IN remain at logic “1.” In this case, X is at a nonzero voltage level which causes Out to experience a temporary glitch. The duration of this glitch is determined by the local window width, which is determined by the delay between CLK and CLK_d. When CLK_d becomes high, and if X remains low, then Y rises to logic “1,” and turns off M1. Thus the contention period is over, and the temporary glitch at Out is eliminated.

C–Q delay mode takes places when IN make a transition from high to low before CLK becomes low. When CLK becomes low, X rises to logic “1” and Y

remains at logic “0” for the entire evaluation cycle. The delay is measured by the falling edge of both CLK and Out: hence the name C–Q delay. D–Q delay mode utilizes the pre-evaluated characteristic of CD logic to enable high-performance operations. In this mode, CLK falls from high to low before IN transit, hence X

initially rises to a nonzero voltage level. As soon as IN become logic “0,” while Y is still low, then X quickly rises to logic “1.” A race condition exists in this case between X and Y. If CLK_d rises much earlier than X and Y will go to logic “1,” turn off M1, and result in a false logic evaluation. If CLK_d rises slightly slower than X, then Y

will initially rise (thus slightly turns off M1) but eventually settle back to logic “0.”

The contention mode happens when CLK is low while IN remain at logic “1.” In this case, X is at a nonzero voltage level which causes Out to experience a temporary glitch. The duration of this glitch is determined by the local window width, which is determined by the delay between CLK and CLK_d. When CLK_d becomes high, and if X remains low, then Y rises to logic “1,” and turns off M1. Thus the contention period is over, and the temporary glitch at Out is eliminated.When CLK becomes low, X rises to logic “1” and Y remains at logic “0” for the entire evaluation

cycle. The delay is measured by the falling edge of both CLK and Out: hence the name C–Q delay.

In this mode, CLK falls from high to low before IN transit, hence X initially rises to a nonzero voltage level. As soon as IN become logic “0,” while Y is still low, then X quickly rises to logic “1.” A race condition exists in this case between X and Y. If CLK_d rises much earlier than X and Y will go to logic “1,” turn off M1, and result in a false logic evaluation. If CLK_d rises slightly slower than X, then Y will initially rise (thus slightly turns off M1) but eventually settle back to logic “0.” CD logic can

still perform the correct logic operation in this case, however, its performance is degraded because of M1‟s reduced current drivability. Therefore, it is important to maintain a sufficient window width under process-voltage– temperature (PVT) variations.

Figure 2.6: CD logic (a) block diagram and

Figure 2.7: CD logic (b) buffer

3.Implementation of ROM In CD Logic:

3.1 Stages of Designing ROM:

3.1.1 Decoder:

A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.In digital electronics, a decoder can take the form of a input, multiple-output logic circuit that converts coded inputs into coded multiple-outputs, where the input and output codes are different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding.

The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is called as "active low output". A slightly more complex decoder would be the n-to-2n type binary decoders. These type of decoders are combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n unique outputs. We say a

maximum of 2n outputs because in case the 'n' bit coded information has unused bit combinations, the decoder may have less than 2n outputs. We can have 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder. We can form a 3-to-8 decoder from two 2-to-4 decoders (with enable signals).

Similarly, we can also form a 4-to-16 decoder by combining two 3-to-8 decoders. In this type of circuit design, the enable inputs of both 3-to-8 decoders originate from a 4th input, which acts as a selector between the two 3-to-8 decoders. This allows the 4th input to enable either the top or bottom decoder, which produces outputs of D(0) through D(7) for the first decoder, and D(8) through D(15) for the second decoder.A decoder that contains enable inputs is also known as a decoder-demultiplexer. Thus, we have a 4-to-16 decoder produced by adding a 4th input shared among both decoders, producing 16 outputs.

3.1.2. 3*8 Decoder:

3*8 Decoder consists of three input pins and eight output pins. So eight possible combinations are there for inputs and for each possible combination single output that is one of the eight output pins will be enabled.

The truth table of the 3*8 decoder and the output logical equations are given below in Table 3.1.

Table 3.1: Truth table of 3*8 decoder

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

The eight outputs will have equations each and are given below. D0 = A‟B‟C‟

D1 = A‟B‟C D2 = A‟BC‟ D3 = A‟BC D4 = AB‟C D5 = AB‟C D6 = ABC‟ D7 = ABC

From the above equations it is evident that there will be three inverters that is NOT gates to invert each input and to multiply or AND the three input combination eight AND gates are required for eight input combinations.

Here in the first place three decoders are designed in three logic styles namely

 Static CMOS logic style

 Dynamic domino logic style

 CD(constant delay) logic style

 Static CMOS Decoder

First the schematics of NOT gate and AND gate are seen individually. The schematics of CMOS NOT gate is as follows.

Figure 3.1: schematic of NOT gate

The schematic of AND gate will be as follows.

So the CMOS decoder with three inverters and eight AND gates will be as follows

Figure 3.3 CMOS 3*8 Decoder

Dynamic domino decoder: The schematic of dynamic domino decoder consists of three NOT gates and eight AND gates. The schematic of dynamic domino NOT gate is as follows.

Figure 3.4: Dynamic domino NOT gate

The schematic of Dynamic domino AND gate is as follows.

So the Dynamic domino decoder with three inverters and eight AND gates will be as follows

 CD Decoder:

The schematic of dynamic domino decoder consists of three NOT gates and eight AND gates. The schematic of dynamic domino NOT gate is as follows.

Figure 3.6: CD logic style NOT gate

The schematic of Dynamic domino AND gate is as follows.

Figure 3.7: CD logic style 3 input AND gate

Figure 3.8: CD logic style 3*8 decoder

3.2 ROM (read only memory):

Read means output data-bits corresponding to the address bits set at the input. The bits are used by some processor or device or circuit for further operations. Data bits of different addresses store at ROM and all bits remain stored in the memory even after a power interruption or power switch OFF ROM is randomly accessed. An equal time interval is taken for a read of data-bits from each address. Address bits can be set randomly by an external circuit.ROM is a previously programmed „Decoder-diode(or transistor) links‟ array based logic device, programmed using appropriate masks at the manufacturing stage or by laboratory programming device ROM has an address decoder (n to 2n decoder) within it Each output line of decoder has 8 connections through a fusible diode. A diode n-end connects to a data bit output.

3.2.1 Block diagram of ROM:

………

……… .

. . . .

……….. .

Y0 Y1 Y8

Figure 3.9: Block diagram of ROM using two decoders.

This ROM is designed in three logic styles. The decoders are designed in three logic styles already. Using these decoders the ROM is implemented as shown in the block diagram. The designed decoders are saved and symbols of respective schematics are created in the LTspice tool. Using these symbols by calling them the ROM schematic is created in three logic styles that is in CMOS, Dynamic domino and Constant delay logic style.

The schematics of the ROMs designed in three logic styles are as follows.

Figure 3.10: Schematic of CMOS ROM

Decoder 1

Decoder 2

I

N

P

U

T

S

NMOS NMOS NMOS

NMOS NMOS

Schematic diagram of Dynamic domino ROM

Figure 3.11: Schematic of Dynamic domino ROM

Schematic diagram of CD ROM

Figure 3.12: Schematic of CD ROM

4 Simulation Results:

To justify that the constant delay logic style have reduced its input to output delay the delay in three logic styles CMOS, Dynamic domino and Constant delay styles have to be compared. The outputs of each logic styles are presented individually and then compared using a table.

4.1 CMOS Rom Outputs:

delay comparison is not possible. So the combinations where the output is Logic1 are shown and the delay is shown as follows.

Figure 4.1: CMOS ROM combination decoder-1(111) decoder-2(110)

The delay difference between input signal and output signal in the above figure is 393.23ps.Below is the output of the decoders‟ combination 1(100) decoder-2(100). In the below figure the input signal and the output signal are compared as discussed. Here at 0.9v the delay difference shown is 382.038ps.

Figure 4.2: CMOS ROM combination decoder-1(100) decoder-2(100)

4.2 Dynamic domino ROM outputs

Figure 4.3: Dynamic domino ROM combination decoder-1(111) decoder-2(111)

In the above output waveform the delay is measured between clock that is given to both decoders and the output of the ROM obtained according to the decoders combination.The special feature of dynamic domino logic style is that it works only when clock is high, that means the evaluation of output is seen only when the clock is “1”. As a result the delay is not seen between input and output. However large input may be output is generated only when clock is high. Hence delay is measured only between clock and the output which is shown below in all outputs.Below is the output of the decoders combination decoder-1(111) decoder-2(001). In the below figure the clock signal and the output signal are compared as discussed. Here at 0.9v the delay difference shown is 216.831ps.

Figure 4.4: Dynamic domino ROM combination decoder-1(111) decoder-2(001).

4.3 CD ROM outputs:

Figure 4.5: CD ROM combination decoder-1(110) decoder-2(110)

Below is the output of the decoders combination decoder-1(110) decoder-2(010). In the below figure the input signal and the output signal are compared as discussed.

Here at 0.9v the delay difference shown is 61.3825ps.

Figure 4.6: CD ROM combination decoder-1(110) decoder-2(010)

4.4 Analysis:

Table 4.1: Delay analysis in ROM

Static Dynamic CD

Delay(ps)

389.74

206.136

72.04

The above table shows the delay of ROM in three logic styles. Here the delay in all the combinations are normalized or averaged and are presented here. So now comparing here the delay of CMOS ROM 389.74ps is considered as 100% then the dynamic domino ROM‟s delay of 206.136ps will be 52.89% and CD ROM‟s delay of 72.04ps will be 18.48%. That means CD logic ROM is 48.2% faster than Dynamic domino ROM and 81.52% faster that static CMOS ROM.

5.Conclusion & Future Scope:

5.1 Conclusion:

A new high-performance logic style with CD characteristic and self-reset circuitry was proposed. The pre-evaluated feature of CD logic makes it particularly suitable in a circuit block where a unique critical path exists and performance is the primary concern. The output is evaluated only when the clock is low, this unique feature makes CD logic very special. Since it works only when the clock is low we can easily adjust the clock according to our need. All such properties of this logic style improves the performance of any circuit implemented in that style. But in some of the circuits the logic may not give better results and also in some circuits it consumes huge power and increase the number of transistors. Performance analysis of ROM reveals that CD logic is 81% and 48% faster than static and dynamic domino logic, respectively. This logic can be used and design circuits only in the fields where the power is not at all a concern and only speed is the main constraint and objective. In such areas the CD logic can be very helpful in achieving outputs in a quicker way. Also another trade off to be done is that lot more number of transistors are used in CD logic style than in CMOS and Dynamic domino. So when speed is the goal CD is preferable with other two constraints trading off.

5.2 Future Scope:

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