UM0488 User manual. STM3210E-EVAL evaluation board. Introduction. Features. Demonstration software. Order code

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UM0488

User manual

STM3210E-EVAL

evaluation board

Introduction

The STM32F103Z evaluation board STM3210E-EVAL is designed as a complete development platform for STMicroelectronic's ARM Cortex-M3 core-based STM32F103Z microcontroller with full speed USB2.0, CAN2.0A/B compliant interface, two I2S channels, two I2C channels, five USART channels with smartcard support, three SPI channels, two DAC channels, FSMC interface, SDIO, internal 64KB SRAM and 512KB Flash, JTAG and SWD debugging support.

The full range of hardware features on the board is intended to help you evaluate all peripherals (USB, motor control, CAN, MicroSD card, smartcard, USART, NOR Flash, NAND flash, SRAM) and develop your own applications. Extension headers make it possible to easily connect a daughter board or wrapping board for your specific application.

Features

■ Three 5 V power supply options: power jack, USB connector or daughter board

■ Boot from user Flash, system memory or SRAM

■ I2S Audio DAC, stereo audio jack

■ 128 Mbyte MicroSD card

■ Both A and B type smartcard support

■ 64 or 128 Mbit serial Flash, 512 Kx16 SRAM, 512 Mbit or 1 Gbit NAND Flash and 128 Mbit NOR Flash

■ I2C/SMBus compatible serial interface temperature sensor

■ Two RS232 channels with RTS/CTS handshake support on one channel

■ IrDA transceiver

■ USB2.0 full speed connection

■ CAN2.0A/B compliant connection

Figure 1. STM3210E-EVAL evaluation board

■ Inductor motor control connector

■ JTAG and trace debug support

■ 240x320 TFT color LCD

■ Joystick with 4-direction control and selector

■ Reset, wakeup, tamper and user buttons

■ 4 color LEDs

■ RTC with backup battery

Demonstration software

To use the STM3210E-EVAL evaluation board, you must have the demonstration software version 1.1 or later. If the version installed on your evaluation board is earlier than version 1.1, you must download the latest version from

www.st.com.

Order code

To order the STM32F103Z evaluation board, use the order code STM3210E-EVAL.

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Contents UM0488

1 Hardware layout and configuration . . . 4

1.1 Power supply . . . 6

1.2 Boot option . . . 7

1.3 Clock source . . . 7

1.4 Reset source . . . 7

1.5 Audio . . . 8

1.6 Serial Flash . . . 8

1.7 CAN . . . 8

1.8 RS232 connectors . . . 9

1.9 Motor control . . . 9

1.10 Smartcard . . . 10

1.11 MicroSD card . . . 11

1.12 Temperature sensor . . . 11

1.13 Analog input . . . 12

1.14 IrDA . . . 12

1.15 USB . . . 12

1.16 Development and debug support . . . 13

1.17 Display and input devices . . . 13

1.18 SRAM . . . 14

1.19 NAND Flash . . . 14

1.20 NOR Flash . . . 15

2 Connectors . . . 16

2.1 Motor control connector CN1 . . . 16

2.2 Analog input connectors CN2, CN3 and CN5 . . . 17

2.3 CAN D-type 9-pin male connector CN4 . . . 17

2.4 QST connector CN6 . . . 17

2.5 Trace debugging connector CN7 . . . 18

2.6 RS232 connector CN8 with RTS/CTS handshake support . . . 19

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UM0488 Contents

2.9 RS232 connector CN12 . . . 26

2.10 MicroSD connector CN13 . . . 26

2.11 USB type B connector CN14 . . . 27

2.12 Audio jack CN15 . . . 27

2.13 TFT LCD connector CN16 . . . 27

2.14 Power connector CN17 . . . 27

2.15 Smartcard connector CN18 . . . 28

3 Schematic diagrams . . . 29

Appendix A

STM3210E-EVAL IO assignment. . . 42

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Hardware layout and configuration UM0488

1 Hardware layout and configuration

The STM3210E-EVAL evaluation board is designed around the STM32F103Z

microcontroller in a 144-pin TQFP package. The hardware block diagram Figure 2 illustrates the connection between the STM32F103Z and peripherals (LCD, SPI Flash, USART, IrDA, USB, audio, CAN bus, smartcard, MicroSD card, NOR Flash, NAND Flash, SRAM, temperature sensor, audio DAC and motor control) and Figure 3 will help you locate these features on the actual evaluation board.

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UM0488 Hardware layout and configuration

Figure 3. STM3210E-EVAL evaluation board layout

CN10 Extension connector CN8 USART2 U1 STM32F103Z CN2,3,5 BNC U13 IrDA CN14 USB CN12 USART1 B1 RESET B2 WAKEUP CN18 Smartcard B3 Tamper U19 Joystick B4 User key CN1 Motor control CN4 CAN connector CN6 QST CN7 Trace CN9 JTAG U17 Color LCD CN15 Audio jack RV1 Potentiometer CN11 Extension connector CN13 MicroSD card CN17 5V power

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1.1 Power

supply

The STM3210E-EVAL evaluation board is designed to be powered by 5V DC power supply and to be protected by PolyZen U15 in the event of wrong power plug-in. It is possible to configure the evaluation board to use any of following three sources for the power supply:

● 5V DC power adapter connected to CN17, the power jack on the board (PSU on silk screen for power supply unit).

● 5V DC power with 500 mA limitation from CN14, the type-B USB connector (USB on silkscreen).

● 5V DC power from both CN10 and CN11, the extension connector for daughter board (DTB for daughter board on silkscreen).

The power supply is configured by setting the related jumpers JP13, JP12 and JP1 as described in Table 1.

Table 1. Power related jumpers

Jumper Description

JP13

JP13 is used to select one of the three possible power supply resources.

For power supply jack(CN17) to the STM3210E-EVAL only, JP13 is set as shown (default setting).

For power supply from the daughter board

connectors(CN10 and CN11) to STM3210E-EVAL only,

JP13 is set as shown.

For power supply from USB (CN14) to STM3210E-EVAL only, JP13 is set as shown.

For power supply from power supply jack(CN17) to both STM3210E-EVAL and daughter board connected on CN10 and CN11, JP13 is set as shown (daughter board must

not have its own power supply connected).

JP12 Enables consumption measurements of both VDD and VDDA.

Default setting: Fitted

JP1

V_bat is connected to 3.3V power when JP1 is set as shown (default setting).

V_bat is connected to battery when JP1 is set as shown.

PS U DT B USB PSU DT B US B PS U DT B USB PSU DT B US B 1 2 3 1 2 3

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1.2 Boot

option

The STM3210E-EVAL evaluation board can boot from:

● Embedded User Flash

● System memory with boot loader for ISP

● Embedded SRAM for debugging

The boot option is configured by setting the switches BOOT0 and BOOT1.

1.3 Clock

source

Two clock sources are available on STM3210E-EVAL evaluation board for STM32F103 and RTC.

● X2, 32KHz crystal for embedded RTC

● X1, 8MHz crystal with socket for STM32F103Z microcontroller, it can be removed from socket when internal RC clock is used.

1.4 Reset

source

The reset signal of STM3210E-EVAL evaluation board is low active and the reset sources include:

● Reset button B1

● Debugging Tools from JTAG connector CN7 and Trace connector CN9

● Daughter board from CN11

Table 2. Boot related switches

Switch Boot from Switch

configuration

BOOT0 BOOT1

STM3210E-EVAL boots from User Flash when BOOT0 is set as shown to the right. BOOT1 is not required in this configuration. (Default setting)

STM3210E-EVAL boot from Embedded SRAM when BOOT0 and BOOT1 are set as shown to the right.

STM3210E-EVAL boot from System Memory when BOOT0 and BOOT1 are set as shown to the right.

0 < > 1 Bo ot 0 0 < > 1 Boo t 0 Boo t 1 0 < > 1 Bo ot 0 B oot 1

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1.5 Audio

The STM3210E-EVAL evaluation board supports stereo audio play because it provides an audio DAC AK4343 connected to both I2S port and two channels of DAC of microcontroller STM32F103Z. Either external slave mode or PLL slave mode (reference clock BICK or LRCK) of audio DAC can be used by setting the jumper JP18.

The I2S_MCK is multiplexed with smartcard and motor control, and can be enabled by setting the jumper JP15. Refer to Section 1.9: Motor control for details. Audio DAC AK4343 is in power-down mode when PDN pin is pulled-down by PG11.

1.6 Serial

Flash

A 64 or 128 Mbit serial Flash connected to SPI1of STM32F103Z, serial Flash chip select is managed by IO pin PB2. The SPI1_MISO is multiplexed with motor control, it can be enabled by setting the jumper JP3. Refer to Section 1.9: Motor control for details.

1.7 CAN

STM3210E-EVAL evaluation board supports CAN2.0A/B compliant CAN bus

communication based on 3.3V CAN transceiver. The high-speed mode, standby mode and slope control mode are available and can be selected by setting JP8.

Table 3. Reset related jumper

JP19

Enables reset of the STM32F103Z embedded JTAG TAP controller each time a system reset occurs. JP19 connects the TRST signal from the JTAG connection with the system reset signal RESET#.

Default setting: not fitted

Table 4. Audio related jumpers

JP18

External slave mode (MCK from STM32F103Z) is selected when JP18 is set as shown (default setting).

PLL slave mode (reference clock BICK or LRCK) is selected when JP18 is set as shown.

1 2 3

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1.8 RS232

connectors

Two D-type 9-pin connectors CN12 (USART1) and CN8 (USART2) are available on the STM3210E-EVAL evaluation board. The USART1 connector is connected to RS232 transceiver U7 while the USART2 connector with RTS/CTS handshake signal support is connected to RS232 transceiver U5.

The USART2_CTS is multiplexed with motor control, it can be enabled by setting the jumper JP4. Refer to Section 1.9: Motor control for details.

1.9 Motor

control

The STM3210E-EVAL evaluation board supports three-phase brushless motor control via a 34-pin connector CN1, which provides all required control and feedback signals to and from the motor power driving board. Available signals on this connector include emergency stop, motor speed, three-phase motor current, bus voltage, heatsink temperature coming from the motor driving board and 6 channels of PWM control signals going to the motor driving circuit.

JP 20 allows to choose between two synchronization methods for power factor correction (PFC).

The I/O pins used on the motor control connector CN1 are multiplexed with some

peripherals on the board; either the motor control connector or multiplexed peripherals can be enabled by setting the jumpers JP3, JP4, JP11, JP15 and JP16 as described in Table 6.

Table 5. CAN related jumpers

JP8

CAN transceiver works in standby mode when JP8 is set as shown.

CAN transceiver works in high-speed mode when JP8 is set as shown (default setting).

CAN transceiver works in slope control mode when JP8 is open.

JP6 CAN terminal resistor is enabled when JP6 is fitted.

1 2 3

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1.10 Smartcard

STMicroelectronics smartcard interface chip ST8024 is used on STM3210E-EVAL board for asynchronous 3V and 5V smartcards. It performs all supply protection and control functions based on the connections with STM32F103Z listed in Table 7.

Table 6. Motor control related jumpers

Jumper Description Multiplexed

peripherals

JP20

JP20 allows to have a PFC synchronization signal redirected to the timer 3 input capture 1 pin, and additionally to the timer 3 external trigger input. JTAG debugging is disabled when JP20 is fitted.

JP2

JP2 should be kept on open when encoder signal is input from pin 31 of CN1 while it should be kept on close when analog signal is from pin 31 of CN1 for special motor.

JP4

MC_EnA is enabled when JP4 is set as shown to the right (default setting):

USART2_CTS is enabled when JP4 is set as show to the right:

USART2

JP3

MC_EmergencySTOP is enabled when JP3 is closed. The pin PA6 is used as SPI1_MISO when JP3 is open.

SPI1

JP11

MC_PFCpwm is enabled when JP11 is open. The pin PB5 will be used as interrupt input from temperature sensor when JP11 is closed.

Temperature sensor

JP15

MC_UH or I2S_MCK are enabled when JP15 is open. The pin PC6 is used as Smartcard_CMDVCC when JP15 is closed.

I2S and smartcard

JP16 MC_VH is enabled when JP16 is open. The pin PC7 is

used as Smartcard_OFF when JP16 is closed Smartcard

1 2 3

Table 7. Connection between ST8024 and STM32F103Z

Signals of ST8024 Description Connect to

STM32F10X

5V/3V Smartcard power supply selection pin PB0

I/OUC MCU data I/O line PB10

XTAL1 Crystal or external clock input PB12

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The Smartcard_CMDVCC and Smartcard_OFF are multiplexed with motor control. They can be enabled by setting the jumpers JP15 and JP16. Refer to Section 1.9: Motor control on page 9 for details.

1.11 MicroSD

card

The 128 Mbyte MicroSD card connected to SDIO of STM32F103Z is available on the board. MicroSD card detection is managed by standard IO port PF11.

The MicroSDcard_D3 is multiplexed with IrDA. It can be enabled by setting the jumper JP22, as explained in Section 1.14: IrDA on page 12.

The MicroSD card_D0 and MicroSD card CMD are multiplexed with the motor control connector. They can be enabled by setting the jumpers JP17 and JP20.

The jumper settings are described in Table 9.

1.12 Temperature

sensor

One I2C interface temperature sensor STLM75 (–55°C to +125°C) connected to I2C of STM32F103Z is available on the board.

RSTIN Card reset input from MCU PB11

CMDVCC Start activation sequence input (active low),

share same pin with I2S DAC and motor control PC6

Table 8. Smartcard related jumpers

JP15

The CMDVCC is connected to PC6 when JP15 is closed. It should be kept on open, or the SD card needs to be removed from the MicroSD card connector when PC6 is used by I2S or motor control connector. Default setting: not fitted

JP16

The OFF is connected to PC7 when JP16 is closed. It has to be kept on open when PC7 is used by the motor control connector.

Table 7. Connection between ST8024 and STM32F103Z (continued)

Signals of ST8024 Description Connect to

STM32F10X

Table 9. MicroSD card related jumpers

JP17

JP17 is used to enable MicroSD card data line D0. MicroSD card D0 is enabled when JP17 is fitted. The JP17 should be kept on open when motor control connector CN1 is used.

Default setting: fitted

JP20

JP20 is used by the motor control connector, refer to Table 6 for details. JP20 should be kept on open for MicroSD card operation. JTAG debugging is disabled when JP20 is fitted.

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1.13 Analog

input

Three BNC connectors CN2,CN3 and CN5 are connected to PC3, PC2 and PC1 of STM32F103Z as external analog input. The 50 ohm terminal resistor can be enabled by closing the solder bridge JP23, JP24 and JP25 for each BNC connector. A low pass filter can be implemented for each BNC connector CN5, CN3 and CN2 by replacing R5 and C22, R4 and C13, R3 and C9 with the right resistor and capacitor values, depending on the requirements of your application.

1.14 IrDA

IrDA communication is supported by the IrDA transceiver U13 connected to USART3 of STM32F103Z. The IrDA transceiver can be enabled or disabled by setting JP21.

1.15 USB

STM3210E-EVAL evaluation board support USB2.0 compliant full speed communication via a USB type B connector (CN14). The evaluation board can be powered by this USB connection at 5V DC with 500mA current limitation. USB disconnection simulation can be implemented by disconnecting 1.5K pull-up register from USB+ line. The USB disconnection simulation feature is enabled by setting JP14.

Table 10. IrDA related jumpers

JP21

JP21 is used to shutdown the IrDA transceiver.

IrDA is enabled when JP21 is fitted while IrDA is disabled when JP21 is not fitted.

Default setting: fitted

JP22

IrDA_RX is enabled when JP22 is closed. The IO pin PC11 is used as the data line 3 of the MicroSD card when JP22 is open.

Table 11. USB related jumpers

JP14

The USB 1.5K pull-up register is always connected to USB+ line when JP14 is set as shown.

The USB 1.5K pull-up register can be disconnected by software from USB+ line when JP14 is set as shown. In this case, the USB connect/disconnect feature is managed by standard IO port PB14 (default setting).

1 2 3

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1.16 Development and debug support

The two debug connectors available on STM3210E-EVAL evaluation board are:

● CN9, standard 20-pin JTAG interface connector that is compliant with ARM7 and ARM9 debug tools.

● CN7, SAMTEC 20-pin connector FTSH-110-01-L-DV for both SWD and Trace that is compliant with ARM CoreSight debug tools.

1.17 Display and input devices

The 240x320 TFT color LCD connected to bank3 of FSMC interface of STM32F103Z and four general purpose color LEDs (LD 1,2,3,4) are available as display devices. A 4-direction joystick with selection key, general purpose button (B4), wakeup button (B2) and tamper detection button (B3) are available as input devices. The jumper JP4 should be kept on open to enable the wakeup button B2 which shares the same IO with USART2 and motor control connector.

The STM3210E-EVAL evaluation board also supports a second optional 122x32 graphic LCD that can be mounted on the U18 connector. By default, the graphic LCD is not present.

Table 12. LCD modules

TFT LCD CN16 (default) Graphic LCD U18 (optional)

Pin on

CN16 Description Pin connection

Pin on

U18 Description Pin connection

1 CS CS of Bank3 of

FSMC 1 Vss GND

2 RS FSMC_A0 2 Vcc 3.3V

3 WR/SCL FSMC_NWE 3 VO

-4 RD FSMC_NOE 4 CLK PA5

5 RESET RESET# 5 SID PA7

6 PD1 FSMC_D0 6 CS PF10 7 PD2 FSMC_D1 7 A +5V 8 PD3 FSMC_D2 8 K GND 9 PD4 FSMC_D3 10 PD5 FSMC_D4 11 PD6 FSMC_D5 12 PD7 FSMC_D6 13 PD8 FSMC_D7 14 PD10 FSMC_D8 15 PD11 FSMC_D9 16 PD12 FSMC_D10 17 PD13 FSMC_D11

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1.18 SRAM

512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8 bit and 16 bit access are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM respectively.

1.19 NAND

Flash

The 512 Mbit x8 or 1 Gbit x8 NAND Flash is connected to bank0 of the FSMC interface. The ready/busy signal can be connected to either WAIT signal or FSMC_INT2 signal of

STM32F103Z depending on the setting of JP7.

18 PD14 FSMC_D12 19 PD15 FSMC_D13 20 PD16 FSMC_D14 21 PD17 FSMC_D15 22 BL_GND GND 23 BL_control 3.3V 24 VDD 3.3V 25 VCI 3.3V 26 GND GND 27 GND GND 28 BL_VDD 3.3V

29 SDO PA6 via JP26

30 SDI PA7 via JP27

Table 12. LCD modules (continued)

TFT LCD CN16 (default) Graphic LCD U18 (optional)

Pin on

CN16 Description Pin connection

Pin on

U18 Description Pin connection

Table 13. NAND Flash related jumpers

JP7

The ready/busy signal is connected to WAIT signal when JP7 is set as shown (default setting)

The ready/busy signal is connected to FSMC_INT2 signal when JP7 is set as shown.

1 2 3

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1.20 NOR

Flash

128 Mbit Nor Flash is connected to bank1 of the FSMC interface. The 16 bit operation mode is selected by a pull-up resistor connected to the BYTE pin of the NOR Flash. Write protection can be enabled or disabled depending on the setting of jumper JP5.

Three different NOR 128 Mbit references can be present on the evaluation board depending on component availability.

These three references are not identical in terms of ID code, speed, timing, block protection. The demonstration firmware and the software library delivered with the board support these three NOR Flash references. However, during the development of your application software, you must verify which NOR reference is implemented on your board (component referenced as U2 on silkscreen and schematic), and take its specificities into account.

Table 14. NOR Flash related jumpers

JP5

Write protection is enabled when JP5 is fitted while write protection is disabled when JP5 is not fitted.

Table 15. NOR Flash reference

Reference Manufacturer

M29W128GL70ZA6E NUMONYX

M29W128GH70ZA6E NUMONYX

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Connectors UM0488

2 Connectors

2.1 Motor control connector CN1

Figure 4. Motor control connector CN1 (top view)

Table 16. Motor control connector CN1

Description STM32F103Z pin CN1 pin # CN1 pin # STM32F103Z pin Description

EMERGENCY STOP PA6 1 2 GND

PWM-UH PC6 3 4 GND PWM-UL PA7 5 6 GND PWM-VH PC7 7 8 GND PWM-VL PB0 9 10 GND PWM-WH PC8 11 12 GND PWM-WL PB1 13 14 PC0 BUS VOLTAGE PHASE A CURRENT PC1 15 16 GND PHASE B CURRENT PC2 17 18 GND PHASE C CURRENT PC3 19 20 GND NTC BYPASS RELAY PB12 21 22 GND DISSIPATIVE BRAKE PWM PA3 through 0ohm resister un fitted 23 24 GND

+5V power +5V 25 26 PC5 Heatsink temperature

PFC SYNC PB4 and

PD2 27 28

3.3V power

PFC PWM PB5 29 30 GND

Encoder A PA0 31 32 GND

Encoder B PA1 33 34 PA2 Encoder Index

33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

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UM0488 Connectors

2.2 Analog input connectors CN2, CN3 and CN5

Figure 5. Analog input connector CN2, CN3 and CN5 bottom view

2.3 CAN D-type 9-pin male connector CN4

Figure 6. CAN D-type 9-pin male connector CN4 (front view)

2.4 QST connector CN6

The QST connector is designed to connect the STM3210E-EVAL to the QST evaluation board to demonstrate the QST function.

Figure 7. QST connector CN6 (front view)

Table 17. Analog input connector CN2, CN3 and CN5

Pin number Description Pin number Description

1 GND 4 GND

2 GND 5 Analog input PC3, PC2 and PC1

for CN2,CN3 and CN5 respectively

3 GND

1 2

4 3

5

Table 18. CAN D-type 9-pins male connector CN4

1,4,8,9 NC 7 CANH

2 CANL 3,5,6 GND

13 11 9 7 5 3 1

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2.5 Trace debugging connector CN7

Figure 8. Trace debugging connector CN7 (top view)

Table 19. QST connector CN6

1 +5V 2 +5V 3 PB6 4 PA5 5 PB7 6 PA7 7 PB1 8 PA6 9 PF11 10 PB5 11 PA8 12 -13 GND 14 GND

Table 20. Trace debugging connector CN7

1 3.3V power 2 TMS/PA13 3 GND 4 TCK/PA14 5 GND 6 TDO/PB3 7 KEY 8 TDI/PA15 9 GND 10 RESET# 11 GND 12 TraceCLK/PE2 13 GND 14 TraceD0/PE3 or SWO/PB3 15 GND 16 TraceD1/PE4 or nTRST/PB4 17 GND 18 TraceD2/PE5 19 GND 20 TraceD3/PE6 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1

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2.6 RS232 connector CN8 with RTS/CTS handshake support

Figure 9. RS232 connector CN8 with RTS/CTS handshake support (front view)

2.7 JTAG debugging connector CN9

Figure 10. JTAG debugging connector CN9 (top view)

Table 21. RS232 connector CN8 with RTS/CTS handshake support

1 NC 6 Connect to Pin 4

2 USART2_PA3 7 USART2_PA1

3 USART2_PA2 8 USART2_PA0

4 Connect to Pin 6 9 NC

5 GND

Table 22. JTAG debugging connector CN9

1 3.3V power 2 3.3V power 3 PB4 4 GND 5 PA15 6 GND 7 PA13 8 GND 9 PA14 10 GND 11 RTCK 12 GND 13 PB3 14 GND 15 RESET# 16 GND 17 DBGRQ 18 GND 19 DBGACK 20 GND 19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2

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2.8 Daughter board extension connectors CN10 and CN11

Two 70-pin male headers CN10 and CN11 can be used to connect a daughter board or standard wrapping board to the STM3210E-EVAL evaluation board. All total 112 GPI/Os are available on it. The space between these two connectors and the position of power, GND and RESET pins (marked in gray in Table 23 and Table 24) are defined as a standard which allows to develop common daughter boards for several evaluations boards. The standard width between CN10 pin1 and CN11 pin1 is 2700 mils (68.58 mm). This standard is implemented on the majority of evaluation boards.

Each pin on CN10 and CN11 can be used by a daughter board after disconnecting it from the corresponding function block on the STM3210E-EVAL evaluation board, as described in

Table 23 and Table 24.

Table 23. Daughter board extension connector CN10

Pin # Description Alternative function How to disconnect from function block on

STM3210E-EVAL board

1 GND -

-3 PC7 MC/Smartcard

Disconnect STM3210E-EVAL evaluation board from motor power drive board.

Keep JP16 on open.

5 PC9 MicroSD card Remove SD card from MicroSD card connector.

7 PA9 UASRT1_TX

-9 PA0 MC/Wakeup/USART2_CTS Keep JP4 on open.

11 - -

-13 PA12 USB_DP Remove R82.

15 PA14 Debug_TCK

-17 PC10 IrDA_TX/MicroSDcard_D2 Remove SD card from MicroSD card connector.

19 GND -

-21 PD0 FSMC_D2

-23 PE2 Trace_CLK/FSMC_A23

-25 PD2 MicroSDcard_CMD/MC

Remove SD card from MicroSD card connector.

27 PD4 FSMC_OEN -29 PD6 FSMC_WAITN -31 PD7 FSMC_EBAR0 Remove R22. 33 PG10 FSMC_EBAR2 Remove R15. 35 PG12 FSMC_EBAR3 Remove R77. 37 PG14 Joystick_Left Remove R102. 39 GND -

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-UM0488 Connectors

41 PB4 Debug_TRST/MC

Keep JP19 on open.

43 PB6 I2C_SCL/QST Disconnect STM3210E-EVAL evaluation board from QST board. 45 PB8 CAN_RX Remove R32. 47 PE0 FSMC_BLN0 -49 D5V - -51 PE4 Trace_D1/FSMC_A20 -53 PE6 Trace_D3/FSMC_A22

-55 PC14 OSC32_IN Remove R135, Keep JP9 (solder bridge) on close.

57 PF0 FSMC_A0 -59 GND - -61 PF2 FSMC_A2 -63 PF4 FSMC_A4 -65 PF6 LD2 Remove R96. 67 PF8 LD4 Remove R98. 69 +3V3 - -2 PC6 Smartcard/MC/I2S_MCK

Keep JP15 on open.

4 PC8 MicroSDcard_D0/MC

Remove SD card from MicroSD card connector. 6 PA8 MCO/LCD_backlight/QST Disconnect STM3210E-EVAL evaluation board from

QST board.

8 PA10 USART1_RX Remove R36.

10 GND -

-12 PA11 USB_DM Remove R81.

14 PA13 Debug TMS

-16 PA15 Debug TDI

-18 PC11 IrDA_RX/MicroSDcard_D2 Remove SD card from MicroSD card connector. Remove R89.

20 PC12 MciroSDcard_CLK Remove SD card from MciroSD card connector.

22 PD1 FSMC_D3

-24 PE1 FSMC_BLN1

-26 PD3 Joystick_Down Remove R100.

Table 23. Daughter board extension connector CN10 (continued)

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Connectors UM0488 28 PD5 FSMC_WEN -30 GND - -32 PG9 FSMC_EBAR1 Remove R21. 34 PG11 - -36 PG13 Joystick_Right Remove R103. 38 PG15 Joystick_Up Remove R104. 40 PB3 Debug_TDO -42 PB5 MC/QST/Temperature sensor

Disconnect STM3210E-EVAL evaluation board from motor power drive board and QST board.

Remove R46.

44 PB7 I2C_SDA/QST Disconnect STM3210E-EVAL evaluation board from QST board. 46 PB9 CAN_TX -48 3V3 - -50 GND - -52 PE3 Trace_D0/FSMC_A19 -54 PE5 Trace_D2/FSMC_A21

-56 PC13 Anti-tamper button Remove R111.

58 PC15 OSC32_OUT Remove R39, Keep JP10 (solder bridge) on close.

60 PF1 FSMC_A1 -62 PF3 FSMC_A3 -64 PF5 FSMC_A5 -66 PF7 LD3 Remove R97. 68 PF9 LD5 Remove R99. 70 GND -

-Table 23. Daughter board extension connector CN10 (continued)

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Table 24. Daughter board extension connector CN11

STM3210E-EVAL board 1 GND - -3 PG7 Joystick_Select Remove R101. 5 PG5 FSMC_A15 -7 PG3 FSMC_A13 -9 PC13 Button B3 - -11 RESET# - -13 PD12 FSMC_A17 -15 PD10 FSMC_D15 -17 PD8 FSMC_D13 -19 D5V - -21 PB13 I2S_CLK -23 PB11 Smartcard_Reset -25 PE15 FSMC_D12 -27 PE13 FSMC_D10 -29 PE11 FSMC_D8 -31 PD15 FSMC_D1 -33 PE9 FSMC_D6 -35 PE7 FSMC_D4 -37 PG1 FSMC_A11 -39 GND - -41 PF14 FSMC_A8 -43 PF12 FSMC_A6 -45 PB2 BOOT1/SPI_NSS

-47 PB1 MC/QST Disconnect STM3210E-EVAL evaluation board from motor power drive board and QST board.

49 - -

-51 PB0 Smartcard_3/5V/MC Disconnect STM3210E-EVAL evaluation board from motor power drive board.

53 PC4 Potentiometer Remove R126.

55 PA6 MC/SPI_MISO/QST

Disconnect STM3210E-EVAL evaluation board from motor power drive board and QST board.

Remove R37.

57 PA4 Audio_RIN Remove R67.

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-Connectors UM0488

61 PA1 MC/USART2_RTS Disconnect STM3210E-EVAL evaluation board from motor power drive board.

63 PC3 MC/BNC3

Disconnect analog signal from BNC3.

65 PC1 MC/BNC1

67 PF10 LCD_CS

-69 +3V3 -

-2 PG8 User button B4 Remove R106.

4 PG6 FSMC_INT2 Keep JP7 on open.

6 PG4 FSMC_A14 -8 PG2 FSMC_A12 -10 GND - -12 PD13 FSMC_A18 -14 PD11 FSMC_A16 -16 PD9 FSMC_A14 -18 PB15 I2S_DIN

-20 PB14 USB disconnect Connect pin1 of JP14 to pin2.

22 PB12 Smartcard_CK/MC/I2S_CMD Disconnect STM3210E-EVAL evaluation board from motor power drive board.

24 PB10 Smartcard_IO Remove R94. 26 PE14 FSMC_D11 -28 PE12 FSMC_D9 -30 GND - -32 PD14 FSMC_D0 -34 PE10 FSMC_D7 -36 PE8 FSMC_D5 -38 - - -40 PG0 FSMC_A10 -42 PF15 FSMC_A9 -44 PF13 FSMC_A7

-46 PF11 QST / MicroSD card detection Disconnect STM3210E-EVAL evaluation board from QST board. Remove SD card from card socket CN13.

48 - -

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50 GND -

-52 PC5 MC Disconnect STM3210E-EVAL evaluation board from

motor power drive board.

54 PA7 MC/SPI_MOSI/QST Disconnect STM3210E-EVAL evaluation board from motor power drive board and QST board.

56 PA5 SPI_CLK/DAC_LIN/QST

Disconnect STM3210E-EVAL evaluation board from QST board.

Remove R68.

58 PA3 MC/USART2_RX

Remove R29.

60 PA2 MC/USART2_TX Disconnect STM3210E-EVAL evaluation board from motor power drive board.

62

-64 PC2 MC/BNC2

66 PC0 MC

Remove C7 & R63.

68 - -

-70 GND -

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2.9 RS232 connector CN12

Figure 11. RS232 connector CN12 (front view)

2.10 MicroSD connector CN13

Figure 12. MicroSD connector CN13 (front view)

Table 25. RS232 connector CN12

1 NC 6 Connect to Pin 4

2 USART1_PA10 7 Connect to Pin 8

3 USART1_PA9 8 Connect to Pin 7

4 Connect to Pin 6 9 NC

5 GND

Table 26. MicroSD connector CN13

1 MicroSDcard_D2 (PC10) 5 MicroSDcard_CLK (PC12)

2 MicroSDcard_D3 (PC11) 6 Vss/GND

3 MicroSDcard_CMD (PD2) 7 MicroSDcard_D0 (PC8)

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2.11 USB type B connector CN14

Figure 13. USB type B connector CN14 (top view)

2.12 Audio jack CN15

A 3.5 mm stereo audio jack CN15 connected to the audio DAC is available on the STM3210E-EVAL board.

2.13 TFT LCD connector CN16

One 30-pin male header is available on the board to connect the LCD module board MB694 to the FSMC interface of the STM32F103Z. Refer to Section 1.17: Display and input devices on page 13 for details.

2.14 Power connector CN17

Your STM3210E-EVAL evaluation board can be powered from a DC 5V power supply via the external power supply jack (CN17) shown in Figure 14. The central pin of CN17 must be positive.

Figure 14. Power supply connector CN17 (front view)

Table 27. USB type B connector CN14

1 VBUS(power) 4 GND

2 PA11 5,6 Shield

3 PA12

DC +5V

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2.15 Smartcard connector CN18

Figure 15. Smartcard connector CN18 (front view)

Table 28. Smartcard connector CN18

1 VCC 5 GND

2 RST 6 NC

3 CLK 7 I/O

4 NC 8 NC

17 Detection pin of card presence 18 Detection pin of card presence 17 18

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UM0488 Schematic diagrams

3 Schematic

diagrams

This section provides the design schematics for the STM3210E-EVAL board key features, to help you implement these features in your applications. Schematics are provided for:

● Microcontroller connections, see Figure 16

● MCU, see Figure 17

● Peripherals, see Figure 18

● RS232 and IrDA connectors, see Figure 19

● Audio, see Figure 20

● LCD and joystick connections, see Figure 21

● SD card and smartcard, see Figure 22

● Motor control, see Figure 23

● JTAG and trace connectors, see Figure 24

● Power supply, see Figure 25

● SRAM and Flash, see Figure 26

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Schematic diagrams UM0488

Figure 16. Microcontroller connections

S T M icr oe le c tr o ni c s Ti tl e: N u m b er : R ev : S h eet o f D .2 (PC B. S CH ) Da te : 200 8 -05-21 M B 67 2 1 11 S TM 3 21 0E -E VA L I2 S _ C M D I2 S _ D IN I2 S _ C K MCO A u di o_ S C K Au di o_ S D A Au di o_ L IN A u di o_ R IN I2 S _ M C K Au di o_ P D N U_ A u di o Au di o. S ch D o c A [0 ..2 3] D [0 ..1 5] FSMC_ N E 3 FSM C _N C E 2 FSMC_ N E 2 FSM C _N W E FSMC_ N O E FS M C _N B L 0 FS M C _N B L 1 FSMC_ N W A IT FSMC_ IN T 2 U_ S R A M & F la sh SR A M &Fl as h. S ch D o c US A R T 2_ R X US A R T 2_ T X U S A R T2 _ R TS U S A R T2 _ C TS US A R T 1_ T X US A R T 1_ R X Ir D A _ R X Ir D A _ T X U_ R S 23 2& Ir D A RS 23 2 & Ir D A .S ch D oc Fl as h_ C S Fl as h_ SC K Fl as h_ M ISO Fl as h_ M O SI LE D 4 LE D 3 LE D 1 LE D 2 US B _ DM US B _ DP US B _ Di sc on ne ct T em per at u re Sen so r_ IN T T em per at u re Sen so r_ S C L T em per at u re Sen so r_ S D A BN C1 CA N _T X CA N _R X Po te nt io m et er BN C2 BN C3 U_ P er ip he ra ls P er ip her al s. S ch D oc MC _E m er g en cy S T O P M C _C u rr ent A M C _C u rr ent B M C _C u rr ent C M C _PFC sy nc 1 M C _PFC sy nc 2 MC _W L MC _V H MC _V L MC _U H MC _U L MC _W H MC _N T C M C _D is si pa ti ve B ra k e M C _PFC p w m M C _E nA M C _E nB M C _H ea ts in kT em pe ra tu re MC _B u sV ol ta ge M C _E nI nd ex BN C1 BN C2 BN C3 U_ M ot or C tr l Mo to rCt rl .S ch D oc U_ P ow er Po w er .Sc hD oc TD I RE S E T # TR A C E _D 3 TR A C E _D 2 TR A C E _D 1 TR A C E _D 0 TR A C E _C K TR S T T M S/ SW D IO TC K /S W C L K TD O /S W O U_ JT AG & S W D JT A G & S W D .S ch D oc TD I TR A C E _C K TM S /S W D IO TC K /S W C L K TD O /S W O US A R T 2_ R X US A R T 2_ T X U S A R T2 _ R TS U S A R T2 _ C TS US A R T 1_ T X US A R T 1_ R X Ir D A _ R X Ir D A _ T X MC_ E m erg en cy S T O P MC _C u rre nt A MC _C u rre nt B MC _C u rre nt C MC _P F C sy nc 1 MC _P F C sy nc 2 MC_ W L MC _V H MC _V L MC _U H MC _U L MC _W H MC _N T C MC_ D is si pa ti ve Br ak e MC _P F C p w m M C _E nA MC_ E nB M C _H ea ts in kT em pe ra tu re MC _B u sV ol ta ge M C _E nI nd ex JO Y _ S E L JO Y _ D O W N JO Y _ LEF T JO Y _ R IG H T JO Y_ UP LC D _ C S LC D _ ba ck li g ht An ti _T am pe r WA K E U P Us er _B u tt on S P I1_C S S P I1_S C K S P I1_M IS O S P I1_M O S I LE D 4 LE D 3 LE D 1 LE D 2 US B _ DM US B _ D P US B _ Di sc on ne ct T em per at u re Sen so r_ IN T CA N _T X CA N _R X Po te nt io m et er FSMC_ N E 3 A[ 0 ..2 3] D[ 0 ..1 5] FSM C _N E 4 FSMC_ N C E 2 FSMC_ N E 2 FSMC_ N W E FSMC_ N O E FSMC_ N B L 0 FSMC_ N B L 1 FSMC_ N W A IT FSMC_ IN T 2 Mi cr o S D C ar d_ CL K Mi cr o S D C ar d_ CMD S m ar tC ar d_ 3/ 5V Sm ar tC ar d_ IO Sm ar tC ar d_ R S T Sm ar tC ar d_ C L K Sm ar tC ar d_ O F F Sm ar tC ar d_ C M D V C C Mi cr o S D C ar d_ D 0 I2 S _ C M D I2 S _ D IN I2 S _ C K MCO I2 C _S C K I2 C _S D A Mi cr o S D C ar d_ D 1 Mi cr o S D C ar d_ D 2 Mi cr o S D C ar d_ D 3 RE S E T # TR A C E _D 3 TR A C E _D 2 TR A C E _D 1 TR A C E _D 0 TR S T Au di o_ L IN Au di o_ R IN M ic ro S D C ar d_ D et ect I2 S _ M C K Au di o_ P D N U_ M C U M C U .S chD oc Mi cr o S D C ar d_ CL K M icr o S D C ar d_ C M D S m ar tC ar d_ 3/ 5V Sma rt C ar d_ IO Sma rt C ar d_ R S T Sma rt C ar d_ C L K Sma rt C ar d_ O F F Sma rt C ar d_ C M D V C C Mi cr o S D C ar d_ D 0 Mi cr o S D C ar d_ D 1 Mi cr o S D C ar d_ D 2 Mi cr o S D C ar d_ D 3 M icr o S D C ar d_ D et ec t U _ SD &Sma rt C ar d SD & Smart C ard .S ch D oc JO Y _ S E L JO Y _ D O W N JO Y _ LEF T JO Y _ R IG H T JO Y _ U P LC D _ C S LC D _ C L K LC D _ D I RE S E T # LC D _ ba ck li g ht A n ti _T am pe r WA KE U P Us er _B u tt on FSM C _N E 4 D[ 0 ..1 5] A[ 0 ..2 3] FSM C _N W E FSM C _N O E LC D _ D O U_ L C D & Jo ys ti ck LC D & Jo ys ti ck .S ch D oc

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UM0488 Schematic diagrams Figure 17. MCU S TMic ro e le c tr o n ic s Ti tl e: N u m b er : R ev : S h eet o f D. 2 (P C B . S CH ) Da te : 200 8 -05-21 M B 67 2 2 11 S TM 3 21 0E -E VA L M C U

MC

U

D5 V D5 V PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PA 6 PA 7 PA 8 PA 9 P A 1 0 PA 1 1 PA 1 2 PA 1 3 PA 1 4 PA 1 5 PB 0 PB 1 PB 2 PB 3 PB 4 P B 5 PB 6 P B 7 PB 8 P B 9 PB 10 PB 11 PB 12 PB 13 PB 14 PB 15 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 P C 8 PC 9 PC 10 PC 11 PC 12 PC 13 PC 14 PC 15 PD 0 P D 1 PD 2 P D 3 PD 4 P D 5 PD 6 PD 7 PD 8 PD 9 PD 1 0 PD 1 1 PD 1 2 PD 1 3 PD 1 4 PD 1 5 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF1 0 PF1 1 PF1 2 PF1 3 PF1 4 PF1 5 PE 3 PE 4 PE 5 PE 6 PE 7 P E 8 PE 9 P E 1 0 PE 1 1 PE 1 2 PE 1 3 PE 1 4 PE 1 5 PE 0 PE 1 PE 2 PG 0 PG 1 PG 2 PG 3 PG 4 PG 5 PG 6 PG 7 PG 8 PG 9 PG 1 0 PG 1 1 PG 1 2 PG 1 3 PG 1 4 PG 1 5 RE S E T # R1 4 82 0 R1 1 82 0 PC 13 12 34 56 78 91 0 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 CN 1 1 H ead er 3 5 X 2 12 34 56 78 91 0 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 CN 1 0 H ead er 3 5 X 2 +3 V 3 +3 V 3

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TD I T M S/ SW D IO TC K /S W C L K US A R T 2_ R X US A R T 2_ T X U S A R T2 _ R TS U S A R T2 _ C TS US A R T 1_ T X US A R T 1_ R X MC _E m erg en cy S T O P MC_ U L M C _D is si pa ti ve B ra k e M C _E nA M C _E nB M C _E nI nd ex LC D _ ba ck li g ht WA KE U P SPI 1 _ S C K SPI 1 _ M IS O SPI 1 _ M O S I US B _ D M US B _ D P I2 S _ C M D I2 S _ D IN I2 S _ C K MCO PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PA 6 PA 7 PA 8 PA 9 PA 1 0 PA 1 1 PA 1 2 PA 1 3 PA 1 4 PA 1 5 3 2 1 JP 4 Au di o_ R IN A u di o_ L IN JP 3 TR S T TD O /S W O MC_ P F Cs yn c1 MC_ W L MC_ V L MC_ N T C MC_ P F Cp w m SPI 1 _ C S T em pe rat u reS en so r_ IN T CA N _T X CA N _RX S m ar tC ar d_ 3/ 5V Sma rt C ar d_ IO Sma rt C ar d_ R S T Sm ar tC ar d_ C L K I2 C _S C K I2 C _S D A PB 0 PB 1 PB 2 PB 3 PB 4 PB 5 PB 6 PB 7 PB 8 PB 9 PB 10 PB 11 PB 12 PB 13 PB 14 PB 15 R4 3 10 K +3 V 3 2 3 1 BO O T 1 Ir D A _ R X Ir D A _ T X M C _C u rr ent A M C _C u rr ent B M C _C u rr ent C MC _V H MC _U H MC _W H Mi cr o S D C ar d_ CL K Sma rt C ar d_ O F F Sma rt C ar d_ C M D V C C Mi cr o S D C ar d_ D 0 Mi cr o S D C ar d_ D 1 Mi cr o S D C ar d_ D 2 Mi cr o S D C ar d_ D 3 JP 1 6 JP 2 2 MC _B u sV ol ta ge M C _H ea ts inkT em pe ra tu re P ot ent io m ete r A n ti _T am pe r 4 1 3 2 X2 M C 30 6-G -06 Q -32 .7 68 ( m an uf ac tu re r JF V N Y ) C4 4 10 pF C4 3 10 pF R3 9 0 1 4 3 2 B1 RE S E T R1 1 9 10 K +3 V 3 C9 4 10 0n F C4 8 20 pF C4 7 20 pF X1 8M Hz ( w it h so ck et ) R4 0 39 0 R4 5 10 K +3 V 3 2 3 1 BO O T 0 RE S E T # RE S E T # M C _PFC sy nc 2 FSMC_ N C E 2 FSMC_ N W E FSMC_ N O E FSMC_ N W A IT Mi cr o S D C ar d_ CM D FSMC_ N B L 0 TR A C E _C K TR A C E _D 3 TR A C E _D 2 TR A C E _D 1 TR A C E _D 0 Us er _B u tt on LE D 3 LE D 1 LE D 2 US B _ Di sc on ne ct JO Y _ S E L JO Y _ D O W N JO Y _ LEF T JO Y _ R IG H T JO Y _ U P FSMC_ N E 2 FSMC_ IN T 2 JP 1 1 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PC 8 PC 9 PC 10 PC 11 PC 12 PC 13 PC 14 PC 15 PD 0 PD 1 PD 2 PD 3 PD 4 PD 5 PD 6 PD 7 PD 8 PD 9 PD 1 0 PD 1 1 PD 1 2 PD 1 3 PD 1 4 PD 1 5 D2 D3 A1 6 D1 3 D1 4 D1 5 A1 7 A1 8 D0 D1 A1 9 A2 0 A2 1 A2 2 A2 3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 D1 2 A0 A1 A2 A3 A4 A5 LE D 4 LC D _ C S A6 A7 A8 A9 A1 0 A1 1 A1 2 A1 3 A1 4 A1 5 D[ 0 ..1 5] A[ 0 ..2 3] A [0 ..2 3] D [0 ..1 5] PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF1 0 PF1 1 PF1 2 PF1 3 PF1 4 PF1 5 PE 2 PE 3 PE 4 PE 5 PE 6 PE 7 PE 8 PE 9 PE 1 0 PE 1 1 PE 1 2 PE 1 3 PE 1 4 PE 1 5 PE 0 PE 1 PG 0 PG 1 PG 2 PG 3 PG 4 PG 5 PG 6 PG 7 PG 8 PG 9 PG 1 0 PG 1 1 PG 1 2 PG 1 3 PG 1 4 PG 1 5 Q S T conn ec tor PA 5 +5 V PA 6 PA 7 PB 1 PF1 1 P B 5 PB 6 PB 7 IC 14 9-14 4-04 5-B 5 R3 1 0 R2 do no t fi t PE 2 1 PF2 12 OS C _ IN 23 PA 0 -W K U P 34 PC 5 45 PG 0 56 PE 1 0 63 PE 1 1 64 PE 3 2 PE 4 3 PE 5 4 PE 6 5 PC 13 -A N T I_ T A M P 7 PC 14 -O SC 3 2_ IN 8 PC 15 -O SC 3 2_ O U T 9 PF0 10 PF1 11 PF3 13 PF4 14 PF5 15 PF6 18 PF7 19 PF8 20 PF9 21 PF1 0 22 OS C _ OU T 24 NR S T 25 PC 0 26 PC 1 27 PC 2 28 PC 3 29 PA 1 35 PA 2 36 PA 3 37 PA 4 40 PA 5 41 PA 6 42 PA 7 43 PC 4 44 PB 0 46 PB 1 47 PB 2 48 PF1 1 49 PF1 2 50 PF1 3 53 PF1 4 54 PF1 5 55 PG 1 57 PE 7 58 PE 8 59 PE 9 60 PE 1 2 65 PB 15 76 PG 2 87 PC 8 98 PA 1 4 10 9 PG 1 1 12 6 PG 1 2 12 7 PG 1 3 12 8 PE 1 3 66 PE 1 4 67 PE 1 5 68 PB 10 69 PB 11 70 PB 12 73 PB 13 74 PB 14 75 PD 8 77 PD 9 78 PD 1 0 79 PD 1 1 80 PD 1 2 81 PD 1 3 82 PD 1 4 85 PD 1 5 86 PG 3 88 PG 4 89 PG 5 90 PG 6 91 PG 7 92 PG 8 93 PC 6 96 PC 7 97 PC 9 99 PA 8 10 0 PA 9 10 1 PA 1 0 10 2 PA 1 1 10 3 PA 1 2 10 4 PA 1 3 10 5 NC 10 6 PA 1 5 11 0 PC 10 11 1 PC 11 11 2 PC 12 11 3 PD 0 11 4 PD 1 11 5 PD 2 11 6 PD 3 11 7 PD 4 11 8 PD 5 11 9 PD 6 12 2 PD 7 12 3 PG 9 12 4 PG 1 0 12 5 PG 1 4 12 9 PB 7 13 7 BO O T 0 13 8 PB 8 13 9 PB 9 14 0 PE 0 14 1 PE 1 14 2 PG 1 5 13 2 PB 3 13 3 PB 4 13 4 PB 5 13 5 PB 6 13 6 U8 A S T M 3 2F 10 3Z E T 6 PA 8 12 34 56 78 91 0 11 12 13 14 CN 6 H ead er 7 X 2 +5 V M ic ro S DC ar d_ De te ct TP 1 1 MCO I2 S _ M C K JP 1 5 D ef aul t s et ti n g: 2< -> 3 D ef au lt s ett in g: O pe n D ef au lt s ett in g: cl os e D ef aul t s ett in g: cl os e D ef au lt s ett in g: cl os e D ef au lt s ett in g: O pe n TP 1 Gr ou nd TP 2 Gr ou nd JP 9 JP 1 0 FSMC_ N E 3 FSMC_ N E 4 FSMC_ N B L 1 A u di o_ P D N (R ig ht ) (L ef t) +3 V 3 JP 1 7 D ef au lt s ett in g: cl os e R1 3 5 0

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Schematic diagrams UM0488 Figure 18. Peripherals

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Tit le : N u m b er : R ev : S heet o f D .2 (PC B. S CH ) Da te : 200 8 -05-2 1 +3 V 3 +3 V 3 C1 4 10 0nF HO LD 7 VC C 8 S 1 Q 2 W 3 VS S 4 D 5 C 6 U6 M25P 64 -V M E 6G SD A 1 SCL 2 OS /I N T 3 GN D 4 A2 5 A1 6 A0 7 VD D 8 U9 ST L M 75 M 2 E +3 V 3 +3 V 3 C4 9 10 0n F U5 V C7 4 10 0nF VC C 1 D-2 D+ 3 GN D 4 SH E L L 0 SH E L L 0 yp eB co n nect or R6 9 1. 5 K R7 0 10 K U5 V R6 5 36 K 2 31 T2 9013 +3 V 3 I/ O 1 1 GN D 2 I/ O 2 3 I/ O 2 4 Vbu s 5 I/ O 1 6 U1 1 U S BL C6 -2 P6 U5 V R9 5 1M C7 8 4. 7 nF 2 31 T1 9013 R6 6 47 K +3 V 3 3 2 1 JP 1 4 D 1 GN D 2 VC C 3 R 4 Vr ef 5 CA N L 6 CA N H 7 RS 8 U4 SN 65 HVD 23 0 1 6 2 7 3 8 4 9 5 CN 4 DB 9-m ale C A N co nne ct o r +3 V 3 +3 V 3 R2 8 12 0 JP 6 3 2 1 JP 8 R2 6 10 K +3 V 3 C2 7 10 0nF 12 LD 3 Red 12 LD 2 Or an g e ₁₂ LD 4 Bl ue 12 LD 1 G reen 1 2 3 4 5 CN 3 VB 33 4 MB 5 2 5 3 11 S TM 3 2 1 0 E -EVAL P e ri p h e r a l s R2 7 0 R3 50 R3 7 0 1 3 2 RV 1 10 K R 126 0 +3 V 3 R4 6 0 R4 4 0 R3 8 0 R9 6 60 0 R9 7 60 0 R9 8 60 0 R9 9 60 0 R3 2 0 Fl as h _CS Fl as h _SCK Fl as h _MI SO Fl as h _MO SI LE D4 LE D3 LE D1 LE D2 US B _D M US B _D P US B _D isc on ne ct emp era tu reSe n so r_ IN T emp era tu reSe n so r_ SC L emp era tu reSe n so r_ SD A BN C1 AN_ TX AN_ R X P ote n tio m ete r S PI F l as h B N C c onnect o r Pot e n tio m e te r T e m per a t u re s en s or CA N U S B 1 2 3 4 5 CN 5 VB 33 4 BN C2 1 2 3 4 5 CN 2 VB 33 4 BN C3 R9 0 R1 0 do not f it LE D R8 2 0 R8 1 0 D ef ault se tt ing : 1 <-> 2 D efau lt s et ti ng : O pen R5 1 4K 7 PA 12 PA 11 PB1 4 PB8 PB9 PB7 PB6 PB5 PF 7 PF 6 PF 9 PF 8 PC2 PC1 PC3 PC4 PB2 PA 6 PA 5 PA 7 JP 2 5 R 136 50 R 137 50 R 138 50 JP 2 4 JP 2 3 JP 2 3-25 De fa u lt se tti ng: ope n C 100 10 nF

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Figure 19. RS232 and IrDA connectors

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Tit le : N u m b er : R ev : S he et o f D .2 (PC B. S CH ) Da te : 200 8 -05-2 1 SD 5 TxD 3 GN D 8 A no de (V CC2 ) 1 Cat ho de 2 Rx D 4 VC C 1 6 Vlo gic 7 U1 3 TF DU 430 0 R9 2 5 R8 5 47 C6 8 0. 1 uF C7 2 0. 1 uF +3 V 3 C7 7 4. 7 uF C7 1 4. 7 uF R8 8 10 K +3 V 3 JP 2 1 R 2ou t 9 R2 in 8 T1i n 11 R 1ou t 12 T1o ut 14 R1 in 13 T2i n 10 T2o ut 7 C1 + 1 C1 -3 C2 + 4 C2 -5 V+ 2 V-6 VC C 16 GN D 15 U5 ST32 32E C T R C3 7 10 0nF C2 9 10 0nF C3 0 10 0nF C2 8 10 0nF C3 1 10 0nF +3 V 3 1 6 2 7 3 8 4 9 5 CN 8 DB 9-m ale US AR T2 R3 3 do not f it R 2ou t 9 R2 in 8 T1i n 11 R 1ou t 12 T1o ut 14 R1 in 13 T2i n 10 T2o ut 7 C1 + 1 C1 -3 C2 + 4 C2 -5 V+ 2 V-6 VC C 16 GN D 15 U7 ST32 32E C T R C5 2 10 0nF C4 1 10 0nF C4 0 10 0nF C3 9 10 0nF C4 2 10 0nF +3 V 3 1 6 2 7 3 8 4 9 5 CN 12 DB 9-m ale US AR T1 R6 2 do not f it R S 232 _TX2 R S 232 _R X2 R S 232 _C TS 2 R S 232 _R TS 2 R S 232 _R X1 R S 232 _TX1 MB 6 7 2 4 1 1 S TM 3 2 1 0 E -EVAL R S 2 3 2& Ir D A R3 6 0 R8 9 0 R2 9 0 R3 0 0 US AR T2 _R X US AR T2 _TX US AR T2 _R TS US AR T2 _C TS US AR T1 _TX US AR T1 _R X IrD A _R X IrD A _T X c o n n e c to r f o r U S ART2 c o n n e c to r f o r U S ART1 Ir D A R3 4 10 K De fa ult se tt ing : c lo se PA 0 PA 1 PA 2 PA 3 PA 9 PA 10 PC1 0 PC1 1

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Schematic diagrams UM0488 Figure 20. Audio

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Tit le : N u m b er : R ev : S h e et o f D .2 (PC B. S CH ) Da te : 200 8 -05-2 1 MB 6 7 2 5 1 1 S TM 3 2 1 0 E -EVAL A u di o I2 S_ CM D I2 S_ D IN I2 S_ CK 3 2 1 JP 1 8 O Ju m p er t o s e lect PL L s lav e c lo c k mo d e : 1 . 1 < -> 2 refe ren ce cl o c k MC K I 2 . 2 < -> 3 ref eren ce cl o ck BI C K o r L R CK TP 7 MC K O +3 V 3 R7 2 10 K C5 9 1u F Aud io_ S C K Aud io_ S D A I2 C co n tro l in te rface se le ct e d (s h a re w it h te m p e ra tur e s en sor ) b y co nn e c ti ng p in "I 2C " to h igh, the s la v e a ddr e ss is se t t o " 0 010 011 " by p u ll up pin " C AD0" . C6 5 10 uF C5 4 10 0nF C5 3 2. 2 u F C3 4 10 0nF +3 V 3 C7 3 10 uF C6 6 10 0nF C7 9 10 uF C1 6 10 0nF +3 V 3 +3 V 3 R8 3 10 C6 7 0. 2 2uF R7 3 10 C7 6 0 .2 2uF R8 6 10 R8 7 6. 8 R8 4 6. 8 C8 0 47 uF C7 0 47 uF 1 2 3 CN 1 5 S T -225 -0 2 1 2 U1 4 KS S -150 8 CC L K /S CL 9 CD T I/ S D A 10 SD T I 11 TES T2 12 LR C K 13 BI C K 14 DV D D 15 DV S S 16 M U TET 25 R OUT /R C N 26 LO UT/R C P 27 M IN/ L IN3 28 RIN 2 /I N 2 -29 LI N2 /I N2 + 30 LI N1 /I N1 -31 RIN 1 /I N 1 + 32 TES T1 1 VC O M 2 AV S S 3 AVD D 4 VC OC /R IN 3 5 I2 C 6 PD N 7 CS N /CA D 0 8 MC K I 17 MC K O 18 SP N 19 SP P 20 HV D D 21 HV S S 22 HP R 23 HP L 24 U1 0 AK4 3 4 3 Aud io_ R IN Aud io_ LI N C5 6 1u F C5 7 1u F C5 8 do not f it C5 5 d o not f it R6 7 0 R6 8 0 TP 9 RIN TP 6 LI N TP 10 HP L TP 8 HP R TP 1 2 SPP TP 13 SPN S_ MCK R5 6 0 R5 7 do not f it De fa ult se tt in g : 1 < -> 2 PC 6 PA 8 PB1 2 PB1 3 PB1 5 PB7 PB6 PA 5 PA 4 R1 2 8 0 Aud io_ P D N PG 1 1

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Figure 21. LCD and joystick connections

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Tit le : N u m b er : R ev : S heet o f D .2 (PC B. S CH ) Da te : 200 8 -05-2 1 R11 2 10K R11 4 10K R11 5 10K R11 6 10K R11 3 10K +3 V 3 C99 100 nF C98 100 nF C97 100 nF C95 100 nF C96 100 nF R 125 10 0 CO MM O N 5 Sel ect io n 2 DW ON 3 LE FT 1 R IGHT 4 UP 6 U1 9 M T 008 -A R 123 22 0K 1 4 3 2 B2 WK UP C9 1 d o not f it +3 V 3 R 120 10 0 R 122 4K 7 1 4 3 2 B4 US ER C9 3 10 0nF +3 V 3 R 117 10 0 R 121 4K 7 1 4 3 2 B3 Ta m pe r C9 2 10 0nF +3 V 3 R 124 10 0 MB 5 2 5 6 1 1 S TM 3 2 1 0 E -EVAL LC D & J o y s ti c k Vss 1 Vc c 2 VO 3 CL K 4 SID 5 CS 6 A 7 K 8 U1 8 HX M 1 220 32-GB 1 ( do n ot f it ) +3 V 3 R7 9 0 R7 6 do not f it R7 4 d o not f it +5 V +3 V 3 C6 4 10 0nF R 104 0 R 103 0 R 102 0 R 100 0 R 101 0 R 110 33 0 R 106 0 R 111 0 +3 V 3 +3 V 3 JO Y _S E L JO Y _D O WN JO Y _L E F T JO Y _R IGH T JO Y _U P LC D_ C S LC D_ C L K LC D_ DI R E S ET# L C D _ back li g ht An ti _T am pe r WAK E U P Us er _ B u tto n R1 0 5 do n ot f it R 107 0 +3 V 3 Joy s ti c k TFT L C D Gr a y L C D T a m per B u tt o n W a ke u p B u tt o n U s er B u tt o n D[ 0. .15] A[ 0. .23] A[ 0. .23] D[ 0. .15] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 D1 2 D1 3 D1 4 D1 5 FSM C_ N W E FSM C_ N O E A0 CS 1 RS 2 WR /S C L 3 RD 4 RE SE T 5 VDD 24 VC I 25 GN D 26 GN D 27 BL _V D D 28 B L _C o ntr ol 23 BL _G N D 22 PD 1 6 PD 2 7 PD 3 8 PD 4 9 PD 5 10 PD 6 11 PD 7 12 PD 8 13 PD 10 14 PD 11 15 PD 12 16 PD 13 17 PD 14 18 PD 15 19 PD 16 20 PD 17 21 SD O 29 SD I 30 CN 16 Co nn ec to r t o Mo th er b o ard R7 8 do not f it R7 5 do not f it R7 7 0 R8 0 0 LC D_ DO PG 7 PD 3 PG 14 PG 13 PG 15 PG 8 P C1 3 PA 0 PG 12 PD 5 PD 4 PA 8 PA 6 PA 5 PA 7 PF1 0 FSM C_ N E 4 JP 2 6 JP 2 7

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Figure 22. SD card and smartcard

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Tit le : N u m b er : R ev : S heet o f D .2 (PC B. S CH ) Da te : 200 8 -05-2 1 MB 6 7 2 7 1 1 S TM 3 2 1 0 E -EVAL S D& S m a rt C a rd +3 V 3 M icro S D C ard _CL K M icro S D C ard _CMD Mi c ro S D c a rd VC C 1 RST 2 CL K 3 NC 4 GN D 5 NC 6 I/ O 7 NC 8 18 17 CN 18 C 816 CL K D IV 1 1 CL K D IV 2 2 5V/ 3V 3 P GND 4 C1 + 5 Vdd p 6 C1 -7 Vup 8 PRE S 9 PRE S 10 I/ O 11 AUX 2 12 AUX 1 13 C GND 14 CL K 15 RST 16 Vc c 17 P O R ADJ 18 CM D V C C 19 RST IN 20 Vdd 21 GN D 22 OF F 23 XTA L 1 24 XTA L 2 25 I/ O U C 26 AU X 1U C 27 AU X 2U C 28 U1 7 S T 80 24C DR C 87 10 0nF C8 6 33 0nF C8 2 47 uF +5 V C 89 10 0nF C9 0 10 0nF R 118 10 0K +3 V 3 R9 0 4K 7 +3 V 3 R 108 10 K R 109 10 K +3 V 3 C1 2 10 0nF C8 4 47 uF +3 V 3 R9 1 10 K +3 V 3 R9 4 0 R7 1 0 R9 3 10 K TP 14 AUX 2 TP 15 AUX 1 Sm art C ard _ 3/ 5 V Sm art C ard _ IO Sm art C ard _ R ST Sm art C ard _ C L K Sm art C ard _ O FF Sm art C ard _ C M D V C C S m a rt C a rd SM S0 64 FF o r SMS1 28 FF 1 2 3 4 5 6 7 8 SW2 ₉ SW1 ₁₀ CN 13 PJ S0 0 8-2 0 00 M icro S D C ard _D 0 M icro S D C ard _D 1 M icro S D C ard _D 2 M icro S D C ard _D 3 Mi cro S D C ar d_ D et ec t PB 12 PB 0 PC6 PC 7 PB1 1 PB 10 PC8 PC9 PC1 0 PC1 1 PD 2 PC1 2 R1 30 47 K R 131 47 K +3 V 3 R 129 0 R 133 47 K R 134 47 K R 132 47 K PF1 1

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Figure 23. Motor control

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Tit le : N u m b er : R ev : S h eet o f D .2 (PC B. S CH ) Da te : 200 8 -05-2 1 R7 3.3 K _C8 _1nF +3 V 3 +3 V 3 +5 V R8 0 C7 100nF C6 10 0nF R5 0 C2 2 do n o t f it C1 3 do n o t f it C9 do n o t f it MB 6 7 2 8 11 S TM 3 2 1 0 E -EVAL M o to r C o n tr o l C6 0 do n o t f it C5 do not f it C2 10nF C4 do not f it C3 do not f it R4 0 R3 0 R6 0 R1 0 JP 2 0 C5 1 do not f it EM ER GE NC Y S T O P 1 MC -U H 3 MC _ U L 5 MC _ V H 7 MC _ V L 9 MC _ W H 11 MC _ W L 13 CU RR E N T A 15 CU RR E N T C 19 CU RR E N T B 17 N T C B Y PA SS R E L A Y 21 DI S S IP A TI VE B R AKE 23 +5 V P O W E R 25 PFC S Y N C 27 PFC P W M 29 En co de r A 31 En co de r B 33 GN D 2 GN D 4 GN D 6 GN D 8 GN D 10 GN D 12 BU S V O L T A G E 14 GN D 16 GN D 18 GN D 20 GN D 22 GN D 24 H eat s in k T e m p er at u re 26 3. 3 V P o w er 28 GN D 30 GN D 32 E n co d er In d e x 34 CN 1 M C _ c onn ec to r M C _ E mer g en cy S T O P MC _ C u rre n tA MC _ C u rre n tB MC _ C u rre n tC MC _ P F C s yn c 1 MC _ P F C s yn c 2 MC _ W L MC _ V H MC _ V L MC _ U H MC _ U L MC _ W H MC _ N T C M C _ D is sip a tive B ra ke M C _P F C pw m MC _ E n A MC _ E n B M C _ H eat si n k T em p erat u re M C _ B usVo lta g e MC _ E n In d e x R6 3 10 0K JP 2 C1 do n o t f it M o to r cont rol c o n n e c tor D efau lt s e tt in g : O p en De fa ult se tt ing : O p e n PA 6 PC6 PA 7 PC7 PB0 PC8 PB1 PA 3 PA 0 PA 1 PA 2 PC 0 PC3 PB4 PB5 PB1 2 PD 2 PC1 PC2 PC5 BN C1 BN C2 BN C3

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Figure 24. JTAG and trace connectors

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Tit le : N u m b er : R ev : S he et o f D .2 (PC B. S CH ) Da te : 200 8 -05-2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CN 7 FT SH -1 1 0-0 1-L -D V MB 6 7 2 9 1 1 S TM 3 2 1 0 E -EVAL J T AG &T r a ce +3 V 3 R5 8 10 K R5 4 10 K R5 3 10 K R5 9 10 K R5 5 do not f it +3 V 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CN 9 JT AG +3 V 3 +3 V 3 R4 8 10 K R4 7 10 K R5 2 10 K JP 1 9 R6 4 10 K R4 9 0 R5 0 do n ot fi t R6 0 0 R6 1 do n ot fi t TDI RE S ET# TR AC E_ D3 TR AC E_ D2 TR AC E_ D1 TR AC E_ D0 TR AC E_ C K TR S T T M S/ SW D IO TC K/ SW C L K TDO /S W O Tr a ce connect o r JT A G c onnect o r D efau lt s et ti ng : O pen PB4 PB3 PA 15 PA 14 PA 13 PE 2 PE 3 PE 4 PE 5 PE 6 KE Y

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Figure 25. Power supply

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Tit le : N u m b er : R ev : S heet o f D .2 (PC B. S CH ) Da te : 200 8 -05-2 1 Vi n 3 GND ₁ Vou t 2 U1 2 LD 108 6D2 M 3 3 C6 1 22 0uF C6 9 47 uF C1 1 10 0nF +5 V TP 5 3V3 SV 1 SG 2 CV 3 CG 1 4 CG 2 5 CG 3 6 U1 6 B NX0 02-0 1 C8 1 10 uF E5 V TP 4 5V +5 V R 127 30 0 12 LD 5 red J u mper for c hoi ce b etw een pow er c o nnec tor , U S B c o n n ec tor or d au ghte r b o a rd TP 16 Gr ou nd 1 2 3 CN 17 DC -1 0 B Z1 SM A J5. 0A -T R C8 5 10 0nF 1 2 3 U1 5 ZE N05 6V13 0A2 4LS +3 V 3 1 2 3 4 5 6 JP 1 3 MB 6 7 2 1 0 1 1 S TM 3 2 1 0 E -EVAL P o w e r D5 V U5 V E 5 V Pow e r r e g u l a to r R4 2 47 R4 1 0 VR EF -L1 BE A D C5 0 10 uF C4 6 10 nF JP 1 2 +3 V 3 VDD A VDD BT 1 C R 122 0 ho lde r Vba t 3 2 1 JP 1 +3 V 3 VDD A VR EF + C4 5 10 nF TP 3 VR E F VD D _7 62 VB A T 6 V SS_ 5 16 VD D _5 17 V SSA 30 VR EF -31 VR EF + 32 VD D A 33 V SS_ 4 38 VD D _4 39 V SS_ 6 51 VD D _6 52 V SS_ 7 61 VS S _10 12 0 V SS_ 1 71 VD D _1 72 V SS_ 8 83 VD D _8 84 V SS_ 9 94 VD D _9 95 V SS_ 2 10 7 VD D _2 10 8 VDD _10 12 1 V SS_ 3 14 3 VD D _3 14 4 VS S _11 13 0 VDD _11 13 1 U8 B S T M 32F 10 3ZE T 6 M CU p o we r C2 3 10 0nF C3 2 10 0nF C3 8 10 0nF C2 6 10 0nF C1 9 10 0nF C1 7 10 0nF C3 6 10 0nF C3 5 10 0nF C3 3 10 0nF C2 5 10 0nF C1 8 10 0nF VD D VD D De fa ult s ett ing : 5 <-> 6 De fa ult se tt ing : 2 <-> 3

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Figure 26. SRAM and Flash

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Tit le : N u m b er : R ev : S heet o f D .2 (PC B. S CH ) Da te : 200 8 -05-2 1 +3 V 3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 +3 V 3 A [0. .23] D [0. .15] RB 7 R 8 E 9 VDD 12 VS S 13 CL 16 AL 17 W 18 WP 19 I/ O 0 29 I/ O 1 30 I/ O 2 31 I/ O 3 32 VS S 36 VDD 37 I/ O 4 41 I/ O 5 42 I/ O 6 43 I/ O 7 44 U3 NAN D 51 2W3 A 2C N6 E +3 V 3 A16 A17 +3 V 3 C_ N E 3 C_ N E 2 FSM C_ N C E 2 C_ N W E C_ N O E C_ N W A IT R1 9 10 K D[ 0. .15] A[ 0. .23] MB 6 7 2 1 1 1 1 S TM 3 2 1 0 E -EVAL S RA M & F L A S H 1 2 3 JP 7 C2 1 10 0nF C2 0 10 0nF C8 8 10 0nF C6 2 10 0nF R1 7 10 K +3 V 3 R2 0 10 K +3 V 3 C7 5 10 0nF C6 3 10 0nF C2 4 10 0nF R1 3 10 K C1 0 10 0nF R2 3 10 K +3 V 3 R2 4 10 K R1 2 10 K +3 V 3 JP 5 A0 A0 A17 A18 +3 V 3 +3 V 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 D1 2 D1 3 D1 4 D1 5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1 0 D1 1 D1 2 D1 3 D1 4 D1 5 D0 D1 D2 D3 D4 D5 D6 D7 R2 2 0 R1 6 10 K R1 5 0 +3 V 3 R2 1 0 R1 8 10 K R2 5 do no t f it D efau lt s et ti ng : O pen D ef ault se tt ing : 2 <-> 3 A4 B4 A3 B3 A2 A5 A1 A4 A0 A3 CE B5 I/ O 0 B6 I/ O 1 C5 I/ O 2 C6 I/ O 3 D5 VC C D6 VS S D1 I/ O 4 E5 I/ O 5 F5 I/ O 6 F6 I/ O 7 G6 WE G5 A16 E4 A15 F4 A14 F3 A13 G4 A12 G3 A11 H5 A10 H4 A9 H3 A8 H2 I/ O 8 B1 I/ O 9 C1 I/ O 1 0 C2 I/ O 1 1 D2 VC C E1 I/ O 1 2 E2 I/ O 1 3 F2 I/ O 1 4 F1 I/ O 1 5 G1 BL E A1 BH E B2 OE A2 A7 D4 A6 C4 A5 C3 A17 D3 A18 H1 VS S E6 U1 IS 61W V 512 16B L L -10M LI A2 2 B8 A1 5 D7 A1 4 C7 A1 3 A7 A1 2 B7 A1 1 D6 A1 0 C6 A9 A6 A8 B6 A1 9 D5 A2 0 D4 W A5 RP B5 A2 1 C5 Vp p /W P B4 RB A4 A1 8 C4 A1 7 B3 A7 A3 A6 C3 A5 D3 A4 B2 A3 A2 A2 C2 A1 D2 VC C D8 A0 E2 E F2 VS S E8 G G2 DQ 0 E3 DQ 8 F3 DQ 1 H3 DQ 9 G3 DQ 2 E4 DQ 10 F4 DQ 3 H4 DQ 11 G4 VC C F1 DQ 4 H5 DQ 12 F5 DQ 5 E5 DQ 13 G6 DQ 6 H6 DQ 14 F6 DQ 7 E6 DQ 15A-1 G7 VS S H7 BY T E F7 A1 6 E7 VC C G5 VS S H2 U2 M 29W 128 GL7 0ZA6 E C1 5 10 0nF M 29W 128 GH7 0ZA6 E NAN D 51 2W3 A 2B N6 E PE 1 PE 0 PD 5 PG 9 PD 6 PD 4 PG 10 PD 7 PG 6 C_ N B L 0 C_ N B L 1 C_ IN T 2 S2 9G L 12 8P9 0 FFIR2 0 R ev D. 2 m odi fi ca ti on : r ef er en ce s of NO R f la sh u se d f o r U2 u pda te d

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Figure 27. Color LCD module

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Tit le : N u m b er : R ev : S heet o f A. 1(PC B. S CH ) Da te : 200 8 -0 3 -2 0 MB 6 9 4 1 1 Co lo r L C D m o d u le w it h 1 6 b it p a r a lle l in te rf a ce En ab le 1 Do tC lk 2 HS YN C 3 VS YN C 4 CS 5 WR /S C L 6 SD I 7 RS 8 NC 9 RD 10 RE SE T 11 PD 0 12 PD 1 13 PD 2 14 PD 3 15 PD 4 16 PD 5 17 PD 6 18 PD 7 19 PD 8 20 PD 9 21 PD 10 22 PD 11 23 PD 12 24 PD 13 25 PD 14 26 PD 15 27 PD 16 28 PD 17 29 VDD 30 VC I 31 VC I 32 NC 33 NC 34 NC 35 NC 36 NC 37 NC 38 NC 39 GN D 40 NC 41 NC 42 NC 43 NC 44 GN D 45 SD O 46 NC 47 NC 48 NC 49 GN D 50 GN D 51 A 52 K 53 CN 1 F H 26 -51S -0 .3 S H W( 05 ) En ab le Do tC lk HS YN C VS YN C CS WR RD RS #R ES E T A K PD 0 PD 1 PD 2 PD 3 PD 4 PD 5 PD 6 PD 7 PD 8 PD 9 PD 10 PD 11 PD 12 PD 13 PD 14 PD 15 PD 16 PD 17 3 0 -p in c o nn ect o r to m o th er b o ar d on ly f or 16 bit syst em i n te rf ac e o f co lor L C D CS RS WR RD #R ES E T VDD VDD BL G N D BL V D D B L _C o ntr ol Ena ble DotC lk HSY NC VSY NC VDD RP 1 10 K C1 1u F/ 50V R4 4K 7 R3 4K 7 SD O SD I SDI SDO PD 1 PD 2 PD 3 PD 4 PD 5 PD 6 PD 7 PD 8 PD 10 PD 11 PD 12 PD 13 PD 14 PD 15 PD 16 PD 17 AM 240 320 L8T NQW 01H Z1 ST PS1 L 4 0M C3 1u F/ 50V L1 22 uH R6 15 BL G N D GN D 1 Vin 2 S HDN 3 Rs et 4 FB 5 LD S 6 Vou t 7 SW 8 U1 ST LD 20D -C 8 BL V D D R5 10 0K C2 2.2 uF R7 0 R8 do n ot f it BL V D D B L _C o ntr ol BL G N D BL G N D BL G N D CS 1 RS 2 WR /S C L 3 RD 4 RE S E T 5 VD D 24 VC I 25 GN D 26 GN D 27 BL _V D D 28 B L _C o ntr ol 23 BL _G N D 22 PD 1 6 PD 2 7 PD 3 8 PD 4 9 PD 5 10 PD 6 11 PD 7 12 PD 8 13 PD 10 14 PD 11 15 PD 12 16 PD 13 17 PD 14 18 PD 15 19 PD 16 20 PD 17 21 SD O 29 SD I 30 CN 2 Co nn ec to r t o Mo th er b oard RP 3 d o not f it RP 2 d o not f it RP 4 d o not f it RP 5 d o not f it PD 0 PD 1 PD 2 PD 3 PD 4 PD 5 PD 6 PD 7 PD 8 PD 9 PD 10 PD 11 PD 12 PD 13 PD 14 PD 15 PD 16 PD 17 R1 0 4K 7 R9 4K 7 SD O SD I R2 do not f it R1 do not f it RD RS

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STM3210E-EVAL IO assignment UM0488

Appendix A

STM3210E-EVAL IO assignment

Table 29. STM3210E-EVAL IO assignment

Pin # Pin name STM3210E-EVAL IO assignment

1 PE2 Trace_CLK/FSMCA23 2 PE3 Trace_D0/FSMCA19 3 PE4 Trace_D1/FSMCA20 4 PE5 Trace_D2/FSMCA21 5 PE6 Trace_D3/FSMCA22 6 VBAT +3V3 or battery

7 PC13-ANTI_TAMP Anti-tamper button 8 PC14-OSC32_IN 32K OSC 9 PC15-OSC32_OUT 32K OSC 10 PF0 FSMCA0 11 PF1 FSMCA1 12 PF2 FSMCA2 13 PF3 FSMCA3 14 PF4 FSMCA4 15 PF5 FSMCA5 16 VSS_5 GND 17 VDD_5 +3V3 18 PF6 LD2 19 PF7 LD3 20 PF8 LD4 21 PF9 LD5

22 PF10 LCD_CS for graphic LCD (optional)

23 OSC_IN 8MHz crystal X1

24 OSC_OUT 8MHz crystal X1

25 NRST Reset button B1

26 PC0 MC_ADC_123_10 pin14 (bus voltage)

27 PC1 MC_ADC11 pin 15 / BNC1

30 VSSA GND

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UM0488 STM3210E-EVAL IO assignment

33 VDDA +3V3

34 PA0-WKUP MC_TIM2_CH1 pin 31(Ena) / WAKEUP /USART2 CTS 35 PA1 MC_TIM2_CH2 pin 33 (EnB)/USART2 RTS

36 PA2 MC_TIM2_CH3 pin34 (EnIndex)/USART2 TX

37 PA3 MC_TIM6_CH4 pin 23 (dissipative brake)/USART2 RX

38 VSS_4 GND

39 VDD_4 +3V3

40 PA4 DAC1_Audio RIN

41 PA5 SPI_Flash_CLK / DAC2_Audio LIN / QST pin4

42 PA6 MC_STOP pin 1 (Emergency stop) / SPI_Flash_MISO / QST pin8

43 PA7 MC_TIM5_CH1N pin 5 (UL) / SPI_Flash_MOSI / QST pin6

44 PC4 Potentiometer

45 PC5 MC_ADC_12_15 pin 26 (heatsink temperature) 46 PB0 MC_TIM5_CH2N pin 9 (VL) / SmartCard_3/5 47 PB1 MC1_TIM5_CH3N pin 13 (WL) / QST pin7

48 PB2 Boot1/ NSS_SPI_Flash

49 PF11 QST pin9 / MicroSD card detection

50 PF12 FSMCA6 51 VSS_6 GND 52 VDD_6 +3V3 53 PF13 FSMCA7 54 PF14 FSMCA8 55 PF15 FSMCA9 56 PG0 FSMCA10 57 PG1 FSMCA11 58 PE7 FSMCD4 59 PE8 FSMCD5 60 PE9 FSMCD6 61 VSS_7 GND 62 VDD_7 +3V3 63 PE10 FSMCD7 64 PE11 FSMCD8 65 PE12 FSMCD9 66 PE13 FSMCD10

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STM3210E-EVAL IO assignment UM0488 67 PE14 FSMCD11 68 PE15 FSMCD12 69 PB10 Smart_IO 70 PB11 Smart Reset 71 VSS_1 GND 72 VDD_1 +3V3

73 PB12 Smart_CK / MC_pin21 (NTC) / Audio I2S_CMD

74 PB13 Audio I2S_CK 75 PB14 USB Disconnect 76 PB15 Audio I2S_DIN 77 PD8 FSMCD13 78 PD9 FSMCD14 79 PD10 FSMCD15 80 PD11 FSMCA16 81 PD12 FSMCA17 82 PD13 FSMCA18 83 VSS_8 GND 84 VDD_8 +3V3 85 PD14 FSMCD0 86 PD15 FSMCD1 87 PG2 FSMCA12 88 PG3 FSMCA13 89 PG4 FSMCA14 90 PG5 FSMCA15 91 PG6 FSMC_INT2 92 PG7 JOY_Select 93 PG8 User Button B4 94 VSS_9 GND 95 VDD_9 +3V3

96 PC6 MC_TIM5_CH1 pin 3 (UH) / Smart_ CMD / VCC/I2S_MCK 97 PC7 MC_TIM5_CH2 pin 7(VH) / Smartcard_OFF

98 PC8 MC_TIM5_CH3 pin 11 (WH) / MicroSD card D0

99 PC9 MicroSD card D1

100 PA8 MCO / LCD backlight /QST pin11

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UM0488 STM3210E-EVAL IO assignment 102 PA10 USART1 RX 103 PA11 USB DM 104 PA12 USB DP 105 PA13 Debug TMS 106 NC 107 VSS_2 GND 108 VDD_2 +3V3 109 PA14 Debug TCK

110 PA15 Debug TDI

111 PC10 IRDA TX / MicroSD card D2 112 PC11 IRDA RX /MicroSD card D3

113 PC12 MicroSD card CLK

114 PD0 FSMCD2

115 PD1 FSMCD3

116 PD2 Sd card CMD / MC1_TIM3_ETR pin 27 (PFCsync2)

117 PD3 JOY_Down 118 PD4 FSMCNOE 119 PD5 FSMCNWE 120 VSS_10 GND 121 VDD_10 +3V3 122 PD6 FSMCNWAIT 123 PD7 FSMCNE1 124 PG9 FSMCNE2 125 PG10 FSMCNE3 126 PG11 PDN of Audio DAC 127 PG12 FSMCEBAR3 128 PG13 JOY_Right 129 PG14 JOY_Left 130 VSS_11 GND 131 VDD_11 +3V3 132 PG15 JOY_Up 133 PB3 Debug TDO

134 PB4 Debug TRST/MC_TIM3_CH1 pin 27 (PFCsync1)

135 PB5 Temperature SMBIA / MC_TIM3_CH2 pin 29 (PFC pwm)/ QST pin10

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STM3210E-EVAL IO assignment UM0488

136 PB6 Audio I2C_SCL & Temperature SCL / QST pin3 137 PB7 Audio_I2C_SDA & Temperature SDA / QST pin5

138 BOOT0 BOOT0 139 PB8 CAN RX 140 PB9 CAN TX 141 PE0 FSMCBLN0 142 PE1 FSMCBLN1 143 VSS_3 GND 144 VDD_3 +3V3

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UM0488 Revision history

Revision history

Table 30. Document revision history

Date Revision Changes

5-May-2008 1 Initial release.

2-June-2008 2

Added information on NOR Flash references in Section 1.20 on page 15.