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Index Terms– Hybrid multilevel inverter, Space vector pulse width modulation (SVPWM), Total harmonic distortion (THD).

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AN ALGORITHM FOR MINIMIZING

THD IN MULTILEVEL INVERTERS

WITH SPACE VECTOR MODULATION

R.Karthikeyan,

Asst.Professor / EEE, Annai Mathammal Sheela Engineering College, Namakkal, Tamilnadu, India

Dr.S.Chenthur Pandian

Principal, Dr.Mahalingam College of Engineering and Technology, Pollachi, Tamilnadu, India.

Abstract

Multilevel inverters have been widely used in medium and high voltage applications. Different modulation techniques have been proposed to control the multilevel inverter. This paper presents a switching strategy for cascaded multilevel inverters, based on space vector modulation. The SVPWM can be applied practically in hybrid multilevel inverters with different voltage steps; it can be applied to most multilevel topologies. This paper proposes a new algorithm for hybrid multilevel inverters with unequal voltage steps under the space vector pulse width modulation (SVPWM). The proposed algorithm offers an intuitive method for minimizing the total harmonic distortion (THD) of the output voltage of the inverter and uses simple arithmetic for determining the sector and does not require lookup tables. The proposed techniques lead to a significant reduction in THD. Finally, the algorithm was implemented on a Digital Signal Processor (DSP) and the scheme is explained for a seven level inverter, and experimental results are presented for a seven level inverter.

Index Terms– Hybrid multilevel inverter, Space vector pulse width modulation (SVPWM), Total harmonic distortion (THD).

1.Introduction

In the field of medium and high- power application, multilevel inverters have emerged as an attractive choice [1]. Modulation methods for hybrid multilevel inverter can be classified according to the switching frequencies methods. The most widely used techniques for implementing the pulse width modulation (PWM) strategy for multilevel inverters are sine-triangle PWM (SPWM) and space vector PWM (SVPWM). In this, SVPWM is the most popular PWM technique due to its simplicity both in software and hardware; also it can be efficiently executed in a few microseconds, achieving similar results compared with other PWM methods. There are different techniques available for implementing SVPWM for multilevel inverters. SVPWM is considered a better technique of PWM implementation, as it provides the following advantages: i) better fundamental output voltage; ii) useful in improving harmonic performance and reducing THD; and iii) easier hardware implementation in digital signal processor. The topology of a cascade multilevel inverter is shown in Fig. 1. In general, the SVPWM implementation involves the sector identification, switching-time calculation, switching vector determination and optimum switching response in selection for the inverter voltage vectors. The sector identification can be done by coordinate transformation [9] or by repeated comparison of the three phase reference voltages [1].

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explained for a seven level inverter, and experimental results are presented for a seven level inverter to verify the performance of the proposed technique.

Figure1: Topology of multilevel inverter.

2.Proposed Multilevel Inverter Algorithm

An effective hybrid multilevel inverter must ensure that the total harmonic distortion (THD) in the voltage output waveform is small enough. This paper proposes a new algorithm for the hybrid multilevel inverter with unequal or varying voltage steps under the space vector modulation. The algorithm results in the minimal THD of output voltage of the cascaded multilevel inverter with unequal voltage steps. A new expression of THD is presented to simplify the derivation. Already we know some definitions and equations; the output voltage of the hybrid multilevel inverter is (2S+1) with the SVPWM modulation. Ep1, Ep2, Ep3 … Epn indicates the voltage steps in positive side and En1, En2, En3 … Enn indicates the voltage steps in negative steps. Θ1, Θ2, Θ3 … Θn are

the switching angles that indicates the on and off instance of switches inside the inverter [2]-[3], [6]. 2.1.Mathematical Formulation

The algorithm can be expressed from the basis waveform by applying Fourier series analysis, the amplitude of any odd nth harmonic can be expressed as,

( )

1

4

cos

n

n k k k

V

E

n

n

π

=

θ

=

(1.0)

where n is an odd harmonic and Θk is the kth switching angle. The amplitude of all even harmonics is zero.

The modulation index m is defined as,

1 1

4

n

i i

V

m

E

π

=

=

(2.0)

Vn total harmonic component and V1 is the fundamental harmonic component.

The voltage THD is defined as

2 2 3,5,7,... 1

n

n

V

THD

V

=

=

(3.0)

Now, to find the problem and to implement an algorithm for the following variable inputs of the inverter V1,

V2, V3 …, Vn. Modulation index term m. Output of the algorithm Θ1, Θ2, Θ3 … Θn such that THD is minimum

[9]. The inputs V1, V2, V3 …Vn come from dc capacitor voltages or the additions and subtractions of dc-capacitor

voltages in the inverters.

The dc-capacitor voltage is measured by using sensors. The input m is determined by a controller in multilevel inverter. The pulse angles Θ1, Θ2, Θ3 … Θn are used by the inverter to control the switches [10]. It is the

important to note that minimizing voltage THD is desirable in some applications. In some high power applications one desires to limit each order harmonic to certain maximum allowed values. For the three phase system, the triple order harmonic can be cancelled without help from modulation techniques; yet it is desired to minimize THD for certain applications [10].

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(

)

2 1

1

n

k k

k

m

e

μ ρ

=

=

(4.0) where, 1 k k n l i

E

e

E

=

=

(5.0)

1 1

/ 2

/ 2

nk i k i k n i n i

E

E

E

E

μ

= =

=

(6.0)

The switching angles are determined by,

(

)

sin

k k

θ

=

μ ρ

(7.0) The output voltages of the inverter is,

(

2

)

1 k k k k k

k

V

=

=

E V

θ

V

π θ

+

V

π θ+

+

V

π θ+ (8.0) where V is unit function. By Fourier series expansion,

( )

1,3,5,... n

sin

n

V

V

n

θ

=

=

(9.0)

where,

( )

1 1 1,3,5,..

4

cos

n n

V

E

n

n

π

θ

∞ =

=

(10.0)

Modulation index m for the basic output voltage

( )

1 1 1

cos

1

4

4

n

m

π

V

π

E

n

θ

=

=

=

(11.0)

The THD is expressed as

2 2 3,5,7,... 1 n n

V

d

V

∞ =

=

(12.0)

2.2.Structure of the Algorithm

The flow diagram of the proposed algorithm to find minimum THD is shown in Fig.2. The control processing unit calculates the basic parameters to apply a switching state. The input supply is the amplitude of the voltage steps and modulation index m, the initial value of ρo.

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The modulation index mc is calculated for various iterations. The difference between two modulation index

terms is calculated.

c

m m

<

δ

(13.0)

where, δ – reference value to increases (or) decreases the pulse generation in the pulse generator.

If the difference between two modulation index terms is less than reference value δ, the proposed algorithm outputs the optimal switching angles [9]. The iteration method is used to solve and to find minimization of the voltage THD.

3.Principles of the Proposed SVPWM technique

The SVPWM technique can be easily extended to all multilevel inverters [1]. This section explains the proposed technique for the generation of SVPWM for a five-level inverter. By using the space-vector diagram, the basic principles of the proposed SVPWM method can be easily explained. Fig.3 shows the space vector diagram of a five level inverter [1], [6]. The SVPWM implementation involves two phases: i) Selecting the switching vector and ii) Determining the Center of the subhexagon.

Figure 3: Space vector diagram for a five level inverter.

3.1. Selection of the Switching Vector

In the proposed method, the small triangles formed by the adjacent voltage space vectors are called sectors. Such six sectors around a space vector forms a hexagon called subhexagon. The space vector modulation diagram of a multilevel inverter can be viewed composed of a number of subhexagons. Sector identification is done by determining the triangle that encloses the tip of the reference space vector. The shaded region in Fig. 4 shows two subhexagons. They are represented as “subhexagon I” having vector 000 as the centre and “subhexagon II” having the vector 032 as the centre. Another “subhexagon III” is also considered, having a vector 330 as the centre. The inner subhexagon can be viewed as a space vector diagram of a two-level inverter whose inverter voltage vectors switch between the lower most levels. Subhexagon II can be also viewed as a space vector diagram of a two level inverter whose; voltage vectors involve higher levels [1], [10].

The shifting of subhexagon in the space vector diagram of a multilevel inverter to the zero vector 000 simplifies the switching time calculations associated with multilevel inverters. The shifting of subhexagon II in the space vector diagram of a multilevel inverter toward the zero vector 000 involves the mapping of the sectors of subhexagon II to the sectors of the inner subhexagon. This is done by subtracting the vector at the centre of the subhexagon II from its other vector.

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In a reverse approach of mapping, the inner subhexagon can be mapped to subhexagon II by adding the voltage space vector at the centre of subhexagon II to the vector of the inner subhexagon. Consider the voltage vectors 000, 001, 101 and 111 associated with sector 5 of the inner subhexagon and the voltage space vector 032 which is the vector at the centre of subhexagon II. Adding the voltage space vector 032 to the voltage space vector associated with sector 5 of the inner subhexagon gives the vectors 032 (001+033), 022(101+022) and 421(100+021), which are the vectors associated with sector 5 of subhexagon. Also, the voltage space vector associated with any subhexagon can be generated by adding the vector at the centre of the particular subhexagon to the voltage space vector of the corresponding sectors in the inner subhexagon. In this paper, the mapping of the inner subhexagon to any other outer subhexagon called as reverse mapping is used to generate the vectors associated with any sector in the space vector diagram of the multilevel inverter.

3.2. Determining the Centre of the subhexagon

The space vector diagram of a five-level inverter, shown in Fig. 5 can be viewed as form of five levels with four layers. These levels are represented as Level 1 to 5. The instantaneous reference space vector lying in layer4 (P=4) and within the S1 region. Depending upon the layer of operation of the instantaneous reference space vector, all vectors for the center of the subhexagon are generated, and the vector which is closest to the reference space vector is taken as the center of the subhexagon. Fig. 5 also shows the six 60o regions S1,S2, S3, S4, S5,and S6. The subhexagon associated with the instantaneous reference space vector can be considered as centered on the inner side of layer 4.

Figure 5: Levels in the space vector diagram of a five-level inverter.

The instantaneous reference space vector can be resolved in to the axes Vx, Vy and Vz using the following where Va, Vband Vc are the instantaneous amplitude of the three reference phase voltages [1]:

(

)

(

)

(

)

3 2 3

2 3

2

x a c

y b a

z c b

V

V

V

V

V

V

V

V

V

=

=

=

(14.0)

The axis lying in the 60region which contains the instantaneous reference space vector will have maximum magnitude among the values.

4. Improved voltage THD by Proposed SVPWM for multilevel Inverter.

The proposed algorithm presented in this paper focus on getting minimal voltage THD. The SVPWM algorithm is used in multilevel inverter with identical voltage steps. The algorithm in this paper is a modified version of the existing method. It uses the information of measured voltage THD for multilevel inverter with unequal or varying voltage steps. The proposed algorithm shows improvement of the voltage THD for multilevel inverter with unequal voltage steps.

The comparisons are carried out for the following two cases in a seven level inverter 1) E2and E3drop

to 0.65 and 0.55 p.u. respectively and 2) E2and E3 drop to 0.85 and 0.65 p.u. respectively, where E1 is 1p.u. in

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5.Simulation and Experimental Results

5.1.Simulation Results

To verify the proposed schemes, a simulation model for a three phase seven level cascaded H-Bridge inverter is implemented as shown in Fig.7. The simulations were performed by using MATLAB SIMULINK. It also helps to confirm the SVPWM switching strategy which can be implemented in a DSP. The simulation parameters for constant switching frequency for Space vector pulse width modulation are as following, 5KW rating, three phase load R = 100 ohms, L = 20 mH, each source Vdc = 5V, switching frequency 2KHz. Phase leg voltages have been calculated and drawn for SVPWM Method shown in Fig.8.

Fig. 7. Simulation diagram of three phase Multilevel Inverter

Fig. 8. Simulation result for Five-level inverter with SVPWM.

Fig.9.Space Vector Pulse Width Modulation Harmonic Spectrum

5.2. Experimental Results

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Fig.10. Output voltage of the multilevel inverter.

Fig.11. Output harmonics of Single phase cascaded multilevel

Fig.12. Hardware setup of Single phase cascaded multilevel

6. Conclusion

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References

[1] J. Rodriguez, J.-S. Lai, and F. Z. Peng, 2002. “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738.

[2] Y. Liang and C. O. Nwankpa, 1999. “A new type of STATCOM based on cascading voltage-source inverters with phase-shifted unipolar SPWM,” IEEE Trans. Ind. Appl., vol. 35, no. 5, pp. 1118–1123.

[3] S. Sirisukprasert, J.-S. Lai, and T.-H. Liu, 2002. “Optimum harmonic reduction with a wide range of modulation indexes for multilevel converters,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 875–881.

[4] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, 1999. “Multilevel converters for large electric drives,” IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 36–44.

[5] L. Li, D. Czarkowski, L. Yaguang, and P. Pillay, 2000. “Multilevel selective harmonic elimination PWMtechnique in series-connected voltage inverters,” IEEE Trans. Ind. Appl., vol. 36, no. 1, pp. 160–170.

[6] K. Zhou and D. Wang, 2002 “Relationship between space-vector modulation and three-phase carrier-based PWM: A comprehensive analysis,” IEEE Trans. Ind. Electron., vol. 49, no. 1, pp. 186–196.

[7] G. Carrara, S. G. Gardella, M. Archesoni, R. Salutari, and G. Sciutto, 1992. “A new multilevel PWM method: A theoretical analysis,” IEEE Trans. Power Electron., vol. 7, no. 3, pp. 497–505.

[8] H. W. Van Der Broeck, H.-C. Skudenly, and G. V. Stanke, 1988. “Analysis and realization of a pulse width modulator based on voltage space vectors,” IEEE Trans. Ind. Appl., vol. 24, no. 1, pp. 142–150.

[9] N. Celanovic and D. Boroyevich, 2001. “A fast space-vector modulation algorithm for multilevel three-phase converters,” IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 637–641.

Figure

Figure 2: Flowchart of the Algorithm
Figure 3: Space vector diagram for a five level inverter.
Figure 5: Levels in the space vector diagram of a five-level inverter.
Fig. 7. Simulation diagram of three phase Multilevel Inverter

References

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