Study of Si1-xGex Junction Formation for SOI Based CMOS Technology

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DU, YAN. Study of Si1−xGex Junction Formation for SOI Based CMOS

Technology. (Under the direction of Dr. Veena Misra and Mehmet C. ¨Ozt¨urk.)

Si1−xGex source/drain technology has been sucessfully applied to bulk metal

oxide semiconductor field effect transistors (MOSFETs). Both channel mobility and source/drain contact resistivity are substantially improved with this tech-nology. In this dissertation, Si1−xGex junction formation for silicon on

insula-tor (SOI) based CMOS technology was investigated. Strain in epitaxially grown films on SOI films and silicon nanowires is studied using Raman spectroscopy and transmission electron microscope (TEM). For epitaxially grown Si1−xGex film on

SOI, there is lower degree of strain development in the SOI layer due to the rigid interface between the SOI and the burried oxide as compared to bulk. How-ever, for silicon nanowires on oxide, the situation is different since nanowires serve as compliant substrates. Part of the strain energy is transferred to sili-con nanowires. The sili-consistency between synthesized Raman peak shifts and the experimental measurements verified the strain sharing between the epitaxially grown Si1−xGex films and the silicon nanowires. Splittings of high order Laue

zone line (HOLZ) from a convergent beam electron diffraction (CBED) pattern was quantified to study the strain distribution in epitaxial Si1−xGexfilms grown

on silicon nanowires. It was found out in this study that elastic deformation of epitaxial Si1−xGex at free surfaces leads to strain relaxation at these surfaces.

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the nano-structures. Moreover, atomic layer deposition (ALD) Platinum is pro-posed for metal deposition on 3D epitaxial Si1−xGex source/drain. The uniform

deposition around 3D Si1−xGex films effectively increases the contact surface area

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Technology by

Yan Du

A dissertation submitted to the Graduate Faculty of North Carolina State University

in partial fulfillment of the requirements for the Degree of

Doctor of Philosophy

Electrical Engineering

Raleigh, North Carolina

December, 2007

APPROVED BY:

Veena Misra Mehmet C. ¨Ozt¨urk

Chair of Advisory Committee Co-chair of Advisory Committee

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Dedication

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Biography

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Acknowledgements

I am sincerely grateful to my advisor Dr. Veena Misra for her help and sup-port during my doctoral research work at NC State University. Dr. Misra provids insights into many aspects of my research on strain engineering. She helped me to not only shape my thinking, but also acted as a role model for me on time management, project organization, and interpersonal communication skills. The things I learned from her will benefit my career. I would also like to express my sincere gratitude to my co-advisor Mehmet C. ¨Ozt¨urk for sharing his expertise on Si1−xGexgrowth. I enjoyed those interesting and inspiring discusstions with him.

Moreover, I am deeply indebted to Dr. Gerd Duscher. Without his generous help on TEM CBED measurments, this work would not have been completed. His en-thusiasm on research work motivated me to understand CBED/HOLZ technique better. I would also like to thank Dr. Carlton Osburn for serving on my doctoral committee and his input over the course of my research.

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The graduate students and researchers in the research groups of Dr. Misra, Dr. ¨Ozt¨urk, and Dr. Duscher provided valuable help and support. I would like to thank Dr. Niv Biswas, Dr. Saurabh Chopra, Dr. Yanxia Lin, Dr. Yong Luo, Zhong Chen, Steven Novak, Bongmook Lee, Emry Alptekin, Byung-il Kwak, Dr. Wenjun Zhao, Eric Jones and Siddhartha Mal.

I would also like to thank Dr. Anuj Dhawan and Wingo Wang for proofreading the manuscript.

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List of Tables

1.1 Bulk silicon piezoresistance(PR coefficients measured by Smith) . 8 1.2 The PR coefficients for arbitrary crystallographic directions of

uni-axial stress and current([l m n]:direction cosines) . . . 10

1.3 Expected percentage change in movility per 1GPa tensile(-1GPa compressive) channel stress based on piezoresistance coefficients. [1]) 12 2.1 Germanium content(x) in Si1−xGex layers determined by Raman Spectroscopy and SIMS . . . 23

2.2 Samples for UV Raman Study . . . 30

3.1 Process conditions for Si1−xGex epitaxy [2] . . . 45

3.2 Ansys Setup From Yeo’s paper . . . 50

3.3 Comparison between synthesized spectrum and experimental results 57 3.4 Parameters for future multigate CMOS technology . . . 58

4.1 EELS analysis of Si1−xGex epitaxial films on Silicon nanowires . . 68

4.2 Elastic Properties of Silicon and Germanium . . . 70

4.3 Measured HOLZ line splitting(mrad) . . . 72

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List of Figures

1.1 Transistor leakage current versus gate length. . . 2 1.2 Transistor drive current versus gate length. . . 2 1.3 Simplified schematic of valence-band splitting of strained-Si as a

function of gate drive . . . 6 1.4 Hole mobility for uniaxial strained-Si introduced Si1−xGex in the

source and drain [3] . . . 9 1.5 Schematic illustrating the UHV RTCVD system [2] . . . 14 1.6 Schematic illustrating the main processing chamber [2] . . . 14 1.7 Cross-sectional TEM of 1.0µmSi0.6Ge0.4film grown on (a)SOI(001)

and (b) Si(001) substrate [4] . . . 18 1.8 Cross-sectional TEM of (b) EPI Silicon and (c) EPI Si1−xGex film

grown on silicon nanowire . . . 18 2.1 Frequency of the three optical modes as a function of the Ge molar

fraction [5] . . . 22 2.2 Typical Raman spectrum for Si1−xGex films with different thickness. 25

2.3 Comparison of residue strain in Si1−xGex films between

experimen-tal data and simply compliant substrate theory. SOI body thick-ness is 30nm. . . 26 2.4 Impact of body thickness on residue strain. The epitaxial SiGe

thickness is 30nm . . . 28 2.5 Major processing steps for channel strain measurements . . . 31 2.6 High resolution TEM image of non-recessing 50% epitaxial Si1−xGexon

40nm SOI wafer . . . 32 2.7 UV raman data for channel region with non-recessed SiGe junctions 33 2.8 UV raman data for channel region with recessed SiGe junctions . 33 2.9 Parameters for simulation study . . . 35 2.10 Average Stress in the Channel with Different Body Thickness.

Si1−xGex is 10nm. Gate length is 14nm. . . 37

2.11 Average Stress in the Channel with Different Technology Node . . 37 2.12 Average Stress in the Channel with Different Raised Source Drain

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2.13 Average Stress in the Channel as a function of Source and Drain

length . . . 39

3.1 28% Facets of SiGe Epitaxial Growth around silicon nanowire . . 44

3.2 Cross Sectional TEM image of one minute growth of 17% Si1−xGex epitaxial on Silicon Nanowire . . . 46

3.3 Cross Sectional TEM image of one minute growth of 28% Si1−xGex epitaxial on Silicon Nanowire . . . 46

3.4 SEM image 17% Si1−xGexepitaxial growth on silicon nanowire were shown in (a) and (b). SEM image 50% Si1−xGex epitaxial growth on silicon nanowire were shown in (c) and (d). . . 47

3.5 Schematic of nanowire structure . . . 52

3.6 Elastic strain in X direction of 30% Si1−xGex . . . 52

3.7 Elastic strain in Y direction of 30% Si1−xGex . . . 53

3.8 Elastic strain in Z direction of 30% Si1−xGex . . . 53

3.9 Comparison between Si-Si Phonon of Synthesized and measured Raman Spectrum for Si1−xGex epitaxial film around Silicon Nanowire (a) synthesized Raman shift from relaxation position of Si-Si phonon for 60s deposition A on Si1−xGex films (b) synthesized Raman shift from relaxation position of Si-Si phonon for 60s deposition B on Si1−xGex films (c) measured Raman shift from relaxation position of Si-Si phonon for 60s deposition A on Si1−xGex films (d) mea-sured Raman shift from relaxation position of Si-Si phonon for 60s deposition A on Si1−xGex films . . . 60

3.10 Elastic Strain Simulation for nanowire MOSFET with 15nm gate length and 30% Si1−xGexjunction. The contour legend in (a) shows both tensile and compressive strain. (b) is a replot of (a) with only compressive strain legend. . . 61

3.11 Elastic Strain Simulation for nanowire MOSFET with 7.5nm gate length and 30% Si1−xGex junction The contour legend in (a) shows both tensile and compressive strain. (b) is a replot of (a) with only compressive strain legend. . . 61

4.1 Sketch of a low magnification CBED pattern showing the FOLZ ring and diffracted disks, together with the transmitted central disk, which has been magnified for sake of clarity. The three dark (deficit) lines in the central disk correspond to bright (excess) lines in the FOLZ. The diffracted disks are not scaled with the FOLZ ring: in a real pattern the FOLZ lines inside each disk would ap-pear are straight lines. . . 65

4.2 Sketch of the three possible rotations with respect to the electron beam direction:(a) rotation axis parallel to the beam, (b) rotation axis inclined with respect to the beam (c) rotation axis perpendic-ular to the beam [6] . . . 66

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4.4 Dynamic simulation shows the impact of sample thickness on HOLZ lines. (a) thickness=160nm (b) thickness=200nm (c) thickness=240nm (d) thickness=280nm . . . 75 4.5 Overlap of experimental measurements and kinematic simulation

for HOLZ line position at [661] zone axis. The color lines are from kinematic simulation. . . 76 4.6 EELS analysis of Si1−xGex epitaxial films on Silicon nanowires . . 76

4.7 High resolution TEM (HRTEM) image shows the good quality interface of Si1−xGex epitaxial film on Silicon nanowire . . . 77

4.8 Deformation shown by FE simulation after FIB sample preparation process. Only half of the sample was simulated. . . 78 4.9 Deformation along [110] direction of epitaxial Si1−xGex film on

sil-icon nanowire . . . 78 4.10 CBED patterns show the HOLZ splitting at different positions . 79 4.11 Comparison of deformation angle in silicon nanowire between CBED/HOLZ

line measurements and Finite Element Simulations . . . 79 4.12 Comparison of deformation angle in epitaxial film between CBED/HOLZ line measurements and Finite Element Simulations . . . 80 5.1 Typical trends of growth rate as a function of growth temperature

for the ALD process . . . 85 5.2 ALD Pt on Si1−xGexepitaxial films . . . 86

5.3 EELS analysis for Pt ALD on Si1−xGex epitaxy film . . . 87

5.4 SEM images of 70 cycles (a) and 100 cycles (b) ALD Pt on both SiO2and silicon . . . 88

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Chapter 1 Introduction

We are at 2007, 42 years after Gordon E. Moore made his famous prediction. Intel has been scaling the silicon CMOS technology to the 45nm node relent-lessly. Continued CMOS scaling will require the introduction of new materials and new device structures. The International Technology Roadmap for Semicon-ductors is a set of documents produced by a group of semiconductor industry experts. Figure 1.1 shows the ITRS’s requirements on gate leakage and source drain subthreshold leakage current. As devices are scaled down, leakage problem deteriorates. To get around the leakage problem, high-K material has been intro-duced into the 45nm node by Intel which reduces the gate leakage more than 10 times. In the same transistor, polysilicon gate has been replaced by metal gate to achieve low threshold voltage. This new gate stack technology enables 20% switching speed improvements.

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ITRS2006 0.0E+00 5.0E+02 1.0E+03 1.5E+03 2.0E+03 2.5E+03 3.0E+03

32 28 25 22 20 18 16 14

MPU Gate Length (nm)

Maximum Gate Leakage

Density (A/cm 2 ) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

Subthreshold Off-State _{Leakage Current (}

μ

A/

μ

m)

Figure 1.1: Transistor leakage current versus gate length.

ITRS2006 500.00 1000.00 1500.00 2000.00 2500.00

32 28 25 22 20 18 16 14

MPU Gate Length (nm)

Effective NMOS Drive Current(

μ

A/

μ

m)

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current.

Ids =

µef fεox

Lgtox

(Vdd−Vt)1.5 (1.1)

When we scale down the devices,VddandVthare relatively constant. However,

equivalent oxide thickness are scaled down. This causes higher vertical electrical field in the channel region which decreases the mobility substantially. Because of this, much effort has been put into mobility enhancement research. Strained silicon has proved itself to be a good interim solution for carriers mobility en-hancement. Alternative channel materials such as Ge, SiGe, III-V(GaAs etc) are actively under investigation. Among these candidates, strained silicon is the most economical way to enhance the mobility of both electrons and holes. SiGe junctions are integrated into 90nm node [7] to enhance hole mobility, while high stressed Etch Stop Layer has been used to increase electron mobility. Accord-ing to ITRS 2006 update [8], local strain technique should be extendable to at least the 32nm generation. It is also realized that the application of local strain technique will be a challenge beyond the 32nm generation.

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1.1 Strain Engineering’s impact on MOSFETs

Before we go into details of strain engineering, it makes sense to look at possible physical mechanisms which enhance carriers mobility. As Thompson pointed out in [9], there are three main reasons for carrier mobility improvements.

1. Low in-plane mass;

2. High out-of-plane mass;

3. High in-plane mass perpendicular to the channel direction.

The electron mobility in bulk-strained-Si along < 110 > direction is deter-mined by occupation and scattering in the ∆2and ∆4valleys and can be expressed

as:

µef f =

τ∆2n_m∆2_t +τ∆4n_m∆4

l

n∆2+n∆4

(1.2)

Strain will remove the degeneracy of the conduction band. When tensile bi-axial strain is applied as the result of pseudomorphic growth of Si on relaxed Si1−xGex(100) surface, the energy of the conduction-band minima of the four

valleys on the in-plane <100 >axes rises with respect to the energy of the two valleys on the <100 > axes perpendicular to the plane [10]. As a consequence, the electrons prefer to distribute at low energy valleys. Due to low in-plane mass, repopulation of electrons into ∆2 valley will effectively lower mobility. In

addition, warping of conduction band can produce a smaller mt. Furthermore,

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rel-evant phonon with right energy and momentum is absorbed or emitted. With energy splitting, the number of relevant phonons is dropped.

Even though the valence band has different band structure, the three mecha-nisms discussed above remain applicable. The high out-of-plane mass is related to mobility under high vertical electrical field. It is well known that the electronic states in the inversion layer under high vertical electrical field layer are quantized into subbands. Whether this energy splitting adds up or cancels out the energy splitting due to strain depends on the out-of-plane mass. Figure 1.3 shows the effect of strain and high vertical electrical field on the valence-band energy di-agram. Etop represents the top band with large out-of-plane mass for uniaxial

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Figure 1.3: Simplified schematic of valence-band splitting of strained-Si as a function of gate drive

1.1.1 Biaxial Strain Engineering

At the 1992 International Electron Device Meeting(IEDM), a research group from Stanford University reported on strained silicon long-channel MOSFETs fabricated on compositionally graded Si1−xGexbuffer layer. Welser [11] grew

Si1−xGexbuffers that were graded to 29% Ge at 750◦Con which surface channel

MOSFET is fabricated. They demonstrated that strained silicon nMOSFET with SiO2gate could improve the mobility of electron by 70% compared with

bulk silicon.

But some integration problems are realized with this biaxial strain scheme.

• Ge diffused out into channel;

• A substantial difference in doping diffusion property in Si1−xGex . [12]

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• Self-heating problem becomes severe because of low thermal conductivity in Si1−xGex

As pointed out in the previous section, hole mobility drops quickly when ver-tical effective field (Eef f) increases. While strained Si n-MOSFETs displays

elec-tron mobility enhancements over a wideEef f range, hole mobility in p-MOSFETs

with strained Si surface channel is improved primarily at low Eef f , and the

en-hancement ratio r approaches 1 at Eef f (1MV/cm) for substrate Ge fractions

below 30% [13]

In spite of these disadvantages, there remain efforts to combine strained silicon technologies with SOI technologies. IBM’s strained silicon directly on insulator (SSDOI) [14] removes compositionally graded Si1−xGex buffer layer which bypass

all the integration obstacles associated with Si1−xGex . IBM demonstrated that

when surface hole concentration is 1013 cm−2, the hole mobility enhancement is about 21%.

1.1.2 Uniaxial Strain Engineering

Initially, in-situ boron doped Si1−xGex is proposed as a novel low-temperature

source/drain and contact formation technology for sub-70nm CMOS [15]. In 2003, Intel introduced Si1−xGex junction technology into their 90nm pMOSFET

[16]. A unique selectively depositedSi0.83Ge0.17source-drain which demonstrated

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work, it is found that hole mobility is 50% more with Si1−xGex junctions. On

the nMOSFET side, a high stress Si3N4cap layer induces tensile strain in the

channel, which improves the electron mobility by 20% and the drive current by 10% relative to non-strained devices. Last, but not least, this performance enhancement is achieved at expense of 2% more fabrication cost. Since then, strain engineering has been adopted by every major semiconductor company. Figure 1.4 compares the high vertical field’s impact on the hole mobility for biaxial strain and uniaxial strain. It is clearly seen that uniaxial strain provides substantial mobility enhancement even under high gate drive.

1.1.3 Pizeoresistance Model

50 years ago, Smith reported for the first time the change of resistivity in both n and p types silicon and germanium [17]. The complete tensor piezoresistance has been determined experimentally for these materials and expressed in terms of the pressure coefficient of resistivity and two simple shear coefficients. Table 1.1 summarizes the bulk silicon piezoresistance coefficients.

Table 1.1: Bulk silicon piezoresistance(PR coefficients measured by Smith)

PR coefficients [10−11Pa−1] π11 π12 π44

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Figure 1.4: Hole mobility for uniaxial strained-Si introduced Si1−xGex in the

source and drain [3]

The piezoresistance is a second order tensor. We define ∆ ≡ ∆_ρρ and adopt the convention of Nye [18].

∆1 = ∆11, ∆2 = ∆22, ∆3 = ∆33, ∆4 = ∆23, ∆5 = ∆31, ∆6 = ∆12 (1.3)

Stress X may be written in a similar way. For a cubic crystal, the connection between ∆ and X may be written as,

∆ = ΠX, (1.4)

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crystal classes is used, it can be shown that Π reduces to Π =                    

Π11 Π12 Π12 0 0 0

Π12 Π11 Π12 0 0 0

Π12 Π12 Π11 0 0 0

0 0 0 Π44 0 0

0 0 0 0 Π44 0

0 0 0 0 0 Π44

                    (1.5)

Through coordinates transformation, PR coefficients along arbitrary direction can be obtained [19]. When uniaxial stress is applied to the bulk sample, there are two types of piezoresistance. Πl is used when uniaxial stress is parallel to

current flow direction. Πtis used when uniaxial stress is perpendicular to current

flow plane. Πv is used when uniaxial stress is in the current flow plane but

perpendicular to the current flow direction. Table 1.2 shows the PR coefficients for a right-handed Cartesian coordinate system whose three axes have direction cosines [l1 m1 n1], [l2 m2 n2], and [l3 m3 n3] with respect to the cubic axes.

It is well know that, the optimal surface/current orientation for nMOSFET

Table 1.2: The PR coefficients for arbitrary crystallographic directions of uniaxial stress and current([l m n]:direction cosines)

Stress Axes PR coefficients Formula

[l1 m1 n1] πl =π11−2(π11−π12−π44)(l12m21+m21n21+n21l12)

[l2 m2 n2] πv =π12+ (π11−π12−π44)(l21l22+m21m22+n21n22)

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and pMOSFET are (100)/ < 100> and (110)/ <110>. In this dissertation, all the experiments are conducted to measure the strain distribution for (110)/ < 110 > system. This is the case when fin sidewall is along <110 > with current flowing along < 1¯10 > on most common (100) wafer. Direction cosines for this case is summarized in the table.

x l1 = √1₂ m1 =−√1₂ n1 = 0

y l2 = √1₂ m2 = √1₂ n3 = 0

z l3 = 0 m3 = 0 n3 = 1

The corresponding PR coefficients are:

πl= 1₂(π11+π12+π44)

πv = 1₂(π11+π12−π44)

πt=π12

The change in mobility can be related to PR coefficients by:

∆µ µ =

−∆ρ

ρ =−ΠX (1.6)

Following this procedure, the mobility enhancement for two promising Fin ori-entations has been calculated by Shin [1]. From Table 1.3, it is easily seen that for PMOSFET, compressive stress along the channel and tensile stress perpendicular to the channel are desired.

1.2 Epitaxial SiGe Growth

This section provides a introduction on the fabrication tool and process used to generate the test structures for this work. Si1−xGex films were selectively grown

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Table 1.3: Expected percentage change in movility per 1GPa tensile(-1GPa com-pressive) channel stress based on piezoresistance coefficients. [1])

Stress in channel % Changes in mobility per GPa (100) channel with< 100>current direction

(110) channel with <110> current direction

Tensile Compressive

NMOS PMOS NMOS PMOS

σxx(along channel) 102.2% -6.6% -31.2% 71.8%

σyy(vertical to channel) -53.4% 1.1% -17.6% -66.3%

σzz(across channel) -53.4% 1.1% 53.4% -1.1%

1.2.1 UHVCVD system

The Si1−xGex was deposited using a custom system created by Prof. Ozturk

at North Carolina State university [20]. As Figure 1.5 shows, the UHV-RTCVD consists of three chambers, namely

1. Sample entry chamber(SEC);

2. Intermediate chamber(IC);

3. Main processing chamber(MPC).

The base pressure for three chambers are 10−4_{T orr, 10}−9_{T orr}_{and 10}−9_{T orr.The}

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transformation process. All pumps and gate valves used in this system are oil-free to minimize the hydrocarbon contamination. Four wafers are loaded into a cassette in entry chamber, and then moved to the intermediate chamber.

Only one wafer at a time is transferred onto a quartz wafer holder in main chamber for deposition. The wafer transfer between the chambers is achieved using a magnetically coupled transfer arm. To get better temperature uniformity across the wafer, a silicon carbide susceptor ring is usually adopted in commercial-ized CVD tool design. Within this custom system, the sample was heated from the top and the side by two lamp-banks. The top bank consists of eight 2kW tungsten-halogen lamps and the side bank consists of sixteen 1kW lamps. With side lamp-banks, the temperature gradient along the wafer radius is effectively reduced.

Surface passivation is important for high quality epitaxial Silicon/Si1−xGex films.

The efficiency of diluted HF surface preparation is well known in the molecular beam epitaxy (MBE) literature. As pointed out by [21], post HF dipped silicon surface is stable in air and free of silicon dioxide for a time period of minutes. The surface passivation procedure for this work is the standard RCA clean and 30 seconds of 1% HF dip, as detailed below;

1. 10min 70◦Chot bath 1:1:5 N H4OH :H2O2 :H2O;

2. 10min 70◦Chot bath 1:1:5 HCl :H2O2 :H2O;

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Figure 1.5: Schematic illustrating the UHV RTCVD system [2]

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After dilute HF dip, the wafers are loaded into entry chamber as soon as pos-sible. When the pressure is ready, the wafers are transfered through intermediate chamber then into main chamber. Once the base pressure of the main chamber is reached, the tungsten-halogen lamps are turned on to heat up the wafers. Two pyrometers and a closed loop feedback system are used to maintain a constant temperature during deposition. As soon as growth temperature is reached, the corresponding gaseous precursors, such as disilane (Si2H6), germane (GeH4: 10%

inH2), diborane, are released into the reactor. During the temperature rising up,

the debris on the quartz bell jar may replace hydrogen passivation on the silicon surface. To limit this kind of contamination, each deposition run is limited under two minutes.

1.2.2 Epitaxial SiGe on Compliant Substrates

Due to the lattice mismatch, strain energy is stored when Si1−xGex film is

deposited on the silicon substrate. As the film thickness increases, the stored elastic energy increases correspondingly. Once the film thickness is above a certain thickness, which is called critical thickness, it becomes energetically favorable to relieve this strain through misfit dislocations at EPI film/substrate interface. Strained SiGe layers that are grown thicker than the critical thickness, but remain strained and defect-free, are said to be metastable.

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also has limited thermal processing window. The metastable films are easily relaxed during high temperature processing steps.

To circumvent this dilemma, efforts are directed toward compliant substrate systems. An ideal compliant substrate would have a strain partition between the EPI film and substrate. In bulk/EPI system, because of the substantial volume of substrate, the misfit strain is approximately fully stored in EPI film. While in ideal compliant substrate, the thickness of substrate is in the same order as EPI films or even less than EPI film. The misfit strain will be stored both in substrate and EPI films which effectively increases the EPI critical thickness.

Besides misfit dislocation, threading dislocations also plague the electrical performance. Threading dislocations across device junctions provide a leakage path which is unacceptable in device applications. For thick substrate, misfit dislocations at the interface always experience a pulling force (image force) at-tracting them towards the film surface. Therefore, dislocations climb or slip into EPI films. However, if thin substrates are used, image force tends to pull the interface dislocations away from the films and into substrate. Consequently, the decrease of image force toward the grown film or the increase of image force toward the substrate can reduce the density of threading dislocation in EPI films which improve the quality of EPI films. This technique is applied to Si1−xGex EPI on

top of SOI wafer. Young [4] reported high quality relaxedSi0.6Ge0.4 films as thick

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substrates.

From device point of view, there are applications which require both good EPI film and substrate. For MOSFET applications, strain engineering should keep both the Si1−xGex and silicon strained. Strained Si1−xGexcan tune the valance

band edge to a point which gives a small barrier height. Strained silicon can enhances the hole mobility substantially in the channel. Driven by this kind of application, the thickness of EPI films must be well designed to prevent the relaxation and dislocation pileup in the compliant substrate.

The vertical silicon Fin provides a unique opportunity to engineer EPI Si1−xGexon

top of compliant substrate. As pointed out in [22], cross-sectional TEM analysis showed that dislocation density is much smaller than that for bulk substrate sam-ples. Strain partition and image force reduction both contribute to the better epitaxial Si1−xGex film. In FinFET applications, facets also helps to tune the

properties of epitaxial film. SEMATECH demonstrated that EPI Si1−xGex on

Silicon nanowire takes (113) facet.

1.3 Thesis Overview

The main work of this dissertation concentrates on epitaxial Si1−xGexon SOI

wafers and silicon nanowires.

Chapter two will discuss the Raman spectroscopy measurement and the im-plication on strain distribution of epitaxial Si1−xGexfilms on SOI wafers.

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Figure 1.7: Cross-sectional TEM of 1.0µm Si0.6Ge0.4 film grown on (a)SOI(001)

and (b) Si(001) substrate [4]

Figure 1.8: Cross-sectional TEM of (b) EPI Silicon and (c) EPI Si1−xGex film

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technology. Both simulation and Raman measurement results are presented and discussed.

Chapter three presents the strain study of EPI Si1−xGex around silicon nanowires.

It is shown via Raman spectroscopy that EPI Si1−xGex relaxes majority of its

strain, displaying a fundamental difference compared with EPI Si1−xGexon big

silicon islands.

In chapter four, Convergent Beam Electron Diffraction(CBED) technique is used to determine the local strain in silicon nanowire. Correlated with finite element simulation, it is found that the silicon nanowire is strained.

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Chapter 2 Strain Engineering on SOI wafers

2.1 Strain study of Epitaxial Si

1−x

Ge

x

on SOI

wafers

2.1.1 Raman measurement for strain chacterization

The Raman microscope has become an invaluable analytical tool for semicon-ductors industry. It relies on inelastic scattering of monochromatic light from a laser in the visible, near infrared, or near ultraviolet range. The laser light inter-acts with phonons or other excitations in the sample, resulting in the energy of the laser photons being shifted up or down. The shift in energy gives information about the phonon modes in the system [23].

The optical phonon spectra of Si1−xGex is characterized by individual branches

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the Si-Si, the Si-Ge and the Ge-Ge nearest neighbor vibrations.

The Raman shifts of these phonon modes are affected by Germanium composi-tion and strain in Si1−xGex alloy. Two effects can explain the raman peak position

shift’s dependency as a result of varying Germanium composition. Firstly, alloy disorder effectively confines the Raman-active phonon modes. Secondly, charac-teristic bond lengths of Si-Si, Si-Ge and Ge-Ge in Si1−xGex alloys are different.

The bond stiffness changes correspondingly with characteristic bond length. Thus the shift of the Si-Si, Si-Ge and Ge-Ge modes in a relaxed Si1−xGex alloy relative

to the positions in pure Si is coming from two sources: [24]

∆ω1 = ∆ωmass+ ∆ωmicro (2.1)

This dependency has been studied extensively in literature. Data in Figure 2.1 shows that the Si-Si and Ge-Ge mode frequency of samples depends linearly on the Ge molar fraction.

Choppra [2] did a systemetical calibration between Si-Si Phonon and Ge mole fraction in Si1−xGex alloy which is verified by SIMS data. Table 2.1 summarizes

the Si-Si phonon peaks for relevant Ge mole fraction relaxed films. Since all the work in this dissertation is carried in the same UHV-RTCVD system, this set of peaks will be used as reference points.

Due to the lattice mismatch between Si1−xGex and Silicon,

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Table 2.1: Germanium content(x) in Si1−xGexlayers determined by Raman

Spec-troscopy and SIMS

Si-Si Peak(cm−1₎ _Ge(x)(Raman) _{Ge(x) (SIMS)}

487.5 0.478 0.452

502.5 0.284 0.278

509.3 0.176 0.175

this case is [24]

∆x= ∆ω1+ ∆ωmacro (2.2)

With known germanium concentrations in the film, Raman spectroscopy can be used to extract the strain distribution in the epitaxial films. This is the main application of Raman spectroscopy in this dissertation.

2.1.2 Raman Investigation for Silicon Epitaxial Si

1−x

Ge

x

on

SOI wafer

We used a bonded Silicon on Insulator (SOI) wafer supplied from SOITEC: SOI and Buried Oxide (BOX) thicknesses were 200 and 100 nm, respectively. The SOI thickness of the wafer was reduced to 50 nm by sacrificial oxidation and wet etching. x= 0.17 andx= 0.28 Si1−xGex films were grown at 550 ◦C.

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to focus the incident HeNe laser beam (λ=633nm) to a spot size of 1-2 um onto the sample. A filter was chosen to reduce the laser power that strikes the sam-ple. With a cooled charge coupled device (CCD) detector, the raman spectrum between 250cm−1 _{and 550} _cm−1 _{are studied. Si-Si phonon mode is chosen for}

further strain analysis because of the sensitivity on Ge concentration and good linearity,

Following Dietrich’s method [25], the residue strain can be calculated when a simple phenomenological model is solved for two limiting cases, the psudomor-phically strained layer, and the alloy-like stress-free layer.

For alloy-like stress-free films, the epitaxial Si1−xGexis modeled as silicon

under hydrostatic pressure. All the shear strains are assumed to be neglectible. Strains in three direction are assumed to be equal. The validity of Vegard’s law on phonon deformation potentials (PDPs) e.g. K11, K12 is assumed.

11=22=33=, =

a(Si1−xGex)−a(Si)

a(Si)

∆ωT O = (

ω0

6 )(K11+ 2K12)(211+) ∆ωT O = (

ω0

2 )(K11+ 2K12) (2.3)

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500 510 520 530 540 550 1000 2000 3000 4000 5000 Intensity(a.u. )

Wavenumber(cm-1)

Relaxed Si

0.72Ge0.28 films

80nm Si

0.72Ge0.28 films on 40nmSOI

30nm Si_0.72Ge_0.28 films on 40nmSOI

250nm Si_0.72Ge_0.28 films on 40nmSOI

Figure 2.2: Typical Raman spectrum for Si1−xGex films with different thickness.

<110>, only the singlet mode will be detected which can be described as:

11=226=33, σ11 =σ22, σ33= 0,

33=−(

2c12

c11

11)

∆ΩS = (

ω0

2 )(2K1211+K1133) (2.4) The residue strain in the EPI film can be extracted as:

11=

∆ωexp−∆ωsp

ω0(K12− C_C12₁₁K11)

(2.5)

Following the procedure described above, the residue strain in 28% Si1−xGex is

calculated and summarized in Figure 2.3.

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0 50 100 150 200 250 0.2

0.4 0.6 0.8 1.0 1.2

Residue Strain %

SiGe thickness (nm)

Residual Strain calculated from measured Raman Shift Residual Strain from simple compliant substrate theory

Figure 2.3: Comparison of residue strain in Si1−xGex films between experimental

data and simply compliant substrate theory. SOI body thickness is 30nm.

in lattice parameter is denoted by m. The common biaxial modulus is given by

M = 2µ(1 +ν)/(1−ν). The compatibility of deformation of layers and zero net force on any internal plane perpendicular to the interface require that [26],

f −m =s

M fhf +M shs= 0 (2.6)

The elastic strain in each layer prior to formation of dislocation can be solved from these two conditions as

f =m

hs

hs+hf

, s=−m

hf

hs+hf

(2.7)

It is clear from Figure 2.3 that the residue strain in Si1−xGex films is larger

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pure compliant substrate. It is relatively harder to transfer strain from epitaxial Si1−xGexfilm to SOI layer. For further comparison, we investigated the impact

of body thickness on the residual strain in the film. Even though the effect of body thickness from experimental data is consistent with the trend predicted by compliant substrate theory, the residue strain of epitaxial film on top of 40nm SOI is still two times larger than theory. This demonstrates that simple compliant substrate theory may underestimate the strain in epitaxial film and overestimate the strain in the substrate.

2.2 Strain study of Si

1−x

Ge

x

junction on SOI wafers

In recent years, Si1−xGex junction engineering has become a preferred method

for improving contact resistance and introducing uniaxial compressive strain in the channel which can enhance hole mobility. Intel has reported that Si1−xGex can

introduce several hundred Mega-Pascal of compressive stress in the channel region of PMOSFET resulting in a hole mobility enhancement of close to 50% in 90nm technology node [3]. Recently, the concept of recessed Si1−xGex Source/Drain

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30 32 34 36 38 40 0.5

0.6 0.7 0.8 0.9 1.0 1.1 1.2

Residue Strain in Epitaxial Film

SOI Body Thickness

Residual Strain calculated from measured Raman Shift Residual Strain from simple compliant substrate theory

Figure 2.4: Impact of body thickness on residue strain. The epitaxial SiGe thickness is 30nm

of Si1−xGexjunctions is a formidable task as the body thickness scales down.

UV Raman measurements were conducted to clarify the impact of recessing on channel strain. The possibility of using non-recessed junction is also explored in this work. The major processing steps for these test structures are shown in Figure 2.5.

1. Starting from a SOITEC SOI wafer, Photo Resist(PR) lines are defined using ASML 5500/950B system, which employs a 193 nm ArF Excimer laser.

2. Oxide is etched through using RIE withCHF3 and O2.

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4. PR and Bottom Anti-Reflection Coating(BARC) are removed. After RCA clean, 50% Si1−xGex films are grown on the wafer.

High resolution TEM image of 50% non-recessing epitaxial Si1−xGexon 40nm

SOI wafer is shown in Figure 2.6. Stacking faults were found in the junction region. However, no dislocation was observed in the channel region. The de-fects’s location of epitaxial Si1−xGex films on 40nm SOI is similar to epitaxial

Si1−xGexfilms on bulk wafers.

The different parameters for samples are summarized in Table 2.2.

Due to the low spectrum resolution of the CCD camera of the UV Raman tool, curve fitting is performed in Origin software to get the peak of the Si-Si phonon mode. Figure 2.7 and Figure 2.8 show the fitting curves for non-recessed junctions and recessed junctions respectively. Following the strain calculation described in the last section, the strain in Si1−xGex and silicon region are both

calculated. The results are summarized in Table 2.2. It is clearly seen that all the 50% Si1−xGex films are partially relaxed. The strain in epitaxial films and

the strain in channel region are positively correlated. When the epitaxial film is highly strained, the channel is also highly strained. However ideal compliant substrate theory predicts that the strain in epitaxial film and strain in substrate are negatively correlated. Borophosphosilicate glass(BPSG) is explored by other researchers to take advantages of compliant substrate. It is also observed that impact of recessing on strain in the channel is dominant. The Si1−xGex films on

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Table 2.2: Samples for UV Raman Study Sample Number SOI thick-ness (nm) Recessing (nm)

Si1−xGex

thick-ness (nm) Si-Si peak position (cm−1₎

Strain in

Si1−xGex

films (%)

Si-Si peak position (cm−1₎

Strain in Sil-icon (%)

N3 30 0 35 487.9 0 521.24 0.15

N5 50 0 35 491 0.38 521.72 0.21

R3 30 15 35 489.7 0.22 522.12 0.27

R4 40 15 35 493.2 0.67 523.42 0.41

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BARC PR 800A 2000A Si Bulk SiO2(2000A)

Si 500A 400A 300A SiO2300A 300A _300A

BARC PR 800A 2000A Si Bulk SiO2(2000A) Si 500A 400A SiO₂300 _300A

300A BARC PR 800A 2000A Si Bulk SiO2(2000A) Si 500A 400A SiO₂300 _300A

300A

Si Bulk SiO2(2000A) Si 500A 400A SiO₂300 _300A

300A

Si Bulk SiO2(2000A) Si 500A 400A SiO₂300 _300A

300A BARC PR 800A Si Bulk SiO2(2000A)

500A 400A 300A

300A _300A

300A

Figure 2.5: Major processing steps for channel strain measurements

consistent with Wei’s report [27].

2.3 Finite Element Simulation of Strain

Distri-bution

With the scaling of SOI CMOS devices, the Etch-and-EPI technique for uni-axial Si1−xGex strain scheme will encounter significant challenges due to ultra

thin body. Therefore, the possibility of introduction of strain from non-recessed elevated SiGe junctions needs to be explored.

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500 510 520 530 540 550 0 100 200 300 400 500 521.24392 520.30028 521.71573 Intensity(a.u.)

Wavenumber(cm-1)

Silicon N5 N3

Figure 2.7: UV raman data for channel region with non-recessed SiGe junctions

500 510 520 530 540

0 100 200 300 400 500 522.12062 523.42011 523.69368 Silicon R3 R4 R5 Intensity(a.u.)

Wavenumber(cm-1)

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difficult and devices will require non-recessed source/drain junctions. However, the impact of non-recessed SiGe junctions on ultra thin body (UTB) SOI is not known. The goal of this study is to explore the influence of non-recessed SiGe junctions on the strain profiles of UTB SOI channels since any strain introduction via this route could offer significant advantages for UTB SOI devices.

Using Synopsis-Sentaurus package, we investigated the impact of non-recessed SiGe and its various physical paramaters on the strain profile in the channel. The results indicate that significant amount of compressive strain in the channel region is available from non-recessed SiGe junction providing opportunities for high per-formance SOI devices. Due to the lack of dislocation modeling, the Si1−xGex films

in Synopsis-Sentaurus are always assumed to be almost fully strained. However, at the time of this work, Synopsis-Sentaurus did take free surfaces under consid-erations. This gives a more realistic strain profile in the device structures.

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Lg

Spacer

SiGe thickness

SOI thickness Source Length

Figure 2.9: Parameters for simulation study

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rectangle with a width equal to the gate length and a height of 20˚A taken from the oxide-silicon interface.

Even with non-recessed SiGe junctions, significant levels of strain were ob-tained in the Si channel. The dependence of the strain level on the Si body thickness was investigated. It was found that with non-recessed SiGe junctions, the average stress along the channel increases gradually when the body thickness decreases. Furthermore, as shown in Figure 2.10, the stress enhancement for thinner body thicknesses is more significant for higher Ge concentrations. This effect highlights one of the key differences between non-recessed junction and re-cessed junctions. For non-rere-cessed junctions, the stress only extends about 20nm in the silicon body. Therefore, when the body thickness is near 20nm, the stress distribution in the channel will be significantly influenced by changes in body thickness changes.

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0 10 20 30 40 50 4.0x108 6.0x108 8.0x108 1.0x109 1.2x109 1.4x109 1.6x109 1.8x109

Average Compressive Stress (Pascal)

SOI Body Thickness (nm)

Ge17 Ge28 Ge50

Figure 2.10: Average Stress in the Channel with Different Body Thickness. Si1−xGexis 10nm. Gate length is 14nm.

8 10 12 14 16 18 20 22 24

5x108 6x108 7x108 8x108 9x108 1x109 1x109 1x109 1x109 1x109 2x109 2x109 2x109 2x109

Physical Gate Length (nm)

Ge17 Ge28 Ge50 Bulk

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Figure 2.12 shows that with increasing raised source drain thickness, the av-erage compressive stress in the channel can be improved. However, this enhance-ment saturates quickly when raised Si1−xGexis increased from 10nm to 30nm.

For future generation of CMOS technologies, higher germanium concentration is expected to be used in the junction region. For Si1−xGex films with more than

30 percentage germanium, 30 nm is not too far away from critical thickness. Therefore, higher compressive strain can’t be achieved with more than 30nm Si1−xGexfilms.

The stress is also a function of length of source/drain region. When the length of source/drain regions increases, the Si1−xGex volume which contributes

to compressive strain in the channel increases. The average stress in the channel increases with this volume. But when the source/drain region become much larger than the gate length, stress enhancements will saturate too. For real device applications, the length of source and drain are not expected to be much larger than the separation between source and drain. From Figure 2.13, the device engineer can have the freedom to trade the performance with layout area.

In conclusion, uniaxial stress can be introduced into channel with non-recessed Si1−xGexjunctions. Combined with higher Germanium concentration, this

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8 10 12 14 16 18 20 22 24 4x108 5x108 6x108 7x108 8x108 9x108 1x109

Average Compressive Stress(Pascal)

Phyical Gate Length(nm)

SiGe10nm SiGe20nm SiGe30nm

Figure 2.12: Average Stress in the Channel with Different Raised Source Drain thickness.

1 2 3 4 5

2.0x108 4.0x108 6.0x108 8.0x108 1.0x109 1.2x109 1.4x109 1.6x109 1.8x109 2.0x109 2.2x109 2.4x109

Multiplier of distance between source and drain Gate Length=10nm

Gate Length=14nm Gate Length=23nm

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comparable performance improvements as Si1−xGex junctions [31]. Therefore, the

compatibility of non-recessed Si1−xGexjunction and compressive capping layer

should be studied concurrently.

2.4 Discussion

Si1−xGex epitaxial films on SOI wafers were studied using Raman Spectroscopy.

At 500-550◦C growth temperature, SOI wafers do not act as a compliant sub-strate. The rigid interface between SOI and oxide reduces the strain sharing between the Si1−xGexepitaxial film and the SOI layer substantially.

Small critical thickness of high Ge percentage Si1−xGex films in the S/D

re-gions of the SOI device limits the application of high Ge percentage Si1−xGex films.

For 50% Ge in Si1−xGex films on the SOI wafers, high density of dislocations and

stacking faults are formed in the epitaxial films, which is verified by HRTEM. From the design point of view, recessing is another important parameter for retaining strain in the channel region. In our research work, this was confirmed by the comparison of the Raman spectra of the recessed and the non-recessed samples. Condensation of Si1−xGexat the S/D regions was first proposed by

Yeo [32] to create embedded Si1−xGex S/D regions on thin body devices such as

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Chapter 3 Raman Spectrum study of

Epitaxial Si

₁

₋

_x

Ge

_x

on Silicon

Nanowire

Growing epitaxial films on nanostructures has a lot of interesting applications in semiconductor industry. Firstly, it provides a new way to grow high quality heterostructure films on substrate. There are efforts toward the reduction of dis-location density of epitaxial films that are grown on nanostructures. Vanamu [33] demonstrated low (105 cm−2) defect density in thick(10 µm) epitaxially grown Ge films on nanostructured silicon substrate. Compared with buffer layer tech-nique, the gradient of strain relaxation improved in these films . Liang [22] studied Si1−xGex films with Ge contents in the range of 25%-75% on silicon fin or

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smaller than that for bulk silicon substrate samples.

Secondly, strain relaxation process of epitaxial Si1−xGexon top of nanowire

is important for strain engineering for nanowire MOSFET. The strain partition between Si1−xGex film and silicon fin decides the barrier height and mobility

properties which are both vital for high speed CMOS applications.

Si1−xGex epitaxy films were grown on the silicon nanowires provided by

SE-MATECH. These nanowires were defined using lithography and dry etching tech-niques on SOITECH SOI wafers(60nm SOI and 150nm Buried Oxide). The width of nanowires are 20nm, 30nm and 40nm. The morphology of epitaxial Si1−xGexfilms are examined using TEM and SEM techniques. The strain of

epitaxial Si1−xGexfilms are measured using Raman spectroscope. Because of

the complexity of nonuniform strain in the films, the analytical solution is not available for this system. The measured Raman shifts are correlated with syn-thesized Raman spectrum which uses the strain simulated in Finite Element Analysis(FEA) software as inputs. It was found out that early start of strain relaxation of epitaxial film transfers strain into silicon nanowire which will be studied in more detail using TEM technique in the next chapter.

3.1 Epitaxial Si

1−x

Ge

x

on Silicon Nanowire

It is well known that without translational symmetry, facets are formed during silicon and Si1−xGexepitaxial process. During the silicon epitaxial on silicon (100)

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observed [34]. As pointed out by Li and coworkers [35] [36], both surface mass transport and surface free energy are important in modeling facet generation. From minimization of total surface energy point of view [37] [38], the following relationship is assumed,

EIso > E(001) > E(311)> E(111) (3.1)

where E(001),E(311) and E(111) are surface free energies of (001),(311),and (111)

planes.EIso is the interface free energy between the silicon epilayer and the

isola-tion material.The interface free energy is so high that Si epitaxial layer will avoid contacts with oxide. (111) plane is the most favorable besides the oxide sidewall for minimization of free energy. From surface mass transport point of view [39], the epitaxial growth is determined by two incident adatom flux(ISiO2 and J111)

and the outgoing flux (I111).When the incoming flux is equal to the outgoing flux,

silicon atoms are accumulated on the (111) surface.

I311 =ISiO2+J111 (3.2)

In another words,when the silicon adatom diffusion length is much less than the length of the (111) facet, mass accumulation tends to happen. At the growth temperature of 550◦C, the (111) facet was dominantly observed. It is reported in literature that the (113) facets increase when growth temperature is above 600◦C. While in this work, all the films are grown under 550◦C. Figure 3.1 shows a typical Si1−xGex epitaxial growth on silicon nanowire defined in bulk silicon

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Figure 3.1: 28% Facets of SiGe Epitaxial Growth around silicon nanowire

Selectivity of Si1−xGex degrades with in-situ boron doping. To improve

se-lectivity, HCl is usually mixed with other precursor. But there are two inherent problems with this scheme. Firstly, HCl tends to roughen the epitaxial surface. Secondly, the addition of HCl reduces the deposition rate substantially. Re-cently, Kiyota [40] proposed the use of dichlorosilane(SiH2Cl2) instead of HCl

which achieved good selectivity without causing an increase in surface rough-ness or degradation of the growth rate. However, in this dissertation, no spe-cial efforts are made to enhance selectivity. Table 3.1 summarizes the depo-sition conditions for Si1−xGex films. From now on, we will refer these

condi-tions as A, B and C. From experiments, it was found that for condition A, Si1−xGexfilm didn’t grow selectively on silicon with respect to silicon dioxide.

Figure3.2 clearly shows the Si1−xGex growth on top of oxide. Compared with

blank wafer, the growth rate of Si1−xGex films on silicon nanowires for

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Table 3.1: Process conditions for Si1−xGex epitaxy [2]

Condition A Condition B Condition C

Temperature(◦C) 550 550 500

Pressure(mTorr) 100 200 300

Si2H6(sccm) 25 15 10

GeH4(sccm) 30 45 75

H2(sccm) 270 400 675

Ge concentration for bulk films(%) 17 28 50

Growth Rate for bulk films(nm/min) 25 40 30

a blanket to a patterned substrate) [41]. The higher germanium concentration was also verified with EELS analysis. Germanium concentration also plays an important role in selectivity issues. With higher germanium concentration, the selectivity of Si1−xGexdeposition improves. As shown in Figure 3.3, there

is nearly no Si1−xGex deposition on oxide films. However, it is generally more

difficult to grow high quality epitaxy films with high germanium concentration. Figure 3.4 indicates, under condition C, the rough film surface provides a way to relax the build-in strain. Generally, reducing growth temperature for high germanium concentration deposition helps minimize the surface roughness. But even with 425◦C, smooth epitaxial Si1−xGex films can’t be obtained for condition

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Figure 3.2: Cross Sectional TEM image of one minute growth of 17% Si1−xGexepitaxial on Silicon Nanowire

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(a) (b)

(c) (d)

Figure 3.4: SEM image 17% Si1−xGex epitaxial growth on silicon nanowire were

shown in (a) and (b). SEM image 50% Si1−xGex epitaxial growth on silicon

nanowire were shown in (c) and (d).

3.2 Study of strain distribution of Si

₁₋_x

Ge

_x

epitaxial

on silicon nanowire

Anastassakis [42] published the first paper on the impact of uniaxial stress on the Raman spectrum of silicon. The new optical phonon frequencies ωk in the

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φ() =

K111+K12(2+3) K446 K445

K446 K112+K12(3+1) K444

K445 K444 K113+K12(1+2)

φ()υ(_k) = λkυ ()

k (3.3)

where (υ_k())i represents the ith component of the kth normalized eigenvector.

The difference between the new phonon frequency ωk and the phonon frequency

without strain ω0 is related to the eigenvalues of the secular equation by:

∆ωk=ωk−ω0 =

λ ωk−ω0

≈ λ

2ω0

(3.4)

K11,K12and K44are the phonon deformation potentials (PDP). For matrix

rep-resentation, the notation of stress and strain tensor follows Nye’s [18] convention.

       

σ11 σ12 σ13

σ21 σ22 σ23

σ31 σ23 σ33

        →        

σ1 σ6 σ5

σ6 σ2 σ4

σ5 σ4 σ3

               

11 12 13

21 22 23

31 23 33

        →        

1 1₂6 1₂5

1 26 2

1 24

1 25

1 24 3

        (3.5) Raman Spectroscopy has been employed extensively in the semiconductor in-dustry for because it is nondestructive and no sample preparation is needed. Wolf and coworkers [43] [44]studied the local strain measurements in Si3N4/poly-Si

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into account the effects of laser beam width, penetration depth, and focusing. This technique is further developed by Bonera [46]. Following this methodology, the strain in epitaxial Si1−xGexfilms is first simulated using a commercial

finite-element (FE) software package–ANSYS. The corresponding raman spectrum is synthesized by averaging the raman shift contribution from each finite element. Then the results are compared with experimental data.

3.2.1 Strain Field Simulation Using ANSYS

For the CMOS application, Si1−xGexepitaxial is well controlled such that

the film thickness is below critical thickness. In the region, elastic deformation dominates the strain partition between substrate and epitaxial film which can be simulated using the standard finite element analysis(FEA) software. ANSYS is a general purpose FEA modeling package for numerically solving a wide variety of mechanical problems. To get a better understanding of the strain distribution in this epitaxial Si1−xGexon silicon nanowire system, a full three dimensional

simulation is carried out which eliminates the errors brought by the usual plane strain assumption for two dimensional simulation. Element Solid186 was chosen for this study. It is defined by 8 nodes with three degrees of freedom at each node: translations in the nodal x, y and z directions.

For any FEA software, mesh definition is always at the center stage. To achieve accurate results, the density of mesh is increased at Silicon/Si1−xGexinterface

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reduce the computation time. Only one quarter of the structure is simulated in this study. The boundary conditions are such that the bottom of oxide has zero vertical displacement. The traction on the free surfaces is set to zero. Isotropic approximation was used in the calculation of stress and strain in the Si/SiGe structures. This reduced the complexity of computation substantially when com-pared with simulation using anisotropic material properties.

The lattice mismatch between SiGe and Si was described in the framework of thermoelasticity [47]. The strain due to lattice mismatch was simulated by ap-plying a uniform temperature change to the structure,

T hermal =α×∆T =Lattice (3.6)

α is the thermal expansion coefficient difference between the silicon and germa-nium. The material properties used in this study are summarized in Table3.2. Material properties for Si1−xGex films can be calculated from those of silicon and

germanium by linear interpolation.

Figure 3.5 shows the schematic for the 30% Si1−xGex films grown on silicon

Table 3.2: Ansys Setup From Yeo’s paper

Silicon Gemanium Oxide Lattice constant(˚A) 5.431 5.646

Ex 0.1629 0.1317 0.08

PRXY 0.28 0.273 0.17

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nanowires. The structure was constructed after the cross-sectional TEM images. Figure3.6, 3.7 and 3.8 are contour plots of elastic strain in x, y and z direc-tions. Conventionally, a positive sign means tensile strain and a negative sign means compressive strain. From these plots, it is apparent that the free end of Si1−xGexfilm bulges out because of the strain stored in the system. The

defor-mation is exaggerated in these figures for clarity. Intuitively, we would expect the Si1−xGex film is compressively strained along z and y directions, and tensilely

strained in the x direction which is consistent with these figures.

3.2.2 Raman spectrum synthesis from Finite Element stress

models

Because strain is not uniform throughout the structure, spectra originating from each finite element is different from each other. The elastic strain simu-lated using ANSYS was input into a MATLAB program to synthesize the strain introduced raman shift by averaging the contribution from each finite element. In this MATLAB program, each finite element’s contribution is resolved using the secular equation 3.3. There are three optical phonon branches for each finite element. The intensity of the scattered radiation for ideal backscattering follows the selection rule. The intensity for each mode k is given by:

Ik∝ |eTi R ()

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Figure 3.5: Schematic of nanowire structure

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Figure 3.7: Elastic strain in Y direction of 30% Si1−xGex

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where ei and es denote the polarization of incident and scattered radiation. R () k

is the raman tensor with the presence of strain, which is related to the raman tensor without strain in the following way.

R(_k) =

3

X

i=1

Ri(υ ()

k )i k = [1−3] (3.8)

where (υ_k())i represents theith component of thekth normalized eigenvector. In

the absence of stress, the Raman tensors describing the three optical modes of silicon are given by [48]:

R1 =

       

0 0 0 0 0 d 0 d 0

       

R2 =

       

0 0 d 0 0 0 d 0 0

       

R3 =

       

0 d 0 d 0 0 0 0 0

        (3.9)

Experimental factors such as attenuation of a laser beam in the semiconduc-tors, and the width of the laser spot on the sample have to be considered for spectrum synthesis process. Generally, the intensity of laser is assumed to decay exponentially in the sample. And the dependence of the intensity on in plane coordinate assumes a Gaussian shape.

Il(y) = exp(−2αy) (3.10)

Il(x, x0) = exp(−2

(x−x0)2

B2 ) (3.11)

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frequency shift is then integrated across the cross section of the nanowire.

I(∆ω, x) =

Z ∞

0

Il(y)dy

(∆ω−∆_Aωp(x,y))2_{+ 1} (3.12)

I(∆ω, x0) =

Z ∞

−∞

I(∆ω, x)Il(x, x0)dx (3.13)

∆ω=I1∆ω1 +I2∆ω2+I3∆ω3 (3.14)

The maxium of I(∆ω, x0) vs ∆ωplot is the expected observed Raman shift.

Fig-ure 3.9 (b) shows a typical synthesized raman shift spectrum for 30% Si1−xGex epitaxial

film around Silicon Nanowire.

3.2.3 Comparison between Synthesized and Experimental

Raman Spectrum

Figure 3.9 (d) shows a typical Raman measurement of 30% Si1−xGex epitaxial

film around Silicon Nanowire. The peak positions of Si-Si shift of the synthesized and experimental Raman data are compiled in Table 3.3.

An important message coming out of this dissertation is the early start of strain relaxation for epitaxial Si1−xGexfilms on nano structures. This work is

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epitaxial growth of Si1−xGex on patterned nanowire is studied in this dissertation.

Four kinds of different epitaxial/substrate combinations are considered:

• I: Epitaxy of Si1−xGex on 20nm silicon nanowire (Condition A)

• II:Epitaxy of Si1−xGex on 40nm silicon square (Condition A)

• III:Epitaxy of Si1−xGex on 20nm silicon nanowire (Condition B)

• IV:Epitaxy of Si1−xGex on 40nm silicon square (Condition B)

Condition A and Condition B are deposition setups discussed in the previous section. It is clearly seen from Figure 3.9 that the Si-Si shift of epitaxial film on 40nm silicon nanowire is at the right of the Si-Si shift of epitaxial film on 20nm silicon nanowire for both deposition conditions A and B. From strain energy partition point of view, it’s easier to transfer strain to small volume substrate. However, the Si-Si phonon peak for both cases are very close to relaxed Si-Si peak which means the average strain energy of epitaxial film grown on nanowire is small. Compared to the epitaxial growth on a bulk substrate, larger free sur-face area for epitaxial Si1−xGex films on nanowires provides an effective way to

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The work discussed has been concentrated on epitaxial film. In the next section, the strain in silicon nanowires for ITRS projected devices are studied using the simulation tool Ansys.

3.2.4 Elastic Strain Simulation for nanowire MOSFET

To test whether epitaxial Si1−xGex junctions can introduce compressive strain

in the channel, an elastic strain simulation using Ansys was conducted. Accord-ing to ITRS2006, a multigate device will be introduced after 2011. The relevant parameters for this device are summarized in Table 3.4. In this simulation, phys-ical gate length, silicon body thickness and spacer thickness are 15nm,10nm and 7.5nm repectively. The shape of Si1−xGexwas set according to figure 3.3. The

length of Si1−xGex region was assumed three times longer than channel region.

The Si1−xGex epitaxial film was grown before spacer formation which means the

two junctions were only 15nm away from each other. The germanium concentra-tion is set to 30% in this study.

For [001] wafer, the piezoresistance along the channel direction is the larger compared with other perpenticular directions. Consequently, only elastic strain in

Table 3.3: Comparison between synthesized spectrum and experimental results

I II III IV

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Table 3.4: Parameters for future multigate CMOS technology

Years 2011 2012 2013

MPU Physical Gate(nm) Length 16 14 13 Si thickness for multi-gate(nm) 10.3 9 8.4 Spacer thickness(nm) 8.8 7.7 7.2

the channel is plotted in Figure 3.10. The silicon region under Si1−xGex is tensile

strained. Due to incompressity of the solid, the silicon channel is compressively strained. Without the recessing, the compressive strain in the channel is on an average 0.002%. This indicates the difficulty in introducing compressive strain in silicon channel with Si1−xGexjunctions without recessing. But as devices scale

down further, these epitaxial Si1−xGex junctions can provide enough compressive

strain( 0.005%) without recessing which is shown in figure 3.11.

3.3 Discussion

The strain relaxation of epitaxial Si1−xGex at free surfaces is clearly shown

in this study. This might be detrimental for strain engineering in a nanowire MOSFET. Therefore, smart designs must be carried out to constrain the free surfaces.

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that with the introduction of near-field Raman Spectroscopy, obtaining high spa-tial resolution ( 100 nm) will be possible.

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−100 −8 −6 −4 −2 0 2 4 6 8 10 50 100 150 200 250 Wavenumber Shift Intensity(a.u.)

Synthesized Raman spectrum for 20% SiGe on nanowires

−100 −8 −6 −4 −2 0 2 4 6 8 10

5 10 15 20 25 Wavenumber Shift Intensity(a.u.)

Synthesized Raman spectrum for 30% SiGe on nanowires

(a) (b)

500 502 504 506 508 510 512 514 516 518 520 0 10000 20000 30000 40000 Intensity(a.u.) Wavenumber(cm-1 )

60s Condition A Epitaxial on 20nm NW 60s Condition A Epitaxial on 40nm NW

492 496 500 504 508 512 0 4000 8000 12000 16000 20000 24000 Intensity(a.u.) Wavenumber(cm-1 )

60s Condition B Epitaxy on 20nm Silicon NW 60s Condition B Epitaxy on 40nm Silicon NW

(c) (d)

Figure 3.9: Comparison between Si-Si Phonon of Synthesized and measured Ra-man Spectrum for Si1−xGex epitaxial film around Silicon Nanowire (a)

synthe-sized Raman shift from relaxation position of Si-Si phonon for 60s deposition A on Si1−xGexfilms (b) synthesized Raman shift from relaxation position of Si-Si

phonon for 60s deposition B on Si1−xGex films (c) measured Raman shift from

relaxation position of Si-Si phonon for 60s deposition A on Si1−xGex films (d)

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(a) (b)

Figure 3.10: Elastic Strain Simulation for nanowire MOSFET with 15nm gate length and 30% Si1−xGex junction. The contour legend in (a) shows both tensile

and compressive strain. (b) is a replot of (a) with only compressive strain legend.

(a) (b)

Figure 3.11: Elastic Strain Simulation for nanowire MOSFET with 7.5nm gate length and 30% Si1−xGex junction The contour legend in (a) shows both tensile

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Chapter 4 TEM study of Epitaxial

Si

₁

₋

_x

Ge

_x

on Silicon Nanowire

The strain in Si1−xGexgrown on silicon nanowires was studied with Raman

spectroscopy in chapter three. The large spot size (1µm) of the laser only gives an average strain value in the epitaxial Si1−xGex film. It was found out that the

strain in silicon nanowire could not be probed with Raman spectroscopy. This chapter describes the study of the local strain distribution in silicon nanowire which was carried out using transmission electron microscopy (TEM) Convergent Beam Electron Diffraction (CBED) technique.

Study of Si1-xGex Junction Formation for SOI Based CMOS Technology

Dedication

Biography

Acknowledgements

Contents

List of Tables

List of Figures

Chapter 1

Introduction

1.1

Strain Engineering’s impact on MOSFETs

1.1.1

Biaxial Strain Engineering

1.1.2

Uniaxial Strain Engineering

1.1.3

Pizeoresistance Model

1.2

Epitaxial SiGe Growth

1.2.1

UHVCVD system

1.2.2

Epitaxial SiGe on Compliant Substrates

1.3

Thesis Overview

Chapter 2

Strain Engineering on SOI wafers

2.1

Strain study of Epitaxial Si

Ge

on SOI

wafers

2.1.1

Raman measurement for strain chacterization

2.1.2

Raman Investigation for Silicon Epitaxial Si

Ge

on

SOI wafer

2.2

Strain study of Si

Ge

junction on SOI wafers

2.3

Finite Element Simulation of Strain

Distri-bution

2.4

Discussion

Chapter 3

Raman Spectrum study of

Epitaxial Si

1

−

x

Ge

x

on Silicon

Nanowire

3.1

Epitaxial Si

Ge

on Silicon Nanowire

3.2

Study of strain distribution of Si

Ge

epitaxial

on silicon nanowire

3.2.1

Strain Field Simulation Using ANSYS

3.2.2

Raman spectrum synthesis from Finite Element stress

models

3.2.3

Comparison between Synthesized and Experimental

Raman Spectrum

3.2.4

Elastic Strain Simulation for nanowire MOSFET

3.3

Discussion

Chapter 4

₁

₋

_x

_x

₁

₋

_x

_x