The Timepix3 readout chip for hybrid pixel detectors: design and first measurements

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The Timepix3 readout chip for hybrid pixel detectors: design and first

measurements

Presented at FEE 2014, Argonne National Laboratory, May 20

^th

Massimiliano De Gaspari

CERN, European Organization for Nuclear Research Geneva, Switzerland

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Outline

• Introduction to Timepix3

• Front-end architecture

• Tests on bare chips

• Measurements with sensor

• Summary

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Timepix  Timepix3

Timepix Timepix3

Year 2006 2013

# pixels 256 x 256

Pixel size 55 x 55 mm

Technology CMOS 250nm CMOS 130nm

Measurement modes - Time-Over-Threshold (TOT) - Time Of Arrival (TOA)

- Event counting (PC)

- Simultaneous 10bit TOT and 18bitTOA - 18bit TOA only

- 10bit PC and 14bit integral TOT (itot) Readout type Sequential (frame-based) - Frame-based

- Data Driven (zero suppressed)

Dead time >300ms full frame readout > 375ns packet transfer, maximum hit rate 40Mhits/s/cm²

Time resolution 10ns 1.56ns

TOT monotonicity (h⁺) No Yes

Power pulsing No Yes

Minimum threshold ~750e^- >500e^-

Timepix3 is a joint design effort by CERN, NIKHEF and the University of Bonn

Main applications are:

- Fast readout of solid-state pixelated sensors - Readout of gaseous detectors (TPC)

- Vertex Locator for LHCb (future VELOpix) - Power pulsing tests for the Linear Collider - Dosimetry

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Timepix3

14100 µm

16210 µm Sensitive Area (14080 µm)

Active Periphery (1260 µm)

55 µm

128 double columns:

2x256 pixels (64 SuperPixels) each

SuperPixel: 2 x 4 pixels 1 per SuperPixel:

VCO@640MHz for the fast TOA

Analog Front-End 13 x 55 mm² Input pad on top of the digital area

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Fast ToA measurement

40MHz global clock always running (14bit ToA)

One 640MHz Voltage-Controlled Oscillator per SuperPixel (2x4 pixels) activated only when a discriminator fires (4bit fast ToA)

14bit ToA registered

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Pixel/SuperPixel diagram

Global threshold (LSB= ~10e^-)

Front-end (Analog)

Leakage Current compensation

Preamp

Input pad

1 pixel

TpA TpB

TestBit MaskBit

4-bit Local Threshold

~50mV/ke^- 3fF

3fF

T. Poikela

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Pixel/SuperPixel diagram

Front-end (Analog)

Preamp

Input pad

1 pixel

VCO

@640MHz

Super pixel (Digital)

Control voltage

Common for 8 pixels

640MHz

TpA TpB

Front-end (Digital)

Counters

&

Latches

clock (40MHz)

Time stamp

14-bits

Synchronizer

&

Clock gating

OP Mode

~50mV/ke^-

TOA (14-bit) TOT (10-bit) FTOA (4-bit) TOA & TOT

TOA (14-bit) FTOA (4-bit)

TOA

iTOT (14-bit) PC (10-bit) PC & iTOT

3fF

T. Poikela

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Pixel/SuperPixel diagram

Front-end (Analog)

Preamp

Input pad

1 pixel

VCO

@640MHz

Super pixel (Digital)

Control voltage

Common for 8 pixels

640MHz

TpA TpB

Front-end (Digital)

Counters

&

Latches

clock (40MHz)

Time stamp

14-bits

Synchronizer

&

Clock gating

OP Mode

~50mV/ke^-

TOA (14-bit) TOT (10-bit) FTOA (4-bit) TOA & TOT

TOA (14-bit) FTOA (4-bit)

TOA

iTOT (14-bit) PC (10-bit) PC & iTOT

3fF

Deserializer [1x31]

Super pixel FIFO [2x31]

Data out to EOC

37-bits

clock (40MHz)

Token arbitration

31-bits handshake

T. Poikela

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Outline

• Introduction to Timepix3

• Front-end architecture

• Tests on bare chips

• Measurements with sensor

• Summary

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Front-end specifications

Parameter Value Notes

Area 55mmx13.5mm

Signal polarity Positive and negative

Detector capacitance ~50fF 25fF to 100fF

Leakage current -5nA to +20nA

Amplitude linearity Not required Time measurement TOT monotonicity Yes, up to 300kh⁺

ToA jitter and mismatch Compatible with

1.56ns resolution Gas detector applications Time-to-peak Target 25ns In view of VELOpix

Noise +

threshold mismatch ~90e^- for a minimum threshold ~500e^- Equalization DACs 4bit Compensate pixel-to-pixel

threshold mismatch Power consumption 12mW/pixel

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Front-end architecture

Polarity switches PMOS diodes (TOT linearity)

Preamplifier + Discriminator OTA + Discriminator

Krummenacher feedback Equalization DAC 1^st stage 2^nd stage (constant total current)

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Timepix/Timepix3: preamplifier

Triple well

Timepix Timepix3 Notes

Preamplifier Differential Single-ended More efficient power usage

C_fb 8fF 3fF Larger gain

Input pad size

& positioning

20x20mm, over analog domain

12x12mm, over digital domain

Minimize parasitics, shielding to

analog ground

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TOT monotonicity

TOT monotonicity issue for large positive input charges:

Q_in>100kh⁺  V(In)>V(NodeX)  current through the wrong path

Added diode-connected PMOS transistors  good current path

In Out

NodeX

In Out

NodeX

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TOT monotonicity

0 2 4 6 8 10 12 14 16 18 20

-1000 -800 -600 -400 -200 0 200 400 600 800 1000

TOT ms

Q_in ke^-

TOT

TOT no diodes

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Outline

• Introduction to Timepix3

• Front-end architecture

• Tests on bare chips (using test pulses)

• Measurements with sensor

• Summary

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Test setup

SPIDR: Speedy PIxel Detector Readout

Developed for Timepix3 (from single chips up to quads) 1 x 10Gbps Ethernet link IO

Credits:

Bas van der Heijden, Frans Schreuder, Henk Boterenbrood (NIKHEF) Timepix3 Chip on

SPIDR board

VC707

Evaluation Board 10 Gbit

Ethernet

Virtex 7 FPGA

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S-curves

0 100 200 300 400 500

-25 0 25 50 75 100 125 150 175 200 225 250

Couunts

Threshold DAC [LSB]

Noise Floor TP=988e- TP=1542e- TP=2004e-

250 test pulses injected and counted in Photon Counting mode ENC extracted from the S-width: 5.7LSB = 64e^- rms

250 counts plateau

X. Llopart

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Timewalk and TOT linearity

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0 10 20 30 40 50 60 70 80

0 2.5 5 7.5 10 12.5 15 17.5 20

[µs]

time [n s]

[ke-]

TOA TOT

TOT (Linear fit) Threshold 500e^-

TOT slope ~75ns/ke^-

Timewalk

10ns@1500e^- TOA jitter

<0.5ns@5.5ke^- TOA<25ns@800e^-

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Outline

• Introduction to Timepix3

• Front-end architecture

• Tests on bare chips

• Measurements with sensor:

300mm Silicon P-on-N available since last week

• Summary

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Fluorescence measurements (65k pixels)

Noise hits start at 2keV=550e^-

FWHM  energy resolution s=124e^- (Cu) Equalization using noise floor

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Gain calibration using fluorescence (65k pixels)

40.5eV/LSB = 11.2e^-/LSB = 44.6mV/ke^- E. Fröjdh

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Noise map before/after bonding

Same chip measured at wafer level and after sensor bonding:

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Noise distribution

Average noise over the full matrix stays the same. Its distribution widens a little bit.

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17 14 15 14

2 7 10 11 12 12 13 17 11 15 10 15 9 11 9 11 12 10 11 10 5

6 6 7 12

9 9 13 12 9 10 17 8

40 45 50 55 60 65 70 75

2 4 6 8 10 12 14 16

ToT

1 1 1 1 44 7

5 5 4 4 4 4 4 4 5 5 12 8 13 12 13 13 12 13 16 19 21 18 16 16 19 18 18 23 23 24 29

40 45 50 55 60 65 70 75

5 10 15 20 25 30 35 40

Time (ns)

MIP (cosmic)

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Alpha particle

1 1 1

1 2 2 2 2 2 2

1 3 3 4 5 4 3 2 2

2 3 6 16 32 23 9 4 2 1

2 5 17 71 213 123 31 8 3 2

1 3 6 40 225 305 331 83 13 4 2

1 3 5 29 169 360 316 70 12 3 2

2 4 12 41 86 73 25 7 3 2

2 3 4 10 14 13 7 3 3

2 2 3 4 3 3 2 1

1 2 2 2 1

224 226 228 230 232 234 236 0

2 4 6 8 10 12

0 50 100 150 200 250 300 350

Tot

20 19 20

20 11 12 6 9 8 14

20 11 9 5 5 5 5 9 15

11 8 5 1 1 3 3 6 12 19

9 5 5 1 1 3 3 5 8 14

23 8 5 5 3 1 3 5 5 6 14

20 8 5 5 1 3 3 3 5 5 14

11 5 5 5 5 3 5 6 9 17

11 8 6 6 5 3 5 6 11

11 8 8 6 6 9 11 20

20 14 11 11 19

224 226 228 230 232 234 236 0

2 4 6 8 10 12

0 2 4 6 8 10 12 14 16 18 20 22

Time (ns)

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Outline

• Introduction to Timepix3

• Front-end architecture

• Tests on bare chips

• Measurements with sensor

• Summary

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Summary

• Timepix3 designed and fabricated in 2013

• Tests on bare chips and on wafers give good results

• First measurements with 300mm Silicon sensors look promising

Bare chip With 300mm Silicon sensor

Noise 55±2.9 e^- rms 55±3.4 e^- rms

Threshold mismatch (equalized) 35e^- rms 35e^- rms

Minimum threshold 500e^- 550e^-

TOT mismatch 6.5% rms

Timewalk (1ke^- above threshold) 10ns

TOA < 25ns Charge > 0.8ke^- TOA jitter < 0.5ns Charge > 5.5ke^-

Energy resolution 124e^- (Cu)

with equalization on noise floor

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Thanks for your time and attention!

• Timepix3 designed and fabricated in 2013

• Tests on bare chips and on wafers give good results

• First measurements with 300mm Silicon sensors look promising

Massimiliano De Gaspari for the CERN Medipix team (J Alozy, R Ballabriga, M Campbell, E Fröjdh, J Idarraga, S Kulis, X Llopart, T Poikela, P Valerio, W Wong), in collaboration

Bare chip With 300mm Silicon sensor

Noise 55±2.9 e^- rms 55±3.4 e^- rms

Threshold mismatch (equalized) 35e^- rms 35e^- rms

Minimum threshold 500e^- 550e^-

TOT mismatch 6.5% rms

Timewalk (1ke^- above threshold) 10ns

TOA < 25ns Charge > 0.8ke^- TOA jitter < 0.5ns Charge > 5.5ke^-

Energy resolution 124e^- (Cu)

with equalization on noise floor

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Thanks for your time and attention!

References:

- M. De Gaspari et al.

“Design of the analog front-end for the Timepix3 and Smallpix hybrid pixel detectors in 130 nm CMOS technology,” 2014 JINST 9 C01037

- T. Poikela et al.

“Digital column readout architectures for hybrid pixel detector readout chips,”

2014 JINST 9 C01007 - Y. Fu et al.

“The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC,” 2014 JINST 9 C01052

Massimiliano De Gaspari for the CERN Medipix team (J Alozy, R Ballabriga, M Campbell, E Fröjdh, J Idarraga, S Kulis, X Llopart, T Poikela, P Valerio, W Wong), in collaboration with NIKHEF and the University of Bonn.

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Outline

• Back up slides

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Timepix3 floorplan

14.1mm 2.1mm

14.1mm

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Readout modes

Data-driven readout mode.

Sequential frame-based mode.

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Threshold equalization

0 1000 2000 3000 4000 5000 6000 7000 8000 9000

-1500 -1250 -1000 -750 -500 -250 0 250 500 750 1000 1250 1500

Counts

[e-]

µ₀ = -762e^- σ₀ = 195e^-

µ_F = 762e^- σ_F = 197e^- µ_eq = 0e^-

σ_eq = 35e^-

Pixel DAC = 0x0 Pixel DAC = 0xF

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Threshold equalization

0 1000 2000 3000 4000 5000 6000 7000 8000 9000

-1500 -1250 -1000 -750 -500 -250 0 250 500 750 1000 1250 1500

Counts

[e-]

1 256

256

1

X (column number) Y

-1500 -750 0 750 1500

µ₀ = -762e^- σ₀ = 195e^-

1 256

256

1

X (column number) Y

-1500 -750 0 750 1500

µ_F = 762e^- σ_F = 197e^-

1 256

256

1

X (column number) Y

-1500 -750 0 750 1500

µ_eq = 0e^- σ_eq = 35e^-

Pixel DAC = 0x0 Pixel DAC = 0xF

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