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Siemens Simatic S 7 300 - 400 -Function Block Diagram for S7-300 and S7-400

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(1)Preface, Contents Product Overview. 1. Configuration and Elements of Function Block Diagram. 2. Addressing. 3. Bit Logic Instructions. 4. Timer Instructions. 5. Counter Instructions. 6. Integer Math Instructions. 7. Floating-Point Math Instructions. 8. This reference manual is part of the documentation package with the order number:. Comparison Instructions. 9. 6ES7810-4CA04-8BR0. Move and Conversion Instructions. 10. Word Logic Instructions. 11. Shift and Rotate Instructions. 12. Data Block Instructions. 13. Jump Instructions. 14. Status Bit Instructions. 15. Program Control Instructions. 16. SIMATIC S7 Function Block Diagram (FBD) for S7-300 and S7-400 Programming Reference Manual. 10/98 C79000-G7076-C566 Release 01. Appendix Glossary, Index.

(2) Safety Guidelines. !. !. !. This manual contains notices which you should observe to ensure your own personal safety, as well as to protect the product and connected equipment. These notices are highlighted in the manual by a warning triangle and are marked as follows according to the level of danger:. Danger indicates that death, severe personal injury or substantial property damage will result if proper precautions are not taken.. Warning indicates that death, severe personal injury or substantial property damage can result if proper precautions are not taken.. Caution indicates that minor personal injury or property damage can result if proper precautions are not taken.. Note draws your attention to particularly important information on the product, handling the product, or to a particular part of the documentation.. Correct Usage. !. Trademarks. Note the following:. Warning This device and its components may only be used for the applications described in the catalog or the technical description, and only in connection with devices or components from other manufacturers which have been approved or recommended by Siemens.. SIMATIC, AG.. SIMATIC HMI. and. SIMATIC NET are registered trademarks of SIEMENS. Third parties using for their own purposes any other names in this document which refer to trademarks might infringe upon the rights of the trademark owners.. Copyright  Siemens AG 1998 All rights reserved.    

(3)    . The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved.. We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed.. Siemens AG Bereich Automatisierungs- und Antriebstechnik Geschaeftsgebiet Industrie-Automatisierungssysteme Postfach 4848, D-90327 Nuernberg.  Siemens AG 1998 Technical data subject to change.. Siemens Aktiengesellschaft. C79000-G7076-C566. Function Block Diagram (FBD) for S7-300 and S7-400.

(4) Preface. Purpose of the Manual. This manual is your guide to creating user programs in the Function Block Diagram (FBD) programming language. This manual also includes a reference section that describes the syntax and functions of the language elements of Function Block Diagram.. Audience. The manual is intended for S7 programmers, operators, and maintenance/service personnel. A working knowledge of automation procedures is essential.. Where is this Manual Valid?. This manual is valid for release 5.0 of the STEP 7 programming software package.. Which Standards Does the Software Comply With?. FBD corresponds to the “Function Block Diagram” language defined in the International Electrotechnical Commission’s standard IEC 1131-3. For further details, refer to the table of standards in the STEP 7 file NORM_TBL.WRI.. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. iii.

(5) Preface. Requirements. To use this Function Block Diagram manual effectively, you should already be familiar with the theory behind S7 programs which is documented in the online help for STEP 7. The language packages also use the STEP 7 standard software, so you should be familiar with handling this software and have read the accompanying documentation.. Documentation. Purpose. STEP 7 Basic Information with.   . Basic information for technical Working with STEP 7 V5.0, Getting Started personnel describing the methods of implementing control tasks with Manual STEP 7 and the S7-300/400 Programming with STEP 7 V5.0 programmable controllers. Configuring Hardware and Communication Connections, STEP 7 V5.0. Order Number 6ES7810-4CA04-8BA0.  From S5 to S7, Converter Manual STEP 7 Reference with.  Ladder Logic (LAD)/Function Block Diagram (FBD)/Statement List (STL) for S7-300/400 manuals.  Standard and System Functions for S7-300/400. Online Helps. Provides reference information and describes the programming languages LAD, FBD and STL and standard and system functions extending the scope of the STEP 7 basic information.. Purpose. 6ES7810-4CA04-8BA0. Order Number. Help on STEP 7. Basic information on programming and configuring hardware with STEP 7 in the form of an online help.. Part of the STEP 7 Standard software.. Reference helps on STL/LAD/FBD. Context-sensitive reference information.. Part of the STEP 7 Standard software.. Reference help on SFBs/SFCs Reference help on Organization Blocks. Accessing the Online Help. You can display the online help in the following ways:.  Context-sensitive help about the selected object with the menu command Help > Context-Sensitive Help, with the F1 function key, or by clicking the question mark symbol in the toolbar..  Help on STEP 7 via the menu command Help > Contents. References. iv. References to other documentation are indicated by reference numbers in slashes /.../. Using these numbers, you can check the exact title in the References section at the end of the manual.. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(6) Preface. SIMATIC Customer Support Online Services. The SIMATIC Customer Support team offers you substantial additional information about SIMATIC products via its online services:.  General current information can be obtained: – on the Internet under http://www.ad.siemens.de/simatic/html_00/simatic – via the Fax-Polling number 08765-93 02 77 95 00.  Current product information leaflets and downloads which you may find useful are available: – on the Internet under http://www.ad.siemens.de/support/html_00/ – via the Bulletin Board System (BBS) in Nuremberg (SIMATIC Customer Support Mailbox) under the number +49 (911) 895-7100. To dial the mailbox, use a modem with up to V.34 (28.8 Kbps) with the following parameter settings: 8, N, 1, ANSI; or dial via ISDN (x.75, 64 Kbps).. Additional Assistance. If you have other questions, please contact the Siemens representative in your area. The addresses are listed, for example, in catalogs and in Compuserve (go autforum). Our SIMATIC Basic Hotline is also ready to help:.  in Nuremberg, Germany – Monday to Friday 07:00 to 17:00 (local time): telephone: +49 (911) 895–7000 – or E-mail: simatic.support@nbgm.siemens.de.  in Johnson City (TN), USA – Monday to Friday 08:00 to 17:00 (local time): telephone: +1 423 461–2522 – or E-mail: simatic.hotline@sea.siemens.com.  in Singapore – Monday to Friday 08:30 to 17:30 (local time): telephone: +65 740–7000 – or E-mail: simatic@singet.com.sg The SIMATIC Premium Hotline is available round the clock worldwide with the SIMATIC card (telephone: +49 (911) 895-7777).. Courses for SIMATIC Products. Siemens offers a number of training courses to introduce you to the SIMATIC S7 automation system. Please contact your regional training center or the central training center in Nuremberg, Germany for details: Telephone: +49 (911) 895-3154.. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. v.

(7) Preface. Questionnaires on the Manual and Online Help. vi. To help us to provide the best possible documentation for you and future STEP 7 users, we need your support. If you have any comments or suggestions relating to this manual or the online help, please complete the questionnaire at the end of the manual and send it to the address shown. Please include your own personal rating of the documentation.. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(8) Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. iii. 1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1. 2. Configuration and Elements of Function Block Diagram . . . . . . . . . . . . . . . . . . .. 2-1. 2.1. Elements and Box Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2. 2.2. Boolean Logic and Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6. 2.3. Significance of the CPU Registers in Statements . . . . . . . . . . . . . . . . . . . .. 2-9. Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1. 3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2. 3.2. Types of Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-4. Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1. 4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2. 4.2. AND Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3. 4.3. OR Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4. 4.4. AND-before-OR Logic Operation and OR-before-AND Logic Operation .. 4-5. 4.5. Exclusive OR Logic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-6. 4.6. Insert Binary Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-7. 4.7. Negate Binary Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-8. 4.8. Assign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-9. 4.9. Midline Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-10. 4.10. Save RLO to BR Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-11. 4.11. Set Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-12. 4.12. Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13. 4.13. Set Counter Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-14. 4.14. Up Counter Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-16. 4.15. Down Counter Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-17. 4.16. Pulse Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-18. 4.17. Extended Pulse Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-20. 3. 4. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. vii.

(9) Contents. 5. 6. 7. viii. 4.18. On-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-22. 4.19. Retentive On-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-24. 4.20. Off-Delay Timer Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-26. 4.21. Positive RLO Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-28. 4.22. Negative RLO Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-29. 4.23. Address Positive Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-30. 4.24. Address Negative Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-31. 4.25. Set_Reset Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-32. 4.26. Reset_Set Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-33. Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1. 5.1. Memory Areas and Components of a Timer . . . . . . . . . . . . . . . . . . . . . . . . .. 5-2. 5.2. Choosing the Right Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4. 5.3. Pulse S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-5. 5.4. Extended Pulse S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-7. 5.5. On-Delay S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-9. 5.6. Retentive On-Delay S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-11. 5.7. Off-Delay S5 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-13. Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1. 6.1. Memory Address and Components of a Counter . . . . . . . . . . . . . . . . . . . . .. 6-2. 6.2. Up-Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3. 6.3. Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-5. 6.4. Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-7. Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-1. 7.1. Add Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-2. 7.2. Add Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-3. 7.3. Subtract Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-4. 7.4. Subtract Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-5. 7.5. Multiply Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-6. 7.6. Multiply Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-7. 7.7. Divide Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-8. 7.8. Divide Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-9. 7.9. Return Fraction Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-10. 7.10. Evaluating the Bits of the Status Word with Integer Math Instructions . . .. 7-11. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(10) Contents. 8. 9. 10. Floating-Point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-1. 8.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-2. 8.2. Add Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-3. 8.3. Subtract Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-4. 8.4. Multiply Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-5. 8.5. Divide Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-6. 8.6. Evaluating the Bits of the Status Word with Floating-Point Instructions . .. 8-7. 8.7. Forming the Absolute Value of a Floating-Point Number . . . . . . . . . . . . . .. 8-8. 8.8. Forming the Square (SQR) of a Floating-Point Number . . . . . . . . . . . . . . .. 8-9. 8.9. Forming the Square Root (SQRT) of a Floating-Point Number . . . . . . . . .. 8-10. 8.10. Forming the Natural Logarithm of a Floating-Point Number . . . . . . . . . . . .. 8-11. 8.11. Forming the Exponential Value of a Floating-Point Number . . . . . . . . . . . .. 8-12. 8.12. Forming Trigonometric Functions of Angles as Floating-Point Numbers .. 8-13. Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-1. 9.1. Compare Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-2. 9.2. Compare Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-3. 9.3. Compare Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-4. Move and Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-1. 10.1. Assign Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-2. 10.2. BCD to Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-3. 10.3. Integer to BCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-4. 10.4. Integer to Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-5. 10.5. BCD to Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-6. 10.6. Double Integer to BCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-7. 10.7. Double Integer to Real . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-8. 10.8. Ones Complement Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-9. 10.9. Ones Complement Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10. 10.10. Twos Complement Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11. 10.11. Twos Complement Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12. 10.12. Negate Real Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13. 10.13. Round to Double Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14. 10.14. Truncate Double Integer Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15. 10.15. Ceiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16. 10.16. Floor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. ix.

(11) Contents. 11. 12. 13. 14. 15. 16. A. x. Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1. 11.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2. 11.2. (Word) AND Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-3. 11.3. (Word) AND Double Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-4. 11.4. (Word) OR Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-5. 11.5. (Word) OR Double Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-6. 11.6. (Word) Exclusive OR Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-7. 11.7. (Word) Exclusive OR Double Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-8. Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-1. 12.1. Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-2. 12.2. Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10. Data Block Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-1. 13.1. Open Data Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-2. Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-1. 14.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-2. 14.2. Unconditional Jump in a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-3. 14.3. Conditional Jump in a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-4. 14.4. Jump-If-Not . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-5. 14.5. Jump Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-6. Status Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-1. 15.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-2. 15.2. Exception Bit Binary Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-3. 15.3. Result Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-4. 15.4. Exception Bit Unordered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-6. 15.5. Exception Bit Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-7. 15.6. Exception Bit Overflow Stored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-8. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16-1. 16.1. Calling an FC/SFC without Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16-2. 16.2. Calling an FB, FC, SFB, SFC, and Multiple Instances . . . . . . . . . . . . . . . .. 16-4. 16.3. Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16-7. 16.4. Master Control Relay Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16-8. 16.5. Master Control Relay Activate/Deactivate . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10. 16.6. Master Control Relay On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13. Alphabetical Lists of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-1. A.1. A-2. List of Instructions with International Names . . . . . . . . . . . . . . . . . . . . . . . .. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(12) Contents. A.2. B. C. List of Instructions with International (English) Names and German Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-6. A.3. List of Instructions with German SIMATIC Names . . . . . . . . . . . . . . . . . . . .. A-10. A.4. List of Instructions with German Names and International (English) Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-14. Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-1. B.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-2. B.2. Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-3. B.3. Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-7. B.4. Counter and Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-11. B.5. Integer Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-13. B.6. Word Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-14. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. C-1. Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Glossary-1. Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Index-1. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. xi.

(13) Contents. xii. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(14) Product Overview. 1. What is FBD?. FBD stands for Function Block Diagram. FBD is a graphic programming language and uses logic boxes familiar from Boolean algebra to represent logic. Complex functions (for example math functions) can also be represented directly connected to the logic boxes.. The FBD Programming Language. The Function Block Diagram programming language has all the elements necessary for creating a complete user program. It contains a wide range of instructions. These include the various basic instructions and a wide range of addresses and address types. Functions and function blocks allow you to structure your FBD program clearly.. The Programming Package. The FBD programming package is an integral part of the STEP 7 Standard Software. This means that following the installation of your STEP 7 software, all the editor functions, compiler functions, and test/debug functions for FBD are available to you. Using FBD, you can create your own user program. With the Incremental Editor, the input of the local data structure is made easier with the help of table editors. There are three programming languages in the standard software, STL, FBD, and LAD. You can switch from one language to the other almost without restriction and choose the most suitable language for the particular block you are programming. If you write programs in LAD or FBD, you can always switch over to the STL representation. If you convert LAD programs into FBD programs and vice versa, program elements that cannot be represented in the destination language are displayed in STL.. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 1-1.

(15) 1-2. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(16) Configuration and Elements of Function Block Diagram. 2. Chapter Overview. Page. Section. Description. 2.1. Elements and Box Structure. 2-2. 2.2. Boolean Logic and Truth Tables. 2-6. 2.3. Significance of the CPU Registers in Statements. 2-9. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 2-1.

(17) Configuration and Elements of Function Block Diagram. 2.1. Elements and Box Structure. FBD Instructions. FBD instructions consist of elements and boxes that are connected graphically to form networks. The elements and boxes can be classified in the following groups:. Instructions as Elements. STEP 7 represents some of the FBD instructions as individual elements that do not require addresses or parameters (see Table 2-1). Table 2-1. FBD Instruction as an Element without Address or Parameters Element. Instruction as a Box with Address. Section in this Manual. Negate binary input. 4.7. STEP 7 represents some of the FBD instructions as boxes for which you must specify an address (see Table 2-2). For more detailed information about addressing, refer to Chapter 3. Table 2-2. FBD Instruction as Box with Address Element. <Address>. =. Instruction as a Box with Address and Value. Description. Description. Section in this Manual. Assign. 4.8. STEP 7 represents some of the FBD instructions as boxes for which you specify an address and a value (for example a timer or counter value, see Table 2-3). For more detailed information about addressing, refer to Chapter 3. Table 2-3. FBD Instruction as a Box with Address and Value Element. Description. Section in this Manual. Retentive on-delay timer. 4.19. <Address>> SS <Time value>. 2-2. TV. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(18) Configuration and Elements of Function Block Diagram. Instruction as Box with Parameters. STEP 7 represents some of the FBD instructions as boxes with inputs and outputs (see Table 2-4). The inputs are on the left of the box and the outputs on the right. You specify the input parameters and some of the output parameters. Most outputs are provided by the STEP 7 software. To assign parameters, you must use the specific notation of the data types. The parameters of the Enable input (EN) and the Enable output (ENO) are described below. For further information about input and output parameters, refer to the descriptions of the individual instructions in this manual. Table 2-4. FBD Operation as a Box with Inputs and Outputs Box. Description. Section in this Manual. Divide real. 8.5. DIV_R EN. Enable Input and Enable Output Parameters. IN1. OUT. IN2. ENO. If the Enable input (EN) of an FBD box is activated, the box carries out a specific function. If the function is executed by the box without errors, the Enable output (ENO) is activated. The parameters EN and ENO of an FBD box are of the BOOL data type and can be located in the I, Q, M, D, or L memory areas (see Table 2-5 and 2-6). How EN and ENO function is described below:.  If EN is not activated (its signal state is 0), the box does not execute its function and ENO is not activated (its signal state is also 0)..  If EN is activated (its signal state is 1) and if the box executes its function without errors, ENO is also activated (its signal state is also 1)..  If EN is activated (its signal state is 1) and if an error occurs during the execution of the function, ENO is not activated (its signal state remains 0).. Memory Areas and Functions. The majority of the addresses in FBD refer to memory areas. The following table shows the types and their functions.. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 2-3.

(19) Configuration and Elements of Function Block Diagram. Table 2-5. Memory Areas and Their Functions Access to Area. Name of Area. Function of Area. Process input image. At the beginning of the scan cycle, the operating system reads the inputs from the process and records the values in this area. The program uses these values when it is running cyclically.. Using Units of the Following Size:. Process output During the scan cycle, the program calculates output values and image enters them in this area. At the end of the scan cycle, the operating system reads the calculated output values from this area and sends them to the process outputs.. Abbr.. Input bit Input byte Input word Input double word. I IB IW ID. Output bit Output byte Output word Output double word. Q QB QW QD. Bit memory. This area provides memory space for interim results calculated Memory bit in the program. Memory byte Memory word Memory double word. M MB MW MD. I/Os. Using this area, your program has direct access to input and output modules (peripheral inputs and outputs).. Peripheral input byte Peripheral input word Peripheral input double word. PIB PIW PID. Peripheral output byte Peripheral output word Peripheral output double word. PQB PQW PQD. Timer (T). T. Ext. inputs I/Os: Ext. outputs Timers. Timers are function elements in FBD. This area provides memory space for timer cells. In this area, the clock timing accesses the timer cells and updates them by decrementing the timer value. Timer operations access these timer cells.. Counters. Counters are function elements in FBD. This area provides Counter (C) memory space for counters. Count instructions access the cells in this area.. Data block. This area contains data that can be accessed from within any block. If it is necessary to open two data blocks at the same time, you can open one with the “OPN DB” instruction and the other with the “OPN DI” instruction. The notation of the addresses, for example L DBWi and L DIWi identifies the data block to be accessed. Although you can access any data block with the “OPN DI” i instruction, i this hi iinstruction i iis mainly i l used d to open iinstance ddata blocks that are assigned to function blocks (FBs) and system function blocks (SFBs). For more detailed information about FBs and SFBs, refer to the STEP 7 Online Help.. Data block opened with the “OPN DB” instruction: Data bit Data byte Data word Data double word. DBX DBB DBW DBD. Data block opened with the “OPN DI” instruction: Data bit Data byte Data word Data double word. DIX DIB DIW DID. This area contains temporary local data belonging to a logic block (FB or FC). This type of data is also called dynamic local data. This area is used as a buffer. When the logic block is closed, the data are lost. These data are located in the local data stack (L stack).. Temporary local data bit Temporary local data byte Temporary local data word Temporary local data double word. Local data. 2-4. C. L LB LW LD. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(20) Configuration and Elements of Function Block Diagram. Table 2-6 lists the maximum address ranges for the various memory areas. For more detailed information about the address ranges on your CPU, refer to the corresponding manual /70/ or /101/. Table 2-6. Memory Areas and Their Address Ranges Access Using. Name of Area. Units of the Following Sizes:. Abbr.. M i Maximum Address Add Range R. Process input image Input bit Input byte Input word Input double word. I IB IW ID. 0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532. Process output image. Output bit Output byte Output word Output double word. Q QB QW QD. 0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532. Bit memory. Memory bit Memory byte Memory word Memory double word. M MB MW MD. 0.0 to 255.7 0 to 255 0 to 254 0 to 252. I/Os: External inputs. Peripheral input byte Peripheral input word Peripheral input double word. PIB PIW PID. 0 to 65 535 0 to 65 534 0 to 65 532. I/Os: External outputs. Peripheral output byte Peripheral output word Peripheral output double word. PQB PQW PQD. 0 to 65 535 0 to 65 534 0 to 65 532. Timers. Timer. T. 0 to 255. Counters. Counter. C. 0 to 255. Data block. Data block opened with the DB [OPN] instruction DBX DBB DBW DBD. 0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532. Data bit in the instance DB Data byte Data word Data double word. DIX DIB DIW DID. 0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532. Temporary local data bit Temporary local data byte Temporary local data word Temporary local data double word. L LB LW LD. 0.0 to 65 535.7 0 to 65 535 0 to 65 534 0 to 65 532. Data bit in the data block Data byte Data word Data double word Data block opened with the DI [OPN] instruction. Local data 1). 1). With FBD instructions, you can only use an address in the L memory area when you declare it as VAR_TEMP in the variable declaration table.. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 2-5.

(21) Configuration and Elements of Function Block Diagram. 2.2. Boolean Logic and Truth Tables. Boolean Logic. The FBD programming language is based on the binary logic of Boolean algebra in which variables can adopt the values “true” (1) or “false” (0). Each logic instruction checks the signal state of a variable for 1 (true, satisfied) or 0 (false, not satisfied) and then produces a result. The instruction then either saves the result or uses it to perform a Boolean logic operation. The result of the logic operation is known as the RLO. To represent the logic, the logic boxes known from Boolean algebra are used. The results of the logic instructions for all possible combinations of logical variables are listed in truth tables. The rules of Boolean logic are illustrated below based on the AND, OR, and exclusive OR logic operations.. AND Logic Operation. In an AND logic operation, the signal states of two or more specified addresses are checked. If the signal state of the address is 1 the condition is satisfied and the instruction produces the result 1. If the signal state of the address is 0, the condition is not satisfied and the operation produces the result 0. Figure 2-1 illustrates an AND logic operation in the FBD programming language.. The condition is satisfied when the signal state is 1 at inputs I1.0 AND I1.1.. & I1.0 I1.1 Figure 2-1. Q4.0 = AND Logic Operation in FBD. The possible results of an AND logic operation can be represented in a truth table. Here, 1 means “satisfied” and 0 means “not satisfied”. The possible logic instructions and their results are shown in Table 2-7. Table 2-7. AND Truth Table. If the result of the signal and the result of the signal the result of the logic instruction is as follows: state check at address I1.0 state check at address I1.1 is as below is as below. 2-6. 1. 1. 1. 0. 1. 0. 1. 0. 0. 0. 0. 0. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(22) Configuration and Elements of Function Block Diagram. OR Logic Operation. In an OR logic operation, the signal states of two or more specified addresses are checked. If the signal state of one of the addresses is 1, the condition is satisfied and the instruction provides the result 1. If the signal state of all addresses is 0, the condition is not satisfied and the instruction produces the result 0. Figure 2-2 shows an OR logic operation in the FBD programming language.. >=1 Q4.0 =. I1.0 I1.1. Figure 2-2. The condition is satisfied when the signal state is 1 at inputs I1.0 OR I1.1.. OR Logic Operation in FBD. The possible results of an OR logic operation can be shown in a truth table. Here, 1 means “satisfied” and 0 means “not satisfied”. The possible logic operations and their results are shown in Table 2-8. Table 2-8. Exclusive OR Logic Operation. OR Truth Table. If the result of the signal state check at address I1.0 is as below. and the result of the the result of the logic instruction is as follows: signal state check at address I1.1 is as below. 1. 0. 1. 0. 1. 1. 1. 1. 1. 0. 0. 0. In an exclusive OR logic operation, the signal states of two or more specified addresses are checked. If the signal state of one of the addresses is 1 the condition is satisfied and the instruction provides the result 1. If the signal state of all addresses is 0 or 1, the condition is not satisfied and the instruction produces the result 0. Figure 2-3 shows an exclusive OR logic operation in the FBD programming language.. XOR Q4.0 =. I1.0 I1.1. Figure 2-3. The condition is satisfied when the signal state is 1 at input I1.0 OR at input I1.1 exclusively (i.e. not at both).. Exclusive OR Logic Operation in FBD. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 2-7.

(23) Configuration and Elements of Function Block Diagram. The possible results of an exclusive OR logic operation can be represented in a truth table. Here, 1 means “satisfied” and 0 means “not satisfied”. The possible logic operations and their results are shown in Table 2-9. Table 2-9. Exclusive OR Truth Table. and the result of the the result of the logic instruction If the result of the signal state check at is as follows: signal state check at address I1.0 is as below address I1.1 is as below. 2-8. 1. 0. 1. 0. 1. 1. 1. 1. 0. 0. 0. 0. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(24) Configuration and Elements of Function Block Diagram. 2.3. Significance of the CPU Registers in Statements. Explanation. Registers help the CPU perform logic, math, shift, or conversion instructions. These registers are described below.. Accumulators. The accumulators are general-purpose registers that you use to process bytes, words, and double-words. The accumulators are 32-bits wide.. 31. 24. 23. High byte. 16. 8 7. Low byte. High word Figure 2-4. 15 High byte. 0 Low byte. Low word. Accumulator (1 or 2). Areas of an Accumulator. Status Word. The status word contains bits that you can reference in the address of bit logic instructions. The following sections explain the significance of bits 0 through 8. 215.... Figure 2-5. Changes in the Bits of the Status Word. ...29. 28. 27. 26. 25. BR. CC1. CC0. OV. 24 OS. 23. 22. 21. 20. OR. STA. RLO FC. Structure of the Status Word. Value. Meaning. 0. Sets the signal state to 0. 1. Sets the signal state to 1. x. Changes the state. –. State remains unchanged. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 2-9.

(25) Configuration and Elements of Function Block Diagram. First Check. Bit 0 of the status word is called the first-check bit (FC bit, see Figure 2-5). At the start of an FBD network, the signal state of the FC bit is always 0, unless the previous network ended with the SAVE box Each logic instruction checks the signal state of the FC bit as well as the signal state of the contact that the instruction addresses. The signal state of the FC bit determines the sequence of a logic string. If the FC bit is 0 (at the start of an FBD network), the instruction stores the result in the result of logic operation bit (RLO) of the status word and sets the FC bit to 1. This is known as the first check. The 1 or 0 that is set in the RLO bit after the first check is then referred to as the result of first check. If the signal state of the FC bit is 1, an instruction then combines the result of its signal state check at the addressed contact with the RLO formed at the addressed contact after the first check, and sets the result in the RLO bit. A logic string made up of FBD instructions always ends with an output instruction (for example set output, reset output, assign) or with a jump instruction dependent on the result of the logic operation (RLO). These instructions reset the FC bit to 0.. Result of Logic Operation. Bit 1 of the status word is called the result of logic operation bit (RLO bit, see Figure 2-5). This bit stores the result of a string of logic instructions or compare instructions. The signal state of the RLO bit provides information about signal flow. The first instruction in an FBD network checks the signal state of an address and produces a result of 1 or 0. The instruction enters the result of this signal state in the RLO bit. The second instruction in a string of logic operations also checks the signal state of an address and produces a result. The instruction now combines this result with the value of the RLO bit of the status word according to the rules of Boolean logic (see First Check above). The result of the logic operation is entered in the RLO bit of the status word and replaces the previous value in the RLO bit. Each subsequent instruction in the string of logic operations combines two values: the result of the signal check at the specified address and the current RLO. You can, for example, assign the state of a bit memory location to the RLO during a first check using a Boolean logic operation or trigger a jump instruction.. 2-10. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(26) Configuration and Elements of Function Block Diagram. Status Bit. Bit 2 of the status word is called the status bit (STA bit, see Figure 2-5). The status bit stores the value of a bit that is referenced. The status of a logic instruction that reads memory is always the same as the value of the bit that this instruction checks (the bit on which it performs its logic operation). The status of a bit instruction that writes to memory (Set Output, Reset Output, or Assign) is the same as the value of the bit to which the instruction writes. If no writing takes place, the value is the same as the value of the bit that the instruction references. The status bit has no significance for bit instructions that do not access memory. These instructions set the status bit to 1 (STA=1). The status bit is not checked by an instruction. It is interpreted during program test (program status) only.. OR Bit. Bit 3 of the status word is called the OR bit (see Figure 2-5). The OR bit is required to execute an AND before OR logic operation. An AND logic operation can contain the instructions AND input and AND NOT input. The OR bit indicates to the instructions that a previously executed AND logic operation produced the value 1 so that the result of the OR logic operation has already been determined. Any other bit-processing instruction resets the OR bit.. Overflow Bit. Bit 5 of the status word is called the overflow bit (OV bit, see Figure 2-5). The OV bit indicates an error. It is set by a math instruction or a compare floating-point numbers instruction after an error has occurred (overflow, illegal instruction, illegal floating-point number). The bit is set or reset according to the result of the math or compare instruction (error).. Stored Overflow Bit. Bit 4 of the status word is called the store overflow bit (OS bit, see Figure 2-5). The OS bit is set together with the OV bit when an error occurs. Since the OS bit is unchanged when math instructions are executed without errors (in contrast to the OV bit), this indicates whether or not an error occurred in one of the previously executed instructions. The following instructions reset the OS bit: JOS (jump if stored overflow bit = 1, must be programmed in STL), block calls and block end statements.. CC1 and CC0. Bits 7 and 6 of the status word are called condition code 1 and condition code 0 (CC1 and CC0, see Figure 2-5). The CC1 and CC0 bits provide information about the following results or bits:.  Result of a math instruction  Result of a compare instruction  Result of a digital instruction  Bits that have been shifted out of the address by a shift or rotate instruction. Tables 2-10 to 2-15 list the meaning of CC1 and CC0 after your program has executed certain instructions.. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 2-11.

(27) Configuration and Elements of Function Block Diagram. Table 2-10. CC1 and CC0 after Math Instructions, without Overflow. CC1. CC0. Explanation. 0. 0. Result = 0. 0. 1. Result < 0. 1. 0. Result > 0. Table 2-11. CC1 and CC0 after Integer Math Instructions, with Overflow. CC1. CC0. Explanation. 0. 0. Negative range overflow in Add Integer and Add Double Integer. 1. Negative range overflow in Multiply Integer and Multiply Double Integer Positive range overflow in Add Integer, Subtract Integer, Add Double Integer, Subtract Double Integer, Twos Complement Integer, and Twos Complement Double Integer. 1. 0. Positive range overflow in Multiply Integer and Multiply Double Integer, Divide Integer, and Divide Double Integer Negative range overflow in Add Integer, Subtract Integer, Add Double Integer, and Subtract Double Integer. 1. 1. Division by 0 in Divide Integer, Divide Double Integer, and Return Fraction Double Integer. 0. Table 2-12. 2-12. CC1 and CC0 after Floating-Point Math Instructions, with Overflow. CC1. CC0. 0. 0. Gradual underflow. 0. 1. Negative range overflow. 1. 0. Positive range overflow. 1. 1. Not a valid floating-point number. Explanation. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(28) Configuration and Elements of Function Block Diagram. Table 2-13. CC1 and CC0 after Comparison Instructions. CC1. CC0. 0. 0. IN2 = IN1. 0. 1. IN2 < IN1. 1. 0. IN2 > IN1. 1. 1. IN1 or IN2 is not a valid floating-point number. Table 2-14. CC1 and CC0 after Shift and Rotate Instructions. CC1. CC0. 0. 0. Bit shifted out last = 0. 1. 0. Bit shifted out last = 1. Table 2-15. Binary Result Bit. Explanation. Explanation. CC1 and CC0 after Word Logic Instructions. CC1. CC0. 0. 0. Explanation Result = 0. 1. 0. Result <> 0. Bit 8 of the status word is called the binary result bit (BR bit, see Figure 2-5). The BR bit forms a link between the processing of bits and words. This bit is an efficient method with which you can interpret the result of a word instruction as a binary result and include this result in a binary string of logic operations. The BR bit represents an internal memory bit in which the RLO can be saved prior to a word instruction that changes the RLO so that the old RLO is available again after the operation when the interrupted series of bit instructions is resumed. With the BR bit, you can, for example, program a function block (FB) or a function (FC) in Statement List (STL) and call the FB or FC in FBD. If you write a function block or a function that you want to call in FBD, regardless of whether you write the FB or FC in STL or FBD, you must take into account the BR bit. The BR bit corresponds to the Enable output (ENO) of an FBD box. You save the RLO in the BR bit using the SAVE instruction (in STL) or with the SAVE FBD box according to the following criteria:.  Save an RLO of 1 in the BR bit when the FB or FC is processed without errors..  Save an RLO of 0 in the BR bit if an error occurs during the processing of an FB or FC. Program these instructions at the end of the FB or FC so that they are the last instructions executed in the block.. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 2-13.

(29) Configuration and Elements of Function Block Diagram. !. Meaning of EN/ENO. Warning The BR bit can be reset to 0 unintentionally. When you write FBs or FCs in FBD and do not handle the BR bit as described above, an FB or FC might overwrite the BR bit of another FB or FC. To avoid this problem, save the RLO at the end of each FB or FC as described above.. The Enable input (EN) and Enable output (ENO) parameters of an FBD box function as explained below:.  If EN is not activated (its signal state is 0), the box does not execute its function and ENO is not activated (it also has a signal state of 0)..  If EN is activated (its signal state is 1) and the box executes its function without errors, ENO is also activated (its signal state is also 1)..  If EN is activated (its signal state is 1) and an error occurs while the function is being executed, ENO is not activated (its signal state is 0). When you call a system function block (SFB) or a system function (SFC) in your program, the SFB or SFC indicates whether or not the CPU executed the function without errors by setting the signal state of the BR bit:.  If an error occurred during execution, the BR bit is set to 0.  If the function was executed without errors, the BR bit is 1.. 2-14. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(30) 3. Addressing Chapter Overview. Section. Description. Page. 3.1. Overview. 3-2. 3.2. Types of Addresses. 3-4. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 3-1.

(31) Addressing. 3.1. Overview. What is Addressing?. Many FBD instructions operate with one or more addresses. The address specifies a constant or a location at which the instruction finds a variable which it uses to perform a logic operation. This location can be a bit, byte, word, or double word. Examples of possible addresses are as follows:.  A constant, the value of a timer or counter, or an ASCII character string  A bit in the status word of the programmable controller  A data block and a location within the data block area Immediate and Direct Addressing. The following types of addressing are available:.  Immediate addressing (specifying a constant as the address)  Direct addressing (specifying a variable as the address) Figure 3-1 shows an example of immediate and direct addressing. The function of the box is to compare two input parameters (in this case, two 16-bit integers) to see if the first input is less than or equal to the second. The constant 50 is entered as input parameter IN1. Memory word MW200, a location in memory, is entered as input parameter IN2. Because the constant 50 in the example is the actual value with which IN1 of the box will work, 50 is an immediate address of the instruction box. Because MW200 points to a location in memory where there is another value with which IN2 of the box will work, MW200 is a direct address. MW200 is a location, not the actual value itself.. CMP <= I. Figure 3-1. 3-2. 50. IN1. MW200. IN2. Immediate and Direct Addressing. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(32) Addressing. Table 3-1. Constant Formats for Immediate Addressing Using Addresses of Elementary Data Types. Size in Format Options Type and Description Bits. Range and Number Notation (Lowest Value to Highest Value). Example. BOOL (Bit). 1. Boolean Text. TRUE/FALSE. TRUE. BYTE (Byte). 8. Hexadecimal. B#16#0 to B#16#FF. B#16#10 byte#16#10. WORD (Word). 16. Binary. 2#0001_0000_0000_0000. Hexadecimal. 2#0 to 2#1111_1111_1111_1111 W#16#0 to W#16#FFFF. BCD Unsigned decimal. C#0 to C#999 B#(0,0) to B#(255,255). Binary. 2#0 to 2#1111_1111_1111_1111_ 1111_1111_1111_1111 DW#16#0000_0000 to DW#16#FFFF_FFFF B#(0,0,0,0) to B#(255,255,255,255). 2#1000_0001_0001_1000_ 1011_1011_0111_1111. DWORD (Double word). 32. Hexadecimal Unsigned decimal. W#16#1000 word16#1000 C#998 B#(10,20) byte#(10,20). DW#16#00A2_1234 dword#16#00A2_1234 B#(1,14,100,120) byte#(1,14,100,120). INT (Integer). 16. Signed decimal. -32768 to 32767. 1. DINT (Double integer). 32. Signed decimal. L#-2147483648 to L#2147483647. L#1. REAL (Floating point). 32. IEEE floating point. Upper limit: ±3.402823e+38 Lower limit: ±1.175495e-38 ). 1.234567e+13. S5TIME (SIMATIC time). 16. S5 Time in 10-ms units (as default value). S5T#0H_0M_0S_10MS to S5T#2H_46M_30S_0MS and S5T#0H_0M_0S_0MS. S5T#0H_1M_0S_0MS S5TIME#0H_1M_0S_0MS. TIME (IEC time). 32. IEC time in 1-ms units, signed integer. T#-24D_20H_31M_23S_648MS to T#24D_20H_31M_23S_647MS. T#0D_1H_1M_0S_0MS TIME#0D_1H_1M_0S_0MS. DATE (IEC date). 16. IEC date in 1-day units. D#1990-1-1 to D#2168-12-31. D#1994-3-15 DATE#1994-3-15. TIME_OF_ DAY (Time of day). 32. Time of day in 1-ms units. TOD#0:0:0.0 to TOD#23:59:59.999. TOD#1:10:3.3 TIME_OF_DAY#1:10:3.3. CHAR (Character). 8. Character. ’A’,’B’, etc.. ’E’. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 3-3.

(33) Addressing. 3.2. Types of Addresses. Possible Addresses. One of the following elements can be used as the address of an FBD instruction:.  A bit whose signal state will be checked  A bit to which the signal state of the logic operation string will be assigned.  A bit to which the result of logic operation (RLO) will be assigned  A bit that will be set or reset  A number that indicates a counter that will be incremented or decremented.  A number that indicates a timer to be used  An edge memory bit that saves the previous RLO  An edge memory bit that saves the previous signal state of a different address.  A byte, word, or double word containing a value with which the FBD element or box will work.  The number of a data block (DB or DI) that will be opened or created  The number of a function (FC), system function (SFC), a function block (FB), or system function block (SFB) that will be called.  A label as the destination for a jump Address Identifiers. Variables as addresses consist of an address identifier and an address within the memory area indicated by the address identifier. An address identifier can be one of the following two basic types:.  An address identifier that indicates the following two data objects: – The memory area in which the instruction finds a value (data object) with which it can perform a logic operation (for example “I” for process input image, see Table 2-5). – The size of a value (data object) with which the instruction will perform a logic operation (for example B for “Byte”, W for “Word” and D for “Double Word”, see Table 2-5)..  An address identifier that indicates a memory area but not the size of the data object in the area (for example an identifier for the T area (timers), C (counters), or DB or DI (data block) and the number of the timer, counter, or data block, see Table 2-5).. 3-4. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(34) Addressing. Pointers. A pointer identifies the location of a variable. A pointer contains an address instead of a value. When assigning an actual parameter for the parameter type “Pointer”, you provide the memory address. With STEP 7, you can enter the pointer either in the pointer format or simply as an address (for example M 50.0). The following example illustrates the pointer format for accessing data starting at M 50.0. P#M50.0. Working with Words or Double Words as the Data Object. If you are working with an instruction whose address identifier indicates a memory area of your programmable controller and a data object that is either a word or double word in size, remember that the memory location is always referenced as a byte address. This byte address is the smallest byte number or the number of the high byte within the word or double word. The address in the instruction shown in Figure 3-2, for example, references four successive bytes in the memory area M starting at byte 10 (MB10) through to byte 13 (MB13).. Instruction: L MD10 Address identifier. Figure 3-2. Byte address. Example of a Memory Location Referenced as a Byte Address. Figure 3-3 shows data objects with the following sizes:.  Double word: memory double word MD10  Word: memory word MW10, MW11 and MW12  Byte: memory bytes MB10, MB11, MB12 and MB13 If you use absolute addresses that are a word or double word long, make sure that you avoid any overlapping byte assignments.. MW10 MB10. MW12 MB11. MB12. MB13. MW11 MD10 Figure 3-3. Referencing a Memory Location as a Byte Address. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 3-5.

(35) Addressing. 3-6. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(36) 4. Bit Logic Instructions Chapter Overview. Section. Description. Page. 4.1. Overview. 4-2. 4.2. AND Logic Operation. 4-3. 4.3. OR Logic Operation. 4-4. 4.4. AND-before-OR Logic Operation and OR-before-AND Logic Operation. 4-5. 4.5. Exclusive OR Logic Operation. 4-6. 4.6. Insert Binary Input. 4-7. 4.7. Negate Binary Input. 4-8. 4.8. Assign. 4-9. 4.9. Midline Output. 4-10. 4.10. Save RLO to BR Memory. 4-11. 4.11. Set Output. 4-12. 4.12. Reset Output. 4-13. 4.13. Set Counter Value. 4-14. 4.14. Up Counter Instruction. 4-16. 4.15. Down Counter Instruction. 4-17. 4.16. Pulse Timer Instruction. 4-18. 4.17. Extended Pulse Timer Instruction. 4-20. 4.18. On-Delay Timer Instruction. 4-22. 4.19. Retentive On-Delay Timer Instruction. 4-24. 4.20. Off-Delay Timer Instruction. 4-26. 4.21. Positive RLO Edge Detection. 4-28. 4.22. Negative RLO Edge Detection. 4-29. 4.23. Address Positive Edge Detection. 4-30. 4.24. Address Negative Edge Detection. 4-31. 4.25. Set_Reset Flip Flop. 4-32. 4.26. Reset_Set Flip Flop. 4-33. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 4-1.

(37) Bit Logic Instructions. 4.1. Overview. Explanation. Bit logic instructions work with two digits, 1 and 0. These two digits form the base of a number system called the binary system. The two digits 1 and 0 are called binary digits or simply bits. In conjunction with AND, OR, XOR and outputs, a 1 stands for logical YES and a 0 for logical NO. The bit logic instructions interpret the signal states 1 and 0 and combine them according to the rules of Boolean logic. These combinations produce a result of 1 or 0 known as the result of logic operation (RLO, see Section 2.2). The logic operations triggered by the bit logic instructions execute a variety of functions.. Functions. Bit logic instructions are available for the following functions:.  AND, OR, and XOR: these instructions check the signal state and produce a result that is either copied to the RLO bit or combined with it. With AND logic operations, the result of the signal state check is combined according to the AND truth table (see Table 2-7). With OR logic operations, the result of the signal state check is combined according to the OR truth table (see Table 2-8), with exclusive OR logic operations, according to the exclusive OR truth table (see Table 2-9)..  Assign and Midline Output: these instructions assign the RLO or store it temporarily..  The following instructions react to an RLO of 1: – Set Output and Reset Output – Set_Reset Flip Flop and Reset_Set Flip Flop.  Some instructions react to a rising or falling edge so that you can execute the following functions: – Increment or decrement the value of a counter – Start a timer – Produce an output of 1.  The remaining instructions affect the RLO directly in the following ways: – Negate the RLO – Save the RLO in the binary result bit of the status word In this chapter, the counter and timer instructions are shown in the international and SIMATIC forms.. 4-2. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(38) Bit Logic Instructions. 4.2. AND Logic Operation. Description. With the AND instruction, you can check the signal states of two or more specified addresses at the inputs of an AND box. If the signal state of all addresses is 1, the condition is satisfied and the instruction provides the result 1. If the signal state of an address is 0, the condition is not satisfied and the instruction produces the result 0. If the AND instruction is the first instruction in a string of logic operations, it saves the result of its signal state check in the RLO bit. Every AND instruction that is not the first instruction in the string of logic operations, combines the result of its signal state check with the value stored in the RLO bit. These values are combined according to the AND truth table.. Table 4-1. AND Box and Parameters Parameters. FBD Box <address> <address>. Data Type. <address>. BOOL TIMER COUNTER. &. Memory Area. Description. I, Q, M, T, C, D, L. The address indicates the bit whose signal state will be checked.. &. I0.0. Q4.0 =. I0.1. Output Q4.0 is set when the signal state is 1 at input I0.0 AND I0.1.. Status Word Bits. writes Figure 4-1. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. x. x. x. 1. AND Logic Operation. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 4-3.

(39) Bit Logic Instructions. 4.3. OR Logic Operation. Description. With the OR instruction, you can check the signal states of two or more specified addresses at the inputs of an OR box. If the signal state of one of the addresses is 1, the condition is satisfied and the instruction produces the result 1. If the signal state of all addresses is 0, the condition is not satisfied and the instruction produces the result 0. If the OR instruction is the first instruction in a string of logic operations, it saves the result of its signal state check in the RLO bit. Each OR instruction that is not the first instruction in the string of logic operations combines the result of its signal state check with the value stored in the RLO bit. These values are combined according to the OR truth table.. Table 4-2. OR Box and Parameters Parameters. FBD Box <address> <address>. Data Type. <address>. BOOL TIMER COUNTER. >=1. Memory Area. Description. I, Q, M, T, C, D, L. The address specifies the bit whose signal state will be checked. >=1. I0.0. Q4.0 =. I0.1. Output Q4.0 is set when the signal state is 1 at input I0.0 OR at input I0.1.. Status Word Bits. writes Figure 4-2. 4-4. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. x. x. x. 1. OR Logic Operation. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(40) Bit Logic Instructions. 4.4. AND-before-OR Logic Operation and OR-before-AND Logic Operation. Description. With the AND-before-OR instruction, you can check the result of a signal state according to the OR truth table. With an AND-before-OR logic operation the signal state is 1 when at least one AND logic operation is satisfied.. &. I0.0 I0.1. The signal state is 1 at output Q3.1 when at least one AND logic operation is satisfied.. >=1. The signal state is 0 at output Q3.1 when no AND logic operation is satisfied.. &. I0.2. Q3.1 =. I0.3. Status Word Bits. writes Figure 4-3. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. x. x. x. 1. AND-before-OR Logic Operation. Description. With the OR-before-AND instruction, you can check the result of a signal state check according to the AND truth table. With an OR-before-AND logic operation the signal state is 1 when all OR logic operations are satisfied.. I1.0. >=1. I1.1. The signal state is 1 at output Q3.1 when both OR logic operations are satisfied.. &. The signal state is 0 at output Q3.1 when at least one OR logic operation is not satisfied.. >=1. I1.2. Q3.1 =. I1.3. Status Word Bits. writes Figure 4-4. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. x. x. x. 1. OR-before-AND Logic Operation. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 4-5.

(41) Bit Logic Instructions. 4.5. Exclusive OR Logic Operation. Description. With the Exclusive OR instruction, you can check the result of a signal state check according to the Exclusive OR truth table. With an Exclusive OR logic operation, the signal state is 1 when the signal state of one of the two specified addresses is 1.. Table 4-3. Exclusive OR Box and Parameters. FBD Box. Parameters. Data Type. <address> <address> <address>. BOOL TIMER COUNTER. XOR. Q3.1 =. I0.2. Description. I, Q, M, T, C, D, L. The address specifies the bit whose signal state will be checked.. The signal state is 1 at output Q3.1 when the signal state is 1 at either input I0.0 OR at input I0.2 (exclusively, in other words not at both).. XOR I0.0. Memory Area. Status Word Bits. writes. Figure 4-5. 4-6. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. x. x. x. 1. Exclusive OR Logic Operation. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(42) Bit Logic Instructions. 4.6. Insert Binary Input. Description. Table 4-4. The Insert Binary Input instruction inserts a further binary input to an AND, OR, or XOR box. Binary Input Element and Parameters Parameters. FBD Element. <address>. <address>. I1.0 I1.1 I1.2. Data Type BOOL TIMER COUNTER. Memory Area. Description. I, Q, M, T, C, D, L. The address specifies the bit whose signal state will be checked. Output Q4.0 is 1 when the signal state at I1.0 AND I1.1 AND I1.2 is 1.. & Q4.0 =. Status Word Bits. writes Figure 4-6. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. –. 1. x. –. Insert Binary Input. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 4-7.

(43) Bit Logic Instructions. 4.7. Negate Binary Input. Description. The Negate Binary Input instruction negates the RLO. When you negate the result of logic operation, you must remember certain rules:.  If the result of logic operation at the first input of an AND or OR box is negated, there is no nesting..  If the result of logic operation is negated but not at the first input of an OR box, the entire binary logic operation before the input is included in the OR logic operation..  If the result of logic operation is negated but not at the first input of a AND box, the entire binary logic operation before the input is included in the AND logic operation. Table 4-5. Negate Binary Input Element. FBD Element. Parameters. Data Type. None. I1.0 I1.1. I1.2 I1.3. –. Memory Area –. Description –. Output Q4.0 is 1 when:. &. the signal state at I1.0 AND I1.1 is NOT 1 &. AND the signal state at I1.2 AND I1.3 is NOT 1 OR the signal state at I1.4 is NOT 1.. & >=1 Q4.0 =. I1.4. Status Word Bits. writes Figure 4-7. 4-8. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. –. 1. x. –. Negate Binary Input. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(44) Bit Logic Instructions. 4.8. Assign. Description. The Assign instruction produces the result of logic operation. The box at the end of a logic operation has the signal 1 or 0 according to the following criteria:.  The output has the signal 1 when the conditions of the logic operation before the output box are satisfied.  The output has the signal 0 when the conditions of the logic operation before the output box are not satisfied. The FBD logic operation assigns the signal state to the output that is addressed by the instruction (to achieve the same effect, the signal state of the RLO bit could also be assigned to the address). If the conditions of the FBD logic operations are satisfied, the signal state at the output box is 1. Otherwise the signal state is 0. The Assign instruction is influenced by the Master Control Relay (MCR). For more detailed information about the functions of the MCR, refer to Section 16.4. You can only place the Assign box at the right-hand end of the string of logic operations. You can, however, use several Assign boxes. You can create a negated assignment with the Negate Input instruction. Table 4-6. Assign Box and Parameters Parameters. FBD Box <address> =. I0.0. <address>. Data Type BOOL. &. I0.1. Memory Area I, Q, M, D, L. Description The address specifies the bit to which the signal state of the string of logic operations is assigned.. The signal state at output Q4.0 is 1 when the signal state is 1 at inputs I0.0 AND I0.1, OR I0.2 is 0. >=1. I0.2. Q4.0 = Status Word Bits. writes Figure 4-8. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. 0. x. –. 0. Assign. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 4-9.

(45) Bit Logic Instructions. 4.9. Midline Output. Description. The Midline Output instruction is an intermediate element that buffers the RLO. More precisely, this element buffers the bit logic operation of the last branch to be opened before the Midline Output. The Midline Output instruction is influenced by the Master Control Relay (MCR). For more information about the MCR functions, see Section 16.4. You can create a negated Midline Output by negating the input of the Midline Output.. Table 4-7. Midline Output Box and Parameters Parameters. FBD Box <address> #. 1. <address>. Data Type BOOL. Memory Area I, Q, M, D,. Description. L1. The address specifies the bit to which the RLO will be assigned.. With the Connector instruction you can only use an address in the L memory area if you declare the address in VAR_TEMP; you cannot use the L memory area for absolute addresses.. I1.0 I1.1 I1.2 I1.3. M0.0 #. &. M1.1 #. &. &. >=1 DB5.DBX3.2 #. M2.2 #. I1.4. Q4.0 =. The Midline Outputs buffer the following results of the logic operations: M0.0 buffers the negated. &. RLO of. I1.0 I1.1. M2.2 the RLO of. I1.4. #. M1.1 the negated. I1.2 I1.3. RLO of. &. DB5.DBX3.2 the negated RLO of the entire bit logic operation in bit 2 of the 3rd bytes in DB 5.. Status Word Bits. writes Figure 4-9. 4-10. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. 0. x. –. 1. Midline Output. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(46) Bit Logic Instructions. 4.10 Save RLO to BR Memory. Description. The Save RLO to BR Memory instruction saves the RLO in the BR bit of the status word. The first check bit FC is not reset. For this reason, if there is an AND logic operation in the next network, the state of the BR bit is included in the logic operation. Using the “Save RLO to BR Memory” instruction in conjunction with checking the BR bit in the same block or on subordinate blocks is not recommended, because the BR bit can be modified by many instructions occurring inbetween. It is advisable to use the SAVE instruction before exiting a block, since the ENO output (=BR bit) is then set to the value of the RLO bit and you can then check for errors in the block. With the “Save RLO to BR Memory” instruction, the RLO of a network can form part of a logic operation in a subordinate block. The CALL instruction in the calling block resets the first check bit.. Table 4-8. Save RLO to BR Memory Box and Parameters. FBD Box. Parameters. Data Type. None. SAVE. I1.2 I1.3. –. Memory Area –. Description –. The result of logic operation (RLO) is written to the BR bit.. &. SAVE. Status Word Bits. writes Figure 4-10. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. x. –. –. –. –. –. –. –. –. Save RLO to BR Memory. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 4-11.

(47) Bit Logic Instructions. 4.11 Set Output. Description. The Set Output instruction is only executed when the RLO is 1. If the RLO is 1, this instruction sets the specified address to 1. If the RLO is 0, the instruction does not affect the specified address which remains unchanged. The Set Output instruction is influenced by the Master Control Relay (MCR). For more detailed information about the MCR, refer to Section 16.4.. Table 4-9. Set Output Box and Parameters. FBD Box. Parameters. <address>. <address>. Data Type BOOL. Memory Area I, Q, M, D, L. S. Description The address specifies which bit will be set.. The signal state at output Q4.0 is set to 1 only when: I0.0 I0.1.  The signal state is 1 at inputs I0.0 AND I0.1. & >=1.  OR the signal state at input I0.2 is 0.. Q4.0 S. I0.2. If the RLO of the branch is 0, the signal state of Q4.0 is not changed.. Status Word Bits. writes. Figure 4-11. 4-12. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. 0. x. –. 0. Set Output. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01.

(48) Bit Logic Instructions. 4.12 Reset Output. Description. The Reset Output instruction is only executed when the RLO is 1. If the RLO is 1, this instruction resets the specified address to 0. If the RLO is 0, the instruction does not affect the specified address which remains unchanged. The Reset Output instruction is influenced by the Master Control Relay (MCR). For more detailed information about the MCR, refer to Section 16.4.. Table 4-10. Reset Output Box and Parameters. FBD Box. Parameters. <address>. <address>. Data Type BOOL. Memory Area I, Q, M, T, C, D, L. TIMER. R. Description The address specifies which bit will be reset.. COUNTER. The signal state at output Q4.0 is reset to 0 only when: I0.0 I0.1.  The signal state is 1 at inputs I0.0 AND I0.1. & >=1.  OR the signal state at input I0.2 is 0.. Q4.0 R. I0.2. If the RLO of the branch is 0, the signal state at output Q4.0 is unchanged.. Status Word Bits. writes. Figure 4-12. BR. CC1. CC0. OV. OS. OR. STA. RLO. FC. –. –. –. –. –. 0. x. –. 0. Reset Output. Function Block Diagram (FBD) for S7-300 and S7-400 C79000-G7076-C566-01. 4-13.

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