DIPLODOCUS: An Environment for. the Hardware/Software Partitioning of. Institut Mines-Telecom. Complex Embedded Systems

(1)

Institut

Mines-Telecom

the Hardware/Software Partitioning of Complex Embedded Systems

Ludovic Apvrille,

[email protected]

(2)

Goals

I To share an experience of real-time systems modeling

I To propose a language, a tool, and a method dedicated to the partitioning of complex and real-time embedded systems

I DIPLODOCUS, a modeling language based on SysML

I TTool for model simulation and user-friendly formal verification

I A method that applies to a broad variety of real-time systems

(3)

Outline

Introduction

Context: Model-Driven Engineering Our contribution

Design Space Exploration

The DIPLODOCUS Approach DIPLODOCUS in a Nutshell Methodology

(4)

Outline

Introduction

Context: Model-Driven Engineering Our contribution

The DIPLODOCUS Approach Outlook

(5)

Designing Embedded Systems

How to Handle Complexity? Modeling and verification! (But there are other options)

(6)

Modeling is not Really a New Technique. . .

(7)

Abstraction Level

(8)

Software Development Techniques for E. S.

Code-based approaches I Extreme Programming I Strongly tested step-by-step code increments I Agile Software Development I Focus on change in specification Model-based approaches I V-Cycle

I KAOS, AADL, MDE, . . .

makingMessage sendingMessage chout(m1) m.data = secretData m1 = sencrypt(m, sk) I Formal models

(9)

Model Driven Engineering

Definition

I Process based on abstract graphical representations for a given domain

I Intends to improve software engineering quality criteria

I Reliability, extensibility, maintainability, . . .

I Should enhance team communication and documentation

Abstraction levels

I Platform Independent Model, Platform Specific Model

(10)

UML Profiles

Definition

I UML defines extension mechanisms to e.g.,

I Define new operators

I Provide a semantics

I Give a methodology

Example of profiles

I Profiles defined by OMG (e.g., SPT, MARTE, SysML)

I Profiles defined by tool vendors (e.g. in Rhapsody, Artisan)

(11)

UML Profiles and MDE

UML profiles are a way to define domain-specific languages for MDE

Definition of UML profiles for modeling and verifying complex embedded systems

Definition of methodologies based on the V-cycle Definition of model transformations for simulation,

formal verification and code generation purpose Implementation in a toolkit (TTool)

(12)

(13)

TTool: A Multi Profile Platform

TTool

I Open-source toolkit mainly developed by Telecom ParisTech / COMELEC

I Multi-profile toolkit

I DIPLODOCUS, AVATAR, . . .

I Support from academic (e.g. INRIA, ISAE) and industrial partners (e.g., Freescale)

Main ideas

I Lightweight, easy-to-use toolkit

I Simulation with model animation

(14)

Systems-on-Chip

I A System-On-Chip = set of SW and HW components intended to perform a predefined set of functions for a given market

I Constraints

I Right market window

(15)

Design Challenges

Complexity

I Very high software complexity

I Very high hardware complexity

Problem

How to decide whether a function should be implemented in SW or in HW, or both?

Solution

(16)

Design Space Exploration

I Analyzing various functionally equivalent implementation alternatives

I → Find an optimal solution

Important key design parameters

I Speed

I Power Consumption

I Silicon area

(17)

Level of Abstraction

Problematic

I Designers struggle with the complexity of today’s circuits

I Cost of late re-engineering

I Right decisions should be taken as soon as possible ...

I And quickly (time to market issue), and so, simulations must be fast

→ System Level Design Space Exploration

I Reusable models, fast simulations / formal analysis,

prototyping can start without all functions to be implemented But: high-level models must be closely defined so as to take the right decisions

(18)

Outline

Introduction

The DIPLODOCUS Approach DIPLODOCUS in a Nutshell Methodology

(19)

DIPLODOCUS in a Nutshell

DIPLODOCUS = UML Profile

I System-level Design Space Exploration

I Y-Methodology

I MARTE compliant

Main features

I Data are abstracted

I Formal semantics

I Very fast simulation support

I Fully supported by an open-source toolkit

(20)

(21)

(22)

(23)

(24)

Browsing the DIPLODOCUS Methododology

Application structure Application behavior Formal verification Architecture model Mapping model Simulation Formal verification

(25)

Application Structure (Smart Card system)

(26)

Application Behavior

(27)

Formal Verification at Application Level

I No assumption on the underlying architecture

I All possible interleavings between actions are considered

I Formal verification is based on LOTOS/CADP or UPPAAL

I Press-button approach

(28)

Architecture

I Given in terms of parameterized nodes

I CPU, HWA, Bus, Memory, Bridge, etc.

I CPU parameters: scheduling policy, cache miss ratio, miss-branching prediction, pipeline size, etc.

(29)

Mapping

I Task are mapped on execution nodes (e.g., CPUs, HWAs)

I Channels are mapped on communication and storage nodes

(30)

After-Mapping Simulation

I TTool Built-in simulator

I Extremly fast

I Diagram animation

I Step-by-step execution, breakpoints, etc.

(31)

After-Mapping Simulation (Cont.)

<<CPU>> CPU0 AppC::SmartCard AppC::Application AppC::TCPIP 50% 195 pW <<CPURR>> HW1 AppC::InterfaceDevice 66% 230 pW <<CPURR>>HW2 AppC::Timer 0% 90 pW <<BUS>> Bus0 0% <<MEMORY>> Memory0 Back to methodology

(32)

After-Mapping Formal Verification

I TTool built-in simulator can compute all possible execution paths

(33)

After-Mapping Coverage-Enhanced

Simulation

Possibility to select a given part of the model to be explored

I Minimum percentage of operators coverage

I Minimum percentage of branch coverage

(34)

Outline

Introduction

The DIPLODOCUS Approach Outlook

(35)

Results

Fully integrated environment for the partitioning of Systems-on-Chip and complex embedded systems

I Based on UML

I Open-source toolkit

I Partners: Texas Instruments, Freescale, European project EVITA, European project SACRA, LIP6, . . .

I 2 Ph.D. completed (Chafic Jaber, Daniel Knorreck, Jair Gonzalez-Pina), 2 on-going Ph.D. (F´eriel Ben Abdallah, Andrea Enrici)

(36)

A Few Case Studies ...

I MPEG coders and decoders (Texas Instruments)

I LTE SoC (Freescale)

I Partitioning in vehicle embedded systems (EVITA project)

I Partitioning and code generation for Software-Defined Radio systems (SACRA project)

(37)

To Go Further ...

TTool and DIPLODOCUS