EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues

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EE 459/500 – HDL Based Digital Design with Programmable Logic

Lecture 16

Timing and Clock Issues

Overview

 Sequential system timing requirements

 Impact of clock skew on timing

 Impact of clock jitter on timing

 Clock distribution

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Clocked Synchronous State Machine

Flip-Flop Timing Parameters

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Latch Timing Parameters

State Machine Timing

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Satisfying Timing Requirements

 The period must be long enough for the data to propagate through the registers and logic and to be set up at the destination register before the next rising edge of the clock.

Satisfied by making T long enough. Cycle time:

 T_CLK > t_c-q + t_logic + t_su

 The hold time at the destination register must be shorter than the minimum propagation delay through the logic network.

This requirement is independent of system clock;

manufacturer’s minimum delay specifications are needed.

Guarantee that minimum combinational logic delay is larger than hold time. Race margin:

 t_hold < t_c-q,cd + t_logic,cd

Clock Uncertainties

2 4

3 Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines Devices

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Clock Nonidealities

 Clock Skew

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Spatial variations in equivalent clock edges

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Mostly deterministic

 Clock Jitter

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Temporal variations in consecutive clock edges

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Mostly random

 Pulse Width Variation

Clock Skew and Clock Jitter

Clk

t_SK

t_JS

 Clock skew and jitter can affect the cycle times

 Clock skew can cause race conditions

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Overview

 Sequential system timing requirements

 Impact of clock skew on timing

 Impact of clock jitter on timing

 Clock distribution

Clock Skew

Bad design

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Clock Skew

R1

D Q Combinational Logic In

CLK t_CLK1

R2 D Q

t_CLK2 t_c_{- q}

t_c_{- q, cd} t_su, t_hold

t_logic t_{logic, cd}

 Assume the following timing parameters are available:

 Contamination or minimum delay (t_c-q,cd) and maximum propagation delay (t_c-q) of the register

 Setup (t_su) and Hold (t_hold) times for registers

 Contamination delay (t_logic,cd) and maximum delay (t_logic) of the combinational logic

 The positions of the rising edges of clocks CLK1 and CLK2 (t_CLK1 and t_CLK2) relative to a global reference. Ideally t_CLK1 = t_CLK2.

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Positive Clock Skew

 Launching edge arrives before the receiving edge

 Minimum clock cycle:

T+ t_c-q + t_logic + t_su

R1

CLK t_CLK1

R2 D Q

t_CLK2 t_c_{- q}

t_c_{- q, cd} t_su, t_hold

t_logic t_{logic, cd}

Negative Clock Skew

 Receiving edge arrives before the launching edge

 Minimum clock cycle:

T+ t_c-q + t_logic + t_su

R1

CLK t _CLK1

R2 D Q

t _CLK2 t _{c - q}

t _{c - q, cd} t _su, t _hold

t _logic t _{logic, cd}

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Positive and Negative Clock Skew

Impact of Clock Skew on Timing:

Cycle Time (Long Path)

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Impact of Clock Skew on Timing:

Race Margin (Short Path)

Overview

 Sequential system timing requirements

 Impact of clock skew on timing

 Impact of clock jitter on timing

 Clock distribution

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Clock Jitter

CLK

-t_jitter

T_{C LK}

t_jitter

CLK

In Combinational

Logic t_c-q, t_{c-q, cd} t_{log ic}

t_{log ic, cd} t_su,t_hold

REGS

t_jitter





 





T

_CLK

- 2t

_jitter

 t

_c-q

+ t

_logic

+ t

_su

2t

_jitter

+ t

_hold

< t

_c-q,cd

+ t

_logic,cd

Impact of Clock Jitter on Timing:

Cycle Time (Late-Early Problem)

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Impact of Clock Jitter on Timing

Impact of Clock Skew and Jitter:

Cycle Time (Late-Early Problem)

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Impact of Clock Skew and Jitter:

Race Margin (Early-Late Problem)

Combined Impact of Clock Skew and Jitter

 Minimum clock cycle (cycle time)

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T_CLK > t_c-q + t_logic + t_su -  + 2t_jitter

 Positive skew improves performance

 Negative skew reduces performance

 Jitter reduces performance

 Minimum logic delay (race)

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t_logic,cd + t_c-q,cd > t_hold+  + 2t_jitter

 Skew reduces race margin

 Jitter reduces acceptable skew

 Notes:

 Absolute delay through a clock distribution path is not important

 What matters is the relative arrival time at the register points at the end of each path

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Overview

 Sequential system timing requirements

 Impact of clock skew on timing

 Impact of clock jitter on timing

 Clock distribution

Dealing with Clock Skew and Jitter

 Balance clock paths (tree distribution)

 Don’t use gated clocks

 Use negative skew to eliminate race conditions (at the cost of performance):

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Add up the components that result in the time budget - the period must be greater than this value

-  ( <0)

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Clock Distribution

 Distribute clock in a tree fashion

 H-Tree

CLK

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More Realistic H-Trees

Example: EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS

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Spartan-6 FPGA

Spartan-6 FPGA Global Clock Network

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Spartan-6 FPGA I/O Clock Network

Spartan-6 FPGA Clock Management Tile (CMT)

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Digital Clock Manager (DCM)

Eliminating Clock Skew

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Eliminating Clock Skew

Quadrant Phase Shifting

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Fine Phase Shifting

Summary

 Clock skew and clock jitter – increasingly important issues with technology downscaling

 CAD tools (e.g., ISE WebPack) take care of

many issues automatically

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References and Credits

 Chapter 10 of:

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Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits, 2nd Edition, Prentice Hall, 2003.