Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

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ENEE244: Digital Logic Design

Design Example: Counters

• Counter:

a sequential circuit that repeats a specified sequence of output upon clock pulses.

– A,B,C,…, Z.

– G, O, T, E, R, P, S, !.

– 0,1,2,3,4,5,6,7.

– 7,6,5,4,3,2,1,0.

– 0,1,0,0,1,2,3,2,3,2,2,1.

• Binary counter:

follows the binary sequence.

– 2-bit (up) binary counter: 0,1,2,3.

– 3-bit down binary counter: 7,6,5,4,3,2,1,0

Design Example: Counters

• Other useful counters:

– Decimal counter (e.g. BCD counter)

0000,0001,0010,…,1000,1001,0000,0001,…

– Modulo-k counter

Modulo-5 counter: 0,1,2,3,4,0,1,2,…

– M-to-N counter

3-to-8 counter: 3,4,5,6,7,8,3,4,…

– Ripple counter

– Ring counter and Johnson counter

3-Bit Binary Counter

TC TB TA C B A C B A

1 1 1 0 0 0 1 1 1

1 0 0 1 1 1 0 1 1

1 1 0 0 1 1 1 0 1

1 0 0 1 0 1 0 0 1

1 1 1 0 0 1 1 1 0

1 0 0 1 1 0 0 1 0

1 1 0 0 1 0 1 0 0

1 0 0 1 0 0 0 0 0

current state next state flip-flop inputs

000 001 010 011

111 110 101 100

0 1 1

1 0 1

1 1 0

0 0 0

T Q(t+1) Q(t)

3-Bit Binary Counter

• Flip-flop input functions

– TA = BC

– TB = C

– TC = 1 _{T Q}

>

A T Q

>

B T Q

>

C

0 0 0

CP 1

• Figure 6.32 gives a 4-bit binary counter. When Q₀=C, Q₁=B, Q₂=A, delete Q₃, set Count enable bit to be constant 1, it becomes this 3-bit counter.

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Binary Counter with JK Flip-Flops

J

>

K Q Q’

A₁

J

>

K Q Q’

A₂

J

>

K Q Q’

A₃

J

>

K Q Q’

A₄ CP

E

0 x 1 1

1 x 0 1

x 1 1 0

x 0 0 0

K J Q(t+1) Q(t)

1 0 0 1

0 0 0 1

1 1 1 0

0 1 1 0

1 0 1 0

0 0 1 0

1 1 0 0

0 1 0 0

1 0 0 0

0 0 0 0

A1

A2

A3

A4

… … … …

• when E = 1 and CP goes from 0 to 1:

– A₁ – A₂ – A₃ – A₄

• Exercise:

Verify that the circuit is a binary counter that counts down from 15 to 0, and then back to 15 again.

J

>

K Q Q’

A₁

J

>

K Q Q’

A₂

J

>

K Q Q’

A₃

J

>

K Q Q’

A₄ CP

E

0 1 1 0

1 1 1 0

0 0 0 1

1 0 0 1

0 1 0 1

1 1 0 1

0 0 1 1

1 0 1 1

0 1 1 1

1 1 1 1

A1

A2

A3

A4

… … … …

Count-Down Binary Counter

Summary

• Sequential circuit design example

– Shift registers

– Basic counters

• Next time

– Binary counter with parallel load – Ripple counter

– Johnson counter

• Next Monday: Exam IV

– PLD, Chapter 6, 7.1, 7.2

– Discussion on Wednesday’s class

Binary Counter with Parallel Load

• 2 control signals, 3 modes:

– Load (Q_i=D_i) Load = 1

– Count (up) Load = 0, Count = 1 – No change Load = 0, Count = 0 (change, load or count, happens only at

positive edge of the clock pulse.)

• Carry Out: 1 if and only if the counter is in “count” mode with content 1111.

• Read Figure 6.34 for the detailed implementation.

4-bit count D₁ D2

D₃ D0

Load Count

Q1

Q₂ Q3

Q0

CO

>

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Modulo-7 Counter

4-bit count D₁ D2

D3

D0

Load Count

Q1

Q2

Q₃ Q0

CO

>

0 1 2 3 4 5 6 7

15 14 13 12 11 10 9 8 load

modulo-16

0 1 2 3 4 5 6 7

15 14 13 12 11 10 9 8 load

modulo-7 (when to load)

0 0 0 0

1

3-To-8 Counter

4-bit count D₁ D₂ D3

D₀

Load Count

Q₁ Q2

Q₃ Q0

CO

>

0 1 2 3 4 5 6 7

15 14 13 12 11 10 9 8 load

modulo-16

3-to-8 (when and what to load)

0 1 2 3 4 5 6 7

15 14 13 12 11 10 9 8 load 0

0 1 1

1

Design Example

8-bit counter with two 4-bit counters

4-bit count D₁ D2

D₃ D0

Load Count

Q1

Q₂ Q3

Q0

CO

>

4-bit count D1

D2

D₃ D₀

Load Count

Q₁ Q₂ Q3

Q₀

CO

>

Q₁ Q₂ Q3

Q₀

Q5

Q₆ Q7

Q4

0 0

1

Exam IV

• PLD

• Timing diagram for basic latch/flip-flop

• Sequential circuit analysis

• Sequential circuit design

• Registers and counters

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Ripple Counter

• Synchronous counter:

the CP signal of all flip- flops are from the common clock.

• Ripple counter:

the CP of some flip-flops are from other flip-flops (and through logic gates).

– Ripple counter is asynchronous

– Binary ripple (up) counter (read Figure 6.31) – Binary ripple down counter

– Where the CP signal comes from? (By default, flip-flop is positive edge triggered.)

BCD Ripple Counter

• Verify the following circuit is a BCD Ripple counter triggered by negative edge.

J

>

K Q Q’

Q₁

CP J

>

K Q Q’

J

>

K Q Q’

J

>

K Q Q’

Q₂ Q₄ Q₈

1

BCD Ripple Counter

• Verify the following circuit is a BCD Ripple counter triggered by negative edge.

CP

Q₁ ⁰ ¹ ⁰ ¹ ⁰ ¹ ⁰ ¹ ⁰ ¹ ⁰ ¹

Q₂

Q₄

Q₈

0 0 1 1 0 0 1 1 0 0 0 0

0 0 0 0 1 1 1 1 0 0 0 0

0 0 0 0 0 0 0 0 1 1 0 0

Ring Counter

• Ring counter:

a circular shift register (with k flip- flops) that at any time, only one flip-flop is set (having value 1) and all others are cleared (with value 0). It is used to generate k (periodic) timing signals.

• Example: see Figure 6.37 for circuit.

CP Q_A

Q_D

Q_C

Q_B

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Ring Counter as “Counter + Decoder”

• To generate 4 (periodic) timing signals, we need

– a 4-bit ring counter, – or a 2-bit counter

and a 2x4 decoder.

CP

Count Load

2-bit count

0 0

1

2 x 4 decoder

2 0

3 1

Q_DQ_CQ_BQ_A

CO

Johnson Counter

• Johnson counter:

a k-bit circular shift register with the complement of the last flip-flop connected to the input of the first flip-flop, and 2k decoding gates. It is used to generate 2k (periodic) timing signals.

D Q

>

S₃ D Q

>

S₂ D Q

>

S₁

0 0 0

CP

Q’

6 AND gates for decoding

Johnson Counter

1 1

0 0 6

1 1

1 0 5

1 1

1 1 4

1 0

1 1 3

1 0 0 1 2

1 0 0 0 1

T₆ T₅ T₄ T₃ T₂ T₁ S₁ S₂ S₃

AND gate for output

T₆= S₂’S₁ T₅= S₃’S₂ T₄= S₃S₁ T₃= S₂S₁’ T₂= S₃S₂’ T₁= S₃’S₁’

states

6 AND gates for decoding

S₃ S₂ S₁

D Q

>

S₃ D Q

>

S₂ D Q

>

S₁

0 0 0

CP

Q’