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Asymmetric Junctionless Double Gate (JLDG) Silicon on Nothing (SON) MOSFET Modified with the Concept of
Work Function Engineering: A Comparative Performance Study
Priyanka Saha1*, Dinesh Kumar Dash2, Subhramita Basak3, Subir Kumar Sarkar4
Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, West Bengal, India
[email protected], [email protected], [email protected] and [email protected]
Abstract: An analytical compact model for asymmetric junctionless double gate silicon-on-nothing (JLDG SON) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is developed here. This model is developed based on the solution of 2D Poisson’s equation considering different dielectric medium, dielectric thickness of both front and back gates in addition to different applied gate voltages. This model is then further extended to develop a modified structure incorporating work function engineering with linearly graded binary metal alloy gate electrode to further suppress SCEs. Our analytical results found to be in good agreement with simulation results, thereby fulfilling the accuracy of the present analytical model.
Keywords: Junctionless; double gate; silicon on nothing (SON); threshold voltage roll-off; drain induced barrier lowering; subthreshold swing, work function engineering.
1 INTRODUCTION
Among the Silicon-On-Insulator (SOI) devices, Double gate MOSFET using ultra-thin silicon layers is considered the most attractive device to replace the scaling limitations of bulk and single gate SOI MOSFETs. Moreover to avoid the scaling difficulties associated with the sharply
defined source/drain junctions, junctionless transistors (JLTs) have also been investigated [1, 2]. Junctionless transistors are devices with constant doping concentration from source to drain with no doping gradients. JLTs show better SCE immunity, lower leakage current with no requirement of expensive doping techniques and
ultra-fast annealing methods. Compact threshold voltage model of symmetric JLDGSOI MOSFET [3] and for JLDG-Silicon On Nothing (SON) by replacing buried oxide (BOX) layer with air [4] for further reduction in circuit delay have been proposed. Again asymmetry in a DG-MOSFET (ADG) structure can be brought about by applying different gate biases independently and different gate oxide thicknesses for front and back gates. In this paper we have included the influence of using air as the back gate dielectric and oxide as the front gate dielectric and extended to workfunction engineered (WFE) DGSON for both front and back gate electrodes having mole fraction variation from source end (100% P) to drain end (100% Q). The concept of work function engineered gate (WFEG) MOSFET has already been reported in literature [5, 6]. Platinum and Titanium with pure constituent work function of 5.3eV and 4.4eV are used with air and oxide as the back and front gate dielectric respectively.The continuous work function variation minimizes asymmetry in surface potential profile and modifies the vertical field which in turn improves DIBL effect to a significant amount.
2 DEVICE STRUCTURE AND MODEL DERIVATION
The schematic view of N-channel JLDG SON MOSFET with homogeneously doped channel, source and drain is illustrated in figure 1, depicting the silicon film thickness (tsi), front gate oxide thickness (tox), back gate air thickness (tair) and uniform doping concentration (ND). In junctionless devices, the channel needs to be fully depleted for bringing the device in off state.The increasing gate biasing is required to fully deplete the electrons in an N-channel junctionless MOSFET and the channel will become completely unbiased when the applying gate voltage is just same as the flatband voltage. The electrons will flow in the entire volume of the body which is different from the surface conduction of junction-based structure.
This volume current actually contributes to the total current of the JL devices [7-9].Before proceeding towards analytical calculation, the channel is assumed to be wholly depleted. 2D Poisson’s equation applied to the entire region of the fully depleted silicon body of N-channel JLDG-SON MOSFET can be written as [3],
2 2
2 2
( , ) ( , )
for (0 ),( / 2 / 2)
D Si
Si Si
qN
x y x y
x y
x L t y t
(1)
Fig. 1. Cross sectional view of N-channel JLDG SON MOSFET
Where ( , )x y denotes the two dimensional silicon channel potential, q is the charge of a single electron, NDis the N-channel doping concentration supposed to be uniform and Si indicates the dielectric constant of the Si channel. The channel potential distribution is considered parabolic in nature along the perpendicular direction of the channel and the expression is as follows,
1 2 3 2
( , )x y K x K x y K x y( ) ( ) ( )
(2)
With the continuity of potential distribution along the channel, the applied boundary conditions are described below [10]:
1) The central potential distribution Фc(x) is a function of x only.
( , 0 )x K x1( ) C( )x
(3)
2) The derivation of front surface potential,
f( )x
at
2si
y t is deduced by the front gate oxide thickness (tox):
1 2
( ) ( )
( , )
si
f gs fb
ox
t si ox
y
x V V x x y
y t
(4)
3) The derivation of back surface potential, b( )x
at 2si
y t is deduced by the back gate air thickness (tair).
2 2
( ) ( )
( , )
si
b gs fb
air
t si air
y
x V V x x y
y t
(5)
here Vfb(x) denotes the flatband voltage at both front and back gate interface and is determined by
( ) ( )
fb Meff Si
V x x .The effective work function (ФMeff) of a binary metal alloy can be approximated in terms of individual work functions of two pure metals, Фxand Фy, as
( ) (1 )
Meff x x y x x
(6) Front and back potentials are obtained by placing y=tsi/2 and y=-tsi/2 in (2) and front surface potential is expressed as:
2 2
2
( ) ( )3
8 4
( ) 8 3 3
8 4
ox si ox air air si
c gs fb
si air si
f
si si air si ox ox air
si air si
C C C C C C x V V
C C C
x C C C C C C C
C C C
(7)
The central potential can be expressed in terms of front surface potential also. The central surface potential of our proposed structure is found to be:
2 2
( ) ( )
C x c c x cx c
x
(8)
where,
2 2
1 , y x and D gs Si
c c c c c x
c Si c
qN V
L
2
2 2
8 ( ) 8
1
(8 si air ox 3 air ox si3 )
c si si si air ox ox si air si
C C C C C C t C C C C C C C
2
1 2
2
2 2
4 8
.8 ( ) 8
4 8
.
8 ( ) 8
ox air Si ox Si gs
si air ox air ox si
ox air Si air Si gs
si air ox air ox si
C C C C C Vgs V
C C C C C C C C C C C V C C C C C C
Cair, Cox and Csi are silicon, front and back oxide capacitance. The solution of (8) is given below:
1 1
( ) cx cx c c
c
c c
x ae be x
(9) Using boundary conditions:
(0,0) 0
C andC( ,0)L Vds
a and b can be portrayed as,
1 gs 2
a CV C
3 gs 4
b C V C
where 1 / 1
2sinh( / )
L c c
C e
L
(10)
/ 2
( )( 1)
2sinh( / )
D L
ds x Si
Si
qN
V L e
C L
(11)
/
3 1
2sinh( / )
L c c
C e
L
(12)
/ 4
( )(1 )
2sinh( / )
D L
ds x Si
Si
qN
V L e
C L
(13)
Again, by assigning zero to differentiated central potential expression, we can obtain the minimum point of x (xcmin), at which c( )x will attain the least value and they are described as,
min min
2 2 2 min
min min
ln 4 and
2
c c
c
x x
c c
x ab
a ae be x
(14)
By applying zero to this above equation and solving for Vgs, the short channel threshold voltage expression is calculated.
3 RESULTS AND DISCUSSIONS
The performance of our aimed device structure has been examined thoroughly in this section through the 2-D analytical and simulated results of the proposed model in terms of channel potential distribution, threshold voltage roll-off (TVRO), drain induced barrier lowering (DIBL) and subthreshold swing(SS). The plots also include the long channel and short channel behavior of the
WFE-JLDG SON taking L=15nm, 40nm and 100nm respectively with varying drain to source biases.
The surface potential for different gate biases and central potential varying Vds are studied in fig.2 and 3.Figures 4 sketch the threshold voltage roll- off (TVRO) variation with different gate dielectric thicknesses for WFE-JLDG SOI/SON.WFE-SOI provides better results than WFE- SON [6] as SON is more immune to SCEs than SOI structure.
Fig. 5 frames the change in DIBL with L for different high drain biases (Vdsh) while keeping low drain bias (Vdsl) fixed to 0.1 V. Figure 6 explicitly shows the deviation of subthreshold slope (swing) with channel length. The subthreshold swing can be calculated
using,
1
ln(10) f,min gs
KT d
ss q dV
. WFE
DGJLSON will undoubtedly exhibit more promising short channel behaviour because of its smallest subthreshold swing (SS).
Fig. 2. Analysis of potential distributions of our proposed model for WFE-JLDG SON with different gate biases.
Fig. 3. Central potential distribution with respect to position along the channel for WFE-JLDG SON at different channel
lengths and varying Vds.
Fig. 4. Vthroll-off variation versus channel length for different gate dielectric thicknesses while keeping Vds= 0.1 V.
Fig. 5. DIBL variation versus channel length for two different drain biases of different device structures.
Fig. 6. Subthreshold swing (SS) dependence on position of channel length, L for JLDG SOI, JLDG SON, WFE DGJL SOI
and WFE DGJL SON.
4 CONCLUSION
The presented mathematical model establishes the advantageous features of asymmetric WFE-DGJL SON structure. It is found to be more immune to short channel effects compared to WFE-DGJL SOI MOSFET. Its improved performance in terms of DIBL, subthreshold swing and threshold voltage roll off can prove it to be a promising technology for future VLSI technology. Moreover, this model can also give the guidance for designing the JLDG
SON MOSFET and it can be quite acceptable to the designers due its computational efficiency.
ACKNOWLEDGMENT
PriyankaSaha thankfully acknowledges the financial support as PhD fellow under
“Visvesvaraya PhD Scheme”,Deit Y,Government of India.
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