EE 330 Lecture 41. Digital Circuits. Propagation Delay With Multiple Levels of Logic Optimally driving large capacitive loads

EE 330

Lecture 41

Digital Circuits

Device Sizing

Multiple Input Gates: 2-input NOR

DERIVATIONS

W_n=?

W_p=?

Equal Worst Case Rise/Fall (and equal to that of ref inverter when driving C_REF)

Input capacitance = ?

FI=?

t_PROP=? (worst case)

(n-channel devices sized same, p-channel devices sized the same) Assume L_n=L_p=Lmin and driving a load of C_REF

A B C VDD CREF W_n=W_MIN W_p=6W_MIN

INA INB OX MIN MIN OX MIN MIN OX MIN MIN OX MIN MIN REF

7 7 C =C =C W L +6C W L =7C W L = 4C W L = C 4 4             REF 7 7 FI= C FI= 4 or 4      

t_PROP = t_REF (worst case)

Recall:

One degree of freedom was used to satisfy the constraint indicated

Other degree of freedom was used to achieve equal rise and fall times

Overdrive Factors

VIN VOUT M1 M2 VDD

Scaling widths of ALL devices by constant (W_scaled=WxOD) will change “drive” capability relative to that of the reference inverter but not change relative value of t_HL and t_LH

1  PD n OX 1 DD Tn L R = μ C W V -V    1 PD PDOD n OX 1 DD Tn L R R = μ C OD W V -V OD   IN OX 1 1 2 2 C =C W L +W L  2   PU PUOD p OX 2 DD Tp R L R = OD μ C OD W V +V 

Scaling widths of ALL devices by constant will change FI by OD

2  PU p OX 2 DD Tp L R = μ C W V +V



 







INOD OX 1 1 2 2 IN C =C O D W L + O D W L  O D C

Propagation Delay with Over-drive Capability

CL=900CREF VIN VOUT Example CL=900CREF VIN 900 VOUT CL=900CREF VIN 30 VOUT

Compare the propagation delays. Assume the OD is 900 in the third case and 30 in the fourth case. Don’t worry about the extra inversion at this time.





PROP REF REF REF

t

=t

900t

901t





PROP REF REF REF

t

=900t

t

901t





PROP REF REF REF

t

=30t

30t

60t

Note: Dramatic reduction in t_PROP is possible

Will later determine what optimal number of stages and sizing is

CL=900CREF

VIN VOUT

PROP REF

t

=900t

Propagation Delay in

Multiple-Levels of Logic with Stage Loading

G

₁

G

₂

G

₃

G

_n

A

F

OD1: FI2 OD2: FI3 OD3: FI4 ODn: FI(n+1)

FIk denotes the total loading on stage k which is

the sum of the FI of all loading on stage k

Summary: Propagation delay from A to F:

n I(k+1) PROP REF k=1 _k

F

t

=t

OD



Propagation Delay in

Multiple-Levels of Logic with Stage Loading

• Equal rise/fall (no overdrive)

• Equal rise/fall with overdrive • Minimum Sized

• Asymmetric Overdrive

• Combination of equal rise/fall,

minimum size and overdrive

Will consider an example with the five cases

Will develop the analysis methods as needed

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

C

L

V

IN

V

OUT PROP HL LH REF IL HL LH

1

1

1

t

=t +t = t

F

+

2

OD

OD













Asymmetric Overdrive G1 G2 G3 Gn A F OD_HL1 OD_LH1 F_I2

FIk denotes the total loading on stage k which is the sum of the FI of all loading on stage k

OD_HL2 OD_LH2 F_I3 ODHL3 ODLH3 FI4 OD_HLn OD_LHn F_I(n+1)

When propagating through n stages:

1 1  _{ }  _{ }  _   



 n

PROP REF I(k+1)

k=1 HLk LHk 1 t t F 2 OD OD

C

_L

V

_IN Gate

V

OUT

Propagation Delay in Multiple-Levels of

Logic with Stage Loading and Overdrives

A

F 50fF 20fF

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

A F 50fF 20fF REF REF HL t =2t k+1 n PROP REF I k=1 t =t



F

Equal rise-fall gates, no overdrive

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

Equal rise-fall gates, no overdrive

A

F

50fF

20fF



k+1 5 PROP REF I k=1 t =t F

Equal rise-fall gates, no overdrive

3 1 4 13 4 k  _ 3 1 4 10 4 k  _ 3 7 4 1 4 k  _ 3 1 4 10 4 k  _ 3 7 4 1 4 k  _ 3 5 4 4 k  _

In 0.5u proc tREF=20ps,

C_REF=4fF,R_PDREF=2.5K 20fF =5 4fF REF C C  50fF =12.5 4fF REF C C  1 1 F_I2=10.25 F_I3=4.25 F_I4=4.25 F_I5=1.25 F_I6=12.5 10.254.254.25 1.25 12.5   PROP REF t =t PROP REF

t

=32.5t

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

A F 4 4 6 8 20fF 50fF 5

Equal rise-fall gates, with overdrive

k+1 n I PROP REF k=1 F t =t OD_k



In 0.5u proc t_REF=20ps, CREF=4fF,RPDREF=2.5K

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

Equal rise-fall gates, with overdrive

A

F

4 4 6 8

20fF

50fF

5

Equal rise-fall gates, with overdrive

k+1 n I PROP REF k=1 F t =t OD_k



3 3 4 1 4 1 OD k _{ } 20fF =5 4fF REF C C  OD5 1 3 0 4 1 4 1 OD k _{ } 3 1 2 1 4 2 OD k _{ } 3 1 4 7 4 OD k    3 0 4 1 4 1 OD k _{ } 3 0 4 4 2 OD k _  _ 50fF =12.5 4fF REF C C 

In 0.5u proc t_REF=20ps, CREF=4fF,RPDREF=2.5K F_I2=14.25 F_I3=13 F_I4=4.25 F_I5=5 F_I6=12.5 PROP REF 14.25 13 4.25 5 12.5 t =t + + + + 8 1 6 1 4       PROP REF t =23.6 t

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

A F 20fF 50fF ?  PROP REF t = t Minimum-sized gates

In 0.5u proc t_REF=20ps, CREF=4fF,RPDREF=2.5K

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

A F M M M M M M M M M M M M M M M 20fF 50fF ?  PROP REF t = t Minimum-sized gates

Propagation Delay with Minimum-Sized Gates

G A _F CL 1 1     _{ }  _   



 n

PROP REF I(k+1)

k=1 _{HLk LHk}

1

t t F

2 OD OD

• Still need OD_HL and OD_LH for minimum-sized gates

• Still need F_I

Recall:

M

A

_F

Propagation Delay with minimum-sized gates

VOUT VDD A1 A2 Ak A1 A2 Ak M11 M12 M1k M21 M22 M2k VOUT M1k M21 VDD A1 A2 Ak M22 M2k A1 A2 Ak M2k M1k HL OD =1 OD_LH= 1 3k ODHL=1/k OD_LH=1 3 HL OD =? ODLH=? OD_HL=? OD_LH=? OX MIN MIN FI=2C W L

REF OX _{MIN MIN}

C =4C W L

REF

C FI=

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

A

F

M M M M M M M M M M M M M M M

20fF

50fF

Minimum-sized gates HL OD =1 HL OD =1 HL OD =1 LH OD =1/3 LH OD =1/3 HL 1 OD = = k 1/3 HL 1 OD = = k 1/2 LH 1 OD = = 3k 1/12 LH 1 OD = = 3k 1/6 LH 1 OD = = 3k 1/9 20fF =5 4fF REF C C  50fF =12.5 4fF REF C C  1/2 1/2 1/2 1/2 1/2 _1/2 1/2 1/2 1    _{ }  _   



 5

PROP REF I(k+1)

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

Propagation Delay in Multiple-Levels of Logic with

Stage Loading

Asymmetric-sized gates CIN/CREF Equal Rise/Fall Inverter NAND NOR 1 3k+1 4 3+k 4 Minimum Sized Overdrive HL LH 1 1 1/2 1/2 1/2 1 1/3 NOR NAND Inverter HL LH HL LH 1 1 1 1 1 1/(3k) 1/k 1/3 Equal Rise/Fall (with OD) OD 3k+1 OD 4  3+k OD 4  Asymmetric OD (ODHL, ODLH) HL LH OD +3 OD 4  OD OD OD OD OD OD HL LH OD +3k OD 4  HL LH k OD +3 OD 4   ODHL ODLH ODHL ODLH ODHL ODLH n I(k+1) k=1 k F OD n I(k+1) k=1 F _{ 1 }      n I(k+1) k=1 HLk LHk 1 1 F 2 OD OD tPROP/tREF _ 1  _   n I(k+1) k=1 HLk LHk 1 1 F 2 OD OD ODHL ODLH 1    _{ }  _      5 PROP REF I(k+1)

k=1 HLk LHk

1 1

t =t F

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

A F 4 2 4 2 4 2 1 1 1 1 1 1 1/2 1/4 1 1 4 1/4 1 2 2 1 1 2 1 2 1 2 20fF 50fF 1 2 Asymmetric-sized gates 1    _{ }  _   



 5

PROP REF I(k+1)

k=1 HLk LHk

1 1

t =t F

A

F

4 2 4 2 4 2 1 1 1 1 1 1 1/2 1/4 1 1 4 1/4 1 2 2 1 1 2 1 2 1 2 20fF 50fF 1 2 ?  PROP REF t = t Asymmetric-sized gates LH OD =2 HL OD =1 7/8 1 1 20fF =5 4fF REF C C  HL OD =1 2 LH OD =1/4 F_I2=63/8 7/4 11/2 F_I3=29/4 HL OD =1 LH OD =1 F_I4=77/16 HL OD =4 LH OD =1/4 25/16 LH OD =2 HL OD =4 50fF =12.5 4fF REF C C  F_I5=7/2 F_I6=12.5 1    _{ }  _   



 5

PROP REF I(k+1)

k=1 HLk LHk 1 1 t =t F 2 OD OD     63 1 29 77 7 1 1 1 1 2 4 1 1 4 12.5 8 2 4 16 2 4 2 4         _{ }  _     _  _ _  _         PROP REF 1 t =t 2  PROP REF t =44.6 t ODHL ODLH NOR: NAND: 7/2 13/4

(Note: This COX is somewhat larger

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

A F 8 6 M M 3 20fF 50fF 8 3 4 2

Mixture of Minimum-sized gates, equal rise/fall gates and OD

? 

PROP REF

Driving Notation

• Equal rise/fall (no overdrive)

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

A F 8 6 M M 3 20fF 50fF 8 3 4 2

Mixture of Minimum-sized gates, equal rise/fall gates and OD

1    _{ }  _      5 PROP REF I(k+1)

Propagation Delay in Multiple-Levels of

Logic with Stage Loading

Mixture of Minimum-sized gates, equal rise/fall gates and OD

1    _{ }  _      5 PROP REF I(k+1)

Propagation Delay in

Multiple-Levels of Logic with Stage Loading

n I(k+1) PROP REF k=1 k F t =t OD



• Equal rise/fall (no overdrive) • Equal rise/fall with overdrive • Minimum Sized

• Asymmetric overdrive

• Combination of equal rise/fall,

minimum size and overdrive

n PROP REF (k+1) k=1

t

=t



FI

G1 G2 G3 Gn A F FI2 FI3 FI4 FI(n+1) Gxx Gx2 Gx3 Gx4 1    _{ }  _   



 n

PROP REF I(k+1)

k=1 HLk LHk 1 1 t =t F 2 OD OD 1    _   _      n PROP REF I(k+1)

k=1 HLk LHk 1 1 t =t F 2 OD OD 1    _   _      n PROP REF I(k+1)

k=1 HLk LHk

1 1

t =t F

Driving Large Capacitive Loads

A F C_L Assume driving by a reference inverter Assume C_L=1000C_REF

In 0.5u proc t_REF=20ps, CREF=4fF,RPDREF=2.5K

Example

Driving Large Capacitive Loads

A F C_L Assume driving by a reference inverter Assume C_L=1000C_REF

In 0.5u proc t_REF=20ps, CREF=4fF,RPDREF=2.5K

Example

t_PROP=1000t_REF

Driving Large Capacitive Loads

A F

C_L

1000

Assume first stage is a reference inverter Example Assume C_L=1000C_REF t_PROP=?



2 I(k+1) PROP REF k=1 k F t =t OD





1 1 1000 1000 1000 1 1 1000  _  _{ }    

PROP REF REF

t =t t



1001





PROP REF

t t

Driving Large Capacitive Loads

A F

CL

10 100

Assume first stage is a reference inverter Example _{Assume C} L=1000CREF



3 I(k+1) PROP REF k=1 k F t =t OD





1 1 1 10 100 1000 10 10 10 1 10 100  _{ }  _{  }    

PROP REF REF

t =t t

PROP REF

t

= 30t

Dramatic reduction is propagation delay (over a factor of 30!)

Optimal Driving of Capacitive Loads

Assume first stage is a reference inverter

A F

CL

1 θ₁ θ₂ θn-2 θn-1

Need to determine the number of stages, n, and the OD factors for each stage to minimize t_PROP.

{θ

₁

, θ

₂

,...θ

_n-1

,n}

n k PROP REF k=1 _k-1

θ

t

=t

θ



n I(k+1) PROP REF k=1 k F t =t OD



where θ₀=1 , θ_n=C_L/C_REF

This becomes an n-parameter optimization (minimization) problem !

Unknown parameters:

Optimal Driving of Capacitive Loads

Assume first stage is a reference inverter A F CL 1 θ₁ θ₂ θn-2 θn-1 n k PROP REF k=1 _k-1

θ

t

=t

θ



This becomes a 2-parameter optimization (minimization) problem ! Unknown parameters:

Order reduction strategy : Assume overdrive of stages increases by the same factor clear until the load

A F CL 1 θ θ2 θn-1

n

REF

L

θ C

=C

 

θ,n

One constraint :

θ C

n

_REF

=C

_L

Optimal Driving of Capacitive Loads

k n PROP REF _k-1 k=1

θ

t

=t

θ



Unknown parameters: A F CL 1 θ θ2 θn-1

 

θ,n

n k PROP REF k=1 _k-1

θ

t

=t

θ



n REF L θ C =C PROP REF

t

=t

nθ

PROP REF

t

=t

nθ

n REF L

θ C

=C

n REF L

θ C

=C

 

C

_REFL

1

n=

ln

ln

θ

C













 

L PROP REF REF

C

θ

t

=t

ln

ln

θ

C













Optimal Driving of Capacitive Loads

A F CL 1 θ θ2 θn-1 n REF L θ C =C

 

L PROP REF REF

C

θ

t

=t

ln

ln

θ

C













Is suffices to minimize the function

 

Optimal Driving of Capacitive Loads

A F CL 1 θ θ2 θn-1 n REF L θ C =C

 

L PROP REF REF

C

θ

t

=t

ln

ln

θ

C













OPT

θ

= e

L OPT REF

C

n

ln

C





 





















L

PROP REF REF

REF

C

t

= t

e ln

nθt

Optimal Driving of Capacitive Loads

θ

2 e 3

e

• minimum at θ=e but shallow inflection point for 2<θ<3

 

θ

f=

ln

θ

• practically pick θ=2, θ=2.5, or θ=3

• since optimization may provide non-integer for n, must

Optimal Driving of Capacitive Loads

A F

CL

1 θ θ2 θn-1

n-stage pad driver

• Often termed a pad driver

• Often used to drive large internal busses as well • Generally included in standard cells or in cell library • Device sizes can become very large

• Odd number of stages will cause signal inversion but

Optimal Driving of Capacitive Loads

A F

CL

1 θ θ2 θn-1

n-stage pad driver

Example: Design a pad driver for driving a load capacitance of 10pF, determine t_PROP for the pad driver, and compare this with the propagation delay for driving the pad with a minimum-sized

reference inverter._{In 0.5u proc t}

Optimal Driving of Capacitive Loads

A F

CL

1 θ θ2 θn-1

n-stage pad driver

Example: Design a pad driver for driving a load capacitance of 10pF, determine t_PROP for the pad driver, and compare this with the propagation delay for driving the pad with a minimum-sized

reference inverter. _{In 0.5u proc t}

REF=20ps,

CREF=4fF,RPDREF=2.5K W_nk=2.5k-1, W_pk  3 2.5k-1

L_n=L_p=L_MIN

Optimal Driving of Capacitive Loads

A F

CL

1 θ θ2 θn-1

n-stage pad driver

Example: Design a pad driver for driving a load capacitance of 10pF, determine t_PROP for the pad driver, and compare this with the propagation delay for driving the pad with a minimum-sized

reference inverter._{In 0.5u proc t}

REF=20ps, CREF=4fF,RPDREF=2.5K , 3 k-1 k-1 nk pk W =2.5 W  2.5

PROP REF REF REF

t



nθt

=8•2.5•t

=20t

1 17.5 2500 21.6 610 7 L

PROP REF 7 REF REF

Optimal Driving of Capacitive Loads

A F

CL

1 θ θ2 θn-1

n-stage pad driver

Example: Design a pad driver for driving a load capacitance of 10pF, determine t_PROP for the pad driver, and compare this with the propagation delay for driving the pad with a minimum-sized

reference inverter._{In 0.5u proc t}

REF=20ps, CREF=4fF,RPDREF=2.5K , 3 k-1 k-1 nk pk W =2.5 W  2.5

If driven directly with the minimum-sized reference inverter

L

PROP REF REF

REF

C

t =t =2500t

C

Note an improvement in speed by a factor of

2500

125 20

Optimal Driving of Capacitive Loads

A F

CL

1 θ θ2 θn-1

n-stage pad driver

Example: Design a pad driver for driving a load capacitance of 10pF, determine t_PROP for the pad driver, and compare this with the propagation delay for driving the pad with a minimum-sized

reference inverter. _{In 0.5u proc t}

REF=20ps,

CREF=4fF,RPDREF=2.5K W_nk=2.5k-1, W_pk  3 2.5k-1

L_n=L_p=L_MIN

Pad Driver Size Implications

A F

CL

1 θ θ2 θn-1

n-stage pad driver

1 2

3

4 5