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A method for the suppression of fluctuations in the neutral point potential of a three level NPC inverter with a capacitor voltage loop

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Figure

Fig. 1.  Topology of three-level NPC inverter.
Fig. 2  Charging or discharging state of Ccap2 by NP current in under basic carrier-based PD PWM method during a fundamental period
Fig. 4, i.e. it is inversely proportional to the fundamental frequency. 70
Fig. 6  Comparison of fluctuation amplitudes of capacitor voltages with different load power factors (m=1, Zphase6.8 , and f=50Hz)
+6

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