course230B4

MOSFET Scaling

Device scaling: Simplified design goals/guidelines for shrinking device dimensions to achieve density and performance gains, and power

reduction in VLSI. reduction in VLSI.

Issues: Short-channel effect, Power density, Switching delay, Reliability.

The principle of constant-field scaling lies in scaling the

device voltages and the device dimensions (both horizontal and vertical) by the same factor

κ

(

>

1) such that the electric and vertical) by the same factor,

κ

(

>

1), such that the electric field remains unchanged.

Rules of Constant Field Scaling

MOSFET Device and Circuit Parameters Multiplicative _{Factor (κ > 1)} Scaling Device dimensions (t L W x_j) 1/κ Scaling assumptions Device dimensions (t_ox, L, W, x_j) Doping concentration (N_a, N_d) Voltage (V) 1/κ κ 1/κ Derived scalingg Electric field (E) 1 behavior of device

parameters

( ) Carrier velocity (v)

Depletion layer width (W_d) Capacitance (C = εA/t)

1 1/κ 1/κ Inversion layer charge density (Q_i)

Current, drift (I)

Channel resistance (R_ch) 1 1/κ 1 D i d li Ci it d l ti ( CV/I) 1/ Derived scaling behavior of circuit parameters

Circuit delay time (τ ∼ CV/I)

Power dissipation per circuit (P ∼ VI) Power-delay product per circuit (P×τ) Circuit density (∝1/A)

1/κ 1/κ2

1/κ3

κ2

Circuit density ( 1/A) Power density (P/A)

κ

Scaling of Depletion Width

W V qN D si bi dd a = 2ε ψ( + )

Maximum drain depletion width: For N →

κN and V

→ V /

κ

For N_a →

κN

_a and V_dd → V_dd/

κ

, W_D → W_D/

κ

if V_dd >>

ψ

_bi. W qN S si bi a = 2ε ψ

However, the source depletion width,

is indep. of Vp _dddd and only scales as y W_SS→ W_SS/ κ .

Furthermore, the maximum gate depletion width,

scales even less than 1/

W kT N n q N dm si a i a 0 2 4 = ε ln( / )

Generalized Scaling

Allows electric field to scale up by

α

(E →

α

E) while the device dimensions scale down by

κ

,

i e voltage scales by / (V → ( / )V) i.e., voltage scales by

α

/

κ

(V → (

α

/

κ

)V). More flexible than constant-field scaling, but has reliability and power concerns but has reliability and power concerns.

To keep Poisson’s equation invariant under the p q

transformation, (x,y) → (x,y)/

κ

and

ψ

→

ψ

/(

κ

/

α

) within the depletion region: ∂ αψ κ2 ∂ αψ κ2 ( / ) ( / ) qN_a N_a should be scaled to (

ακ

)N_a. ψ ∂ κ ψ ∂ κ ε 2 2 ( ) ( / ) ( ) ( / ) x y q _a si + =

Constant Voltage Scaling

Special case of

α

=

κ

in generalized scaling:

The only mathematically correct scaling as far as 2D Poisson eq. and boundary conditions are concerned.

N_a →

κ

2_N a,

th f th i d l ti idth W 0 4εsikTln(Na / ni) therefore, the maximum depletion width,

scales down by

κ

.

Both the short channel V roll off

W q N dm si a i a 0 2 = ( ) ΔV tox V e L Wdm tox = 24 + − + 2 3 ψ ψ π ( ) / Both the short-channel V_t roll-off,

and the threshold voltage,

ΔV W V e t dm bi bi ds = ψ ψ( + ) V V qN V C t fb B si a B bs ox = +2ψ + 2ε (2ψ + )

remain unchanged for constant-voltage scaling.

However, it is physically incorrect since, p y y

Scaling in Practice

CMOS VLSI t

h

l

ti

CMOS VLSI technology generations

Feature Size Power Supply

Gate Oxide _{Oxide Field} 2 μm 1.2 μm 0 8 μm 5 V 5 V 5 V 350 Å 250 Å 180 Å 1.4 MV/cm 2.0 MV/cm 2 8 MV/cm 0.8 μm 0.5 μm 0.35 μm 5 V 3.3 V 3.3 V 180 Å 120 Å 100 Å Å 2.8 MV/cm 2.8 MV/cm 3.3 MV/cm 0.25 μm 2.5 V 70 Å 3.6 MV/cm

CMOS technology has gone through mixed steps of constant voltage and constant field scaling As a result field and power

voltage and constant field scaling. As a result, field and power density have gone up, but performance gains have been

maintained and power per circuit has come down.

Fortunately, by physics or by learning, we managed to cope with y, y p y y g, g p reliability requirements at higher fields.

Non-Scaling Factors

Primary nonscaling factors:

¾ Built-in potential

u t

pote t a

ψ

ψ

_bibi

(Si bandgap)

(S ba dgap)

¾ Subthreshold current (thermal energy kT/q)

500 1000 Electron E_eff-0.3 t =35 Å t =70 Å ox ox Secondary nonscaling

factors (due to higher E):

100 200 300 ( c m /V -s ) Hole 2 µ eff E_eff-0.3 E_eff-2 ‰ Velocity saturation ‰ Decreased mobility at higher fields 0.1 0.2 0.3 0.5 1 2 3 30 50 0.1 µm CMOS 1 µm CMOS µ E_eff-1 higher fields ‰ Oxide reliability (t_ox

scales less, W_dm more)

(MV/cm)

Other Non-Scaling Factors

¾ Source and drain series resistance

• Doping level limited by solid solubility

p g

y

y

and is not scalable.

• Doping gradient or junction

abruptness limited by annealing

abruptness limited by annealing

process.

¾ Polysilicon gate depletion

¾ Polysilicon gate depletion

¾ Inversion layer depth/thickness

¾ Various process tolerances

¾ Various process tolerances

• Gate length.

• Gate oxide thickness.

MOSFET Threshold Voltage

(

)

I C W L m kT q e e ds eff ox q Vg Vt mkT qVds kT = − ⎛ ⎝ ⎜ ⎞ ⎠ ⎟ − − − μ ( 1) ( ) / 1 / 2 Subthreshold: 1E-4 1E-3 0 8 1 (A/ µ m ) m A/ µ m ) Log 2 , ( 1) ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − = m kT L W C I_dsVt μ_{eff ox} mkT qV Vt ds off t e I I = _, − / 1E-5 1E-4 0.6 0.8 n Cu rre n t ( Cu rren t ( m Slope g scale

increases with the technology node. , ⎟ ⎠ ⎜ ⎝ q L ox eff Vt ds 1E-7 1E-6 0.2 0.4 u rce-Drai n rce -Dr a in Slope ~q/kT V_t Linear scale gy I_ds,Vt ≈ 1 μA/μm for 0.1 μm nMOSFET. 0 0.2 0.4 0.6 0.8 1 1.2 1E-8 0 Gate Voltage (V) So u Sou r Need V_t > 0.2 V for I_off < 10 nA in logic circ its circuits.

CMOS Circuit Delay

Propagation delay dd ds dd gs V V V V ds on

I

I

=

_{= =} , 1 d ) on ds

_I

dt

dV

C

=

−

0 6 0.8 y (norm alize d 0.1 μm CMOS V = 1.5 V_dd 0.4 0.6 CMO S Dela y Delay ~ CV/I_on. 0 0.2 In vers e o f Propagation delay is nearly proportional to 0.6 – V_t/V_dd for V /V < 0 5 Desirable to keep V_t/V_dd < 0 3 V /V_{t dd} 0 0.2 0.4 0.6 0.8 0 for V_t/V_dd < 0.5. Desirable to keep V_t/V_dd < 0.3.

On/off-current trade-off

1E-4 1E-3 0 8 1 m ) µ m) L I 1E-6 1E-5 0.6 0.8 n C u rre nt (A /µ m n C u rren t (m A /µ Log scale V_dd I_on 1E-8 1E-7 0.2 0.4 Sou rce -D rai n So u rc e-D ra in Linear scale I_off -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1E-9 0 Gate Voltage (V) V =V _{ds dd}

For an incremental ΔV_t > 0, I_off decreases by a factor exp(qΔV_t/mkT) while I_on decreases by an amount g_mΔV_t, where g_m = dI_ds/dV_gs is the saturation transconductance.

MOSFET Design Space

t_ox 3t /W = m 1 = 0.4_{ox dm} W + 3t = L/2_{dm ox} Poor Sub-th. tox,max Poor SCE Slope t = V /Eox _dd ox,max 0 High Oxide Field W_dm t_ox,max = L/[6m/(m−1)] ≈ L/20

Direct Tunneling

Direct Tunneling

1E+6 1E+6 ) _{Data t ( )} I 1E+2 1E+3 1E+4 1E+5 1E+2 1E+3 1E+4 1E+5 y (A/cm ) 1.0 1.5 t (nm)_ox 2 I (100°C) I _on I (V =V )_{ds g t} Data Model 1E-2 1E-1 1E+0 1E+1 1E-2 1E-1 1E+0 1E+1 n t D e nsit y 2.2 2.0 2 6 I (100°C)_off I (25°C)_off 1E-6 1E-5 1E-4 1E-3 1E 2 1E-6 1E-5 1E-4 1E-3 1E 2 te C u rre n 2.6 2.9 3.2 3 5 tunneling e 0 1 2 3 1E-8 1E-7 1E-6 1E-8 1E-7 1E-6 Gate Voltage (V) Ga t _3.5 3.6

t (min) ~ 1-1 5 nm

MOSFET Design Space

t_ox

3t /W = m 1 = 0.4_{ox dm}

W + 3t = L/2_{dm ox}

Upper limit for V_dd:

Poor Sub-th. tox,max

20

/

max , ox dd

L

V

≤

E

Poor SCE Slope t = V /Eox _dd ox,max For t_ox

≥

20 nm, E_ox,max ~ 2 MV/cm, V

≤

10 V f L 1 0 High Oxide Field W_dm → V_dd

≤

10 V for L = 1 μm.

MOSFET Scaling Trends

5 10 g e (V) 2 500 eshold V o lta g V _dd 0.5 1 100 200 500 p ply and Thr e s (A) V _t 0.1 0.2 50 100 Pow er S u p x ide Thicknes t_ox 10 20 Ga te O x 0.01 0.02 0.05 0.1 0.2 0.5 1

Active and Standby Power

Higher active _{~CV f} dd 2 active power v ol ta ge CV f_dd Higher standby power w er su p p ly v qV /mkT) exp( Increasing Po w ~exp( qV /mkT)_t performance V /V_{t dd} ~0.7 Threshold voltage

Common to offer multiple-threshold voltages in today’s p g y CMOS technology.

Choice of Gate Work Function

V

V

V

V

Q

C

t fb B ox fb B d ox

=

+

2

ψ

+

=

+

2

ψ

+

2

ψ

_B ~ 1 V, need V_fb ~ -1 V to obtain low V_t;

i.e., n+ _{poly gate on nMOSFET and vice versa.}

q msφ Vg V fb ms= =φ Vg = 0 ψ B E _Ec q msφ Ev E_i Ec Ev E i E f E_f E f E f ⎟ ⎞ ⎜ ⎛ − − = a B g ms N kT q E l 56 0 2

ψ

φ

oxide p-type silicon n+ poly

n+ poly p-type silicon

⎟⎟ ⎠ ⎜⎜ ⎝ − − = i a n q ln 56 . 0 oxide

Threshold Voltage Adjustment

In a uniformly doped MOSFET, the maximum gate depletion width (long-channel),

W qN dm si B a 0 = 4ε ψ V V qN C V t W t fb B si a B fb ox B = +2

ψ

+ 4

ε

ψ

= + +(1 6 )2

ψ

and the threshold voltage,

C W t fb B ox fb dm B

ψ

( )

ψ

are coupled through the parameter N_a, and therefore cannot be varied independently (for given V_fb, t_ox).

To adjust threshold voltage, it is necessary to employ nonuniform channel doping. p y p g

Nonuniform Channel Doping

si x dx d dx d ε ρ ψ ( ) 2 2 − = − = E

For a nonuniform p type doping profile N(x) the electric field is obtained 1-D Poisson’s eq.:

∫

= Wd x N x dx q x) ( ) ( ε E

For a nonuniform p-type doping profile N(x), the electric field is obtained by integrating Poisson’s equation once (neglecting mobile carriers):

where W_d is the depletion layer width.

∫

x si ε

ψ

ε

s si x W W q N x dx dx d d =

∫

∫

( )′ ′ 0 W q N d d

∫

( ) Integrating again,

ψ

ε

s si q xN x dx =

∫

( ) 0 Integration by parts,

Note that the maximum depletion layer width W_dm0 _{is determined by the}

condition = 2 when W = W 0

condition

ψ

_s = 2

ψ

_B when W_d = W_dm0_.

The threshold voltage of a nonuniformly doped MOSFET is then determined by both the integral (depletion charge y g ( p g

High-Low Doping Profile

N(x)

n

The maximum depletion width at threshold is: Ns co n ce n tratio n W qN q N N x dm si a B s a s si 0 2 2 2 2 = ⎛ − − ⎝ ⎜ ⎞ ⎠ ⎟ ε _ψ ε ( ) Na Dop in g c

The body-effect factor takes the same form as before:

xs Wd

Depth

0 x

the same form as before:

m W C C C t W si dm ox dm ox ox dm = +1 = +1 = +1 3 0 0 ε / V V C qN q N N x q N N x C t fb B si a B s a s s a s = + + ⎛ − − ⎝ ⎜ ⎞ ⎠ ⎟ + − 2 1 2 2 2 2 ψ ε ψ ( ) ( )

The threshold voltage is, again, V_fb+2ψ_Β+V_ox(=Q_d/C_ox), i.e.,

C q C t fb B ox si a B si ox ⎝ ⎜ ⎠ ⎟ 2 ψ ψ ε

Implanted Gaussian Profile

Let (N_s − N_a)x_s = D_I and x_s/2 = x_c, Then W qN qD x dm si B I c 0 2 2 = ⎛ − ⎝ ⎜ ⎞ ⎠ ⎟ ε _ψ ε V V qN W C qD C t fb B a dm I = +2 + + 0 ψ and qN_{a ⎝} ε_{si ⎠} C C t fb B ox ox

For shallow surface implants, x_c = 0, there is no change in the depletion width. The Vp _tt shift is simply given by qDp y g y q _II/C_oxox like a sheet of charge at the silicon-oxide interface.

Low-High Doping Profile

Channel Doping N ₄ε ψ Take N_s = 0, then N_s N_a 0 W qN x dm si B a s 0 = 4ε ψ + 2 0 x_s W_dm0 x V V qN C N x qN x C t fb B a si B s a s = + 2ψ + 4ε ψ + 2 − C qN C t fb B ox a s ox ψ

In contrary to high-low doping, low-high (retrograde) doping results in a lower V than uniform doping for a given W_d

Extreme Retrograde Profile

x si s ε / For x_s >> (4

ε

_si

ψ

_B/qN_a′)1/2_, V V C t fb B si s ox B = + 2ψ + 2ψ V V + +⎛ tox ⎜1 3 ⎞⎟2ψ i.e., E_f Vt Vfb _W ox dm B = + + ⎝ ⎜ ⎠ ⎟ 1 2ψ

¾ The depletion depth is the same

i-Layer Region Poly p-Substrate n+ p+ xs=Wdm ≈ xj

as the undoped layer thickness. ¾ All the depletion charge is

located at the far edge of the

Q_M

Q_i

depletion region.

¾ Magnitude of the depletion charge is one half of the

Q_i

Qd

g

Counterdoping Profile

Electric uniform ground-plane V_ox Uniformly-Doped E Counter-Doped Field Ground -Plane counter-doped Area= 2ψ_B E_s (∝ Vox) 0 xs=Wdm Depth x Depletion 2ψ B Depletion width W_dm

Band diagram Field in depletion region

Counter-Doped Channel

Theoretically, it’s possible to obtain even lower V_t than the extreme

retrograde value by placing a shallow

t d d l t th

E_f

counterdoped layer at the surface thus turning the depletion charge term negative

negative.

In practice, this usually results in a buried Depl. Layer Region p-Substrate p+ x_s=W_dm ≈ x_j Midgap gate results in a buried channel device and it becomes difficult to

control W_dd and therefore the short channel effect.

Quantum Effect on Threshold Voltage

In an MOS inversion layer, carriers are confined in the direction perpendicular to the surface and therefore need be treated

quantum mechanically (2 D) Silicon surface E quantum mechanically (2-D).

[

( ) ( ) ( ) ( )

]

2 2 x N x N x n x p q d d d d a d − + ₋ + − − = − = ψ E Poisson’s eq.: q sψ Ec Ej Slope = Es E ′

[

( ) ( ) ( ) ( )

]

2 p dx dx ε_si d a

For 3-D classical case,

n x n e n e n N e i q kT i q kT i q kT i f B ( )= (ψ ψ− )/ = (ψ ψ− )/ = ψ/ 2 Ev Ec′ E f

In the quantum regime, N_a

h2 2 d ϕ

Oxide p-type silicon

where V(x) is formed by

ψ

(x) and the oxide barrier; and n(x) is

− h ₂ + = 2m d dx V x x E x * ( ) ( ) ( ) ϕ _{ϕ ϕ} ; ( )

Numerical Simulation Results

Numerical Simulation Results

Self-Consistent QM Solution

d

ens

ity

Classical

‰ Electron ground state is

E

lect

ron

Quantum

Depth

‰ Electron ground state is at some finite energy above the bottom of the conduction band. Conduction band edge Ox id e p

‰ Band bending must exceed 2

ψ

_B to invert ene rg y Lowest subband surface.

‰ The centroid of inversion layer is farther away

Electron

Bottom of the well

layer is farther away from the surface than in the classical case.

Magnitude of Quantum Effect

For E_s ~ 1 MV/cm, E₀/q = 0.17 V (m_x=0.92m₀) and x₀ = 1.2 nm. This means quantum effect raises V_t by about 100-200 mV and

0.4

adds Δt_ox = (ε_ox/ε_si)Δx_av = (x_avQM − x

avCL)/3 or about 3-4 Å to the

gate oxide thickness for calculation of the inversion charge density.

0 25 0.3 0.35 sh ift (V ) 0.15 0.2 0.25 face po tenti al

1E+3 3E+30 1E+4 3E+4 1E+5 3E+5 1E+6 3E+6 1E+7

0.05 0.1

Sur

f

1E+3 3E+3 1E+4 3E+4 1E+5 3E+5 1E+6 3E+6 1E+7

Channel Profile Evolution

> 1 µm CMOS: HIGH-LOW Dop ing 1E16 cm -3 0.5 µm CMOS: UNIFORM Doping Depth 5E16 cm -3 UNIFORM 0.2 µm CMOS: RETROGRADE Depth D oping 3E17 cm -3 RETROGRADE 0.1 µm CMOS: Depth D 3 HALO 0.05 µm CMOS: 1E18 cm -3 SUPER-HALO _{5E18 cm} -3

Channel Profile Trends

qN t

4ε ψ 6

For uniform channel doping,

V V qN C V t W t fb B si a B ox fb ox dm B = + 2ψ + 4ε ψ = + +(1 6 )2ψ

V_t is increasing slightly toward shorter channel lengths and higher N 2 D quantum effect further raises V as the

higher N_a. 2-D quantum effect further raises V_t as the

surface field increases and the electrons experience more confinement.

On the other hand, device design calls for lower V_dd and V_t as the CMOS dimensions are scaled down.

1-D vertically nonuniform doping only addresses V_t of long channel devices. Laterally nonuniform doping helps control V of short channel de ices

Laterally Nonuniform Doping (Halo)

Gate Drain Lo Hi Hi Source Depletionp boundary

¾ Halo implants are made after gate patterning, therefore self-aligned to the gate like source-drain

self aligned to the gate like source drain.

¾ Halo doped regions are farther apart for longer gates, and closer together for shorter gates.

¾ As a result, the “effective doping” becomes higher toward, p g g shorter devices, thus counteracting short channel effects.

CMOS Inverter

p+ V_dd V_dd V_dd I p p+ n-well In Out Out In C+ V_dd I_P p-substrate n+ In Out Out In I C− n+ I_N

Since only one of the transistors is on in the

steady state, there is no static current or

static power dissipation in a CMOS inverter

static power dissipation in a CMOS inverter.

CMOS Inverter Transfer Curve

Vout V dd A C IP IN V_in4 Vin3 Vin0 Vin1 Vin2 Vin1 Vin2 V D C V_in V dd B D 0 0 B A Vdd Vout in1 Vin3 D C

Qualitatively, the sharpness of the high-to-low

transition of the V

_out

-V

_in

curve is a measure of

how well the circuit performs digital operations

how well the circuit performs digital operations.

Transfer Curves of Logic Ckts.

1

2

3

4

V_in V_out V_in V_out V_in V_out V_in V_out V_{dd Vdd} V_out V_in V_in V_out 0 0

Meas re the abilit to regenerate or refresh binar logic states

V_in V_out V_dd 0 0 V_in V_out V_dd 0 0

Noise Margin of Logic Ckts.

1 2 3 4

V_in V_out V_in V_out

V_in V_out V_in V_out

noise noise noise

1 2 3 4

V_in V_out V_in V_out

V_in V_out V_in V_out

noise noise noise noise noise

V_dd noise V_dd noise

o

is

e

noise noise noise noise noise noise noise noise

V_out

V_in V_in V_out

n

o

Noise margin is given by the size of the largest square that can

V_in V_out V_dd 0 0 V_in V_out V_dd 0 0

Noise margin is given by the size of the largest square that can fit inside the two transfer curves.

Minimum Voltage with Logic Consistency

‰ Need non-linear characteristics for logic-state compression in conventional combinatorial logic circuits.

‰ Standard semiconductor devices exhibit nonlinearity only on voltage scales > kT/q, e.g., diode I-V: I ~ exp(qV/kT)-1.

‰ Multiple fan-in circuits have different transition points ‰ Multiple fan in circuits have different transition points

depending on the input combination.

V dd

A: V_in2 rising, V_in1=V_dd

P2 P1

Vout

B: V_in1 rising, V_in2=V_dd C: Both V_in1, V_in2 rising

N1 N2 Vx V in1 V in2

Minimum Voltage with Logic Consistency

V_dd

C

d

:

V in V ou t

A

C

da

sh

ed

solid:

V_dd 0 0 V _in

solid:

_in V _out

dashed:

The minimum power supply voltage for maintaining logic

Switching Waveform for a Step Input

(a) V dd Vout Sl I /C (b) V dd V_in (a) Pull down t V in Slope= I Nsat/C V dd/ 2 τ_n (b) Pull up t V _t Slope= I Psat/C V dd/ 2 τ in n Vout τp

For nMOSFET pull down transition,

(C +C₊)dVout = C dVout = −I_N(V_i =V_dd)

Similarly, the pMOSFET pull up delay is

C C

The pull down delay is

(C C ) ( ) dt C dt IN Vin Vdd − + + τ_n CVdd dd I CV W I = = 2 2 τ_p dd Psat dd p psat CV I CV W I = = 2 2 n Nsat n nsat I W I 2 2

For symmetric transfer curve and best noise margin,

th

idth

ti

h

ld b W /W

I

/I

2

Active Power Dissipation

Consider a capacitor C between the output node and the ground. Initially, the output node is at the ground potential and there is no charge on C.

During a pull up transition current flows from the power supply through the During a pull up transition, current flows from the power supply through the turned-on pMOSFET and raises the output node to V_dd. The capacitor is now charged to Q = CV_dd.

The energy flow out of the power supply is QV = CV 2 _{in which half or} The energy flow out of the power supply is QV_dd CV_dd , in which half or

CV_dd2_{/2 is energy stored in C; the other half is dissipated irreversibly as Joule} heat.

Now the node is pulled down and the capacitor discharged by current Now the node is pulled down and the capacitor discharged by current

through the turned-on nMOSFET to ground. The stored CV_dd2_{/2 energy is} now dissipated in the circuit.

⇒ A total energy of CV_dd2 _{is dissipated irreversibly in an up-down switching} ⇒ A total energy of CV_dd is dissipated irreversibly in an up down switching cycle. If the clock frequency is f, and on the average a total capacitance C undergoes an up-down cycle in a clock period T, then the CMOS power dissipation is P CVdd CV f 2 2 P T CV f dd dd = =

CMOS NAND and NOR Gates

NOR: Output is low unless all inputs are low.

NAND: Output is high unless all inputs are high.

V dd V dd Vout V in1 V in2 V_in2 Vout in1 V

MOSFET Layout

Contact hole Polysilicon gate W Active region W

d = a + b + c are layout

groundrules dictated by

lith

h

bilit

L c b a d

lithography capability.

Field oxide Field oxide n+ or p+

L is limited by either

lithography or device

design

CMOS Inverter Layout

Output N-well/p+ _p+ n+ Input Gr. V dd (a)

Folded (or

interdigitated) layout

Input N-well/p+ Output G V n+ p+

g

)

y

in (b) reduces the

junction capacitance

contribution by a

Gr. Gr. V dd V dd (b)

contribution by a

factor of 2.

Input Active region Polysilicon gate C t t h l Contact hole Metal

Two-way NAND Layout

Output P2 P1 V dd N-well/p+ p+ V dd n+ P2 P1 N1 Vout V in1 V dd Gr. Vx N2 Vx V in2 Input-1 Input-2 Active region Active region Polysilicon gate Contact hole Metal

Source-Drain Series Resistance

ƒ R_ac is the accumulation-layer resistance which is modulated by gate voltage and should be a part of the channel length

and should be a part of the channel length.

ƒ R_sp is the spreading resistance associated with current injection from the surface channel into the bulk.

ƒ R_sh = ρ_shS /W

Self-Aligned Silicide Technology

Sheet resistance: ƒ Metal (1 μm) — 0.05 Ω/sq ƒ N+, p+ diffusion (0.1N , p diffusion (0.1 μm) μm) — 50-500 Ω/sq50 500 Ω/sq ƒ Silicide (0.03 μm) – 5-10 Ω/sq

¾ R b

li ibl

¾ R

_sh

becomes negligible.

¾ R

_co

between silicide and metal is negligible.

¾ Long contact regime between silicide and Si

¾ Long contact regime between silicide and Si.

MOSFET Capacitances

Cov Cov Gate Cg Cov Cd Cov Drain Source CJ CJ

2

¾ Intrinsic capacitance: ¾ Parasitic capacitances:

C

_g

=

WLC

_ox

_C

_g

=

2

_WLC

_ox

3

• Depletion capacitance • Overlap capacitance • Junction capacitance dm s d

WL

W

C

=

ε

/

/

W

Wd

si

qN

a

Wd

C

=

ε

=

ε

Junction capacitance

)

(

2

/

j bi dj si j

V

Wd

W

Wd

C

+

=

=

ψ

ε

Overlap Capacitance

l Gate C f tgate lov C Drain Source xj Cdo Cof Cif tox C_if C_do Cof Drain Source j Wl 2 W ⎛ t ⎞ 2

ε

W ⎛ x ⎞

Direct overlap Outer fringe Inner fringe

C Wl C Wl t do ov ox ox ov ox = = ε C W t t of ox gate ox = ⎛ + ⎝ ⎜ ⎞ ⎠ ⎟ 2 1 ε π ln C W x t if si j ox = ⎛ + ⎝ ⎜ ⎞ ⎠ ⎟ 2 1 2

ε

π

ln For typical values of typ _{gategate ox}/t_ox ≈ 40 and x_{jj ox}/t_ox ≈ 20,,

C_of/W ≈ 2.3

ε

_ox ≈ 0.08 fF/μm, C_if/W ≈ 1.5

ε

_si ≈ 0.16 fF/μm (off state) C V C C C W l t ov g do of if ox ov ( = ) = + + ≈ ⎛ + ⎝ ⎜ ⎞ ⎠ ⎟ 0

ε

7 For reliability, l ≈ (2-3)t , C /W ≈ 10

ε

≈ 0.3 fF/μm t_ox ⎝ ⎠

Gate Resistance

G I(x) V(x) Gate L Cdx Rdx ( ) x=0 x=W

The resistance per unit length is

where

ρ

is the silicide sheet resistivity (Ω/ ) L R =

ρ

_g /

where

ρ

_g is the silicide sheet resistivity (Ω/ ). The capacitance per unit length is approximately Diffusion eq.:

C

C L

L

t

ox ox ox

=

=

ε

∂

∂

∂

∂

2 2 V RC V = q

The effective RC delay is RCW2_{/4 or}

For

ρ

_g = 10 Ω/ , t_ox = 50 Å;

τ

_g < 1 ps if W < 7.6 μm.

∂

2

∂

x t τ _g = ρgC Wox 2 4 g g

Interconnect Scaling

Lw

Interconnect parameters Scaling factor ( > 1) A w tins (κ > 1) Scaling assumptio Interconnect dimensions (t_w, L_w, W_w, t_ins, W_sp) 1/κ Ground plane ns Resistivity of conductor (ρ_w)

Insulator permittivity (ε_ins)

1 1

Derived Wire capacitance per unit 1

Lw/κ

Derived wire scaling behavior

Wire capacitance per unit length (C_w)

Wire resistance per unit length (R_w) 1 κ2 tins/κ A/κ2 length (R_w) Wire RC-delay (τ_w) Wire current density (I/W t )

1

κ

Interconnect Resistance

Interconnect RC delay is described by the same distributed RC-ckt & diffusion eq. as gate resistance.

1

2

where R_w =

ρ

_w/W_wt_w and C_w ≈ 2

πε

_ins (2 pF/cm).

τ

_w

=

1

R C L

_{w w w}

2

2

L 2 For aluminum and oxide technology,

τ

_w

πε ρ

_{ins w} w w w L W t ≈ L 2

Local wire RC delay < 1 ps as long as L_w2_/W

wtw < 3×105 and b l d d ith t bl s

τ

_w w w w L W t ≈ × − (3 10 18 ) 2

can be scaled down without problem.

For global wires, however, L_w does not scale down, e.g., L_w2_/W

wtw ∼ 108-109, and

τ

w ∼ 1 ns. Therefore, Wwtw cannot

w w w w w w

Global Interconnects

1E-9 1E-8 s) Wire size: 0.1 μm 0 3μm 1E 11 1E-10 n nect delay ( s 0.3 μm 1.0 μm Chip 1E-12 1E-11 In te rc o n Limited by speed of EM-wave

Must also scale

0.001 0.01 0.1 1 10

1E-13

Wire length (cm)

Must also scale up insulator

spacing

otherwise C ↑ RC Delay ~ l 2 /A Time of Flight ~ l /c otherwise C_w↑ RC Delay /A Time of Flight /c

Ultimately, signal propagation is limited by the speed of electromagnetic wave,

c/(ε /

ε

)1/2 _{(70 ps/cm for oxide) instead}

c/(ε_ins/

ε

₀) , (70 ps/cm for oxide), instead of by RC delay.

Propagation Delay

1 2 3 4

V1 V2 V3 V4

C C C C

For a chain of CMOS inverters or NAND/NOR gates,

CL CL CL CL 2.5 g e (V) V1 V2 V3 V4 CMOS propagation delay equals 1.25 Node v o lt a g V1 V2 V3 V4 τn τp 2τ

τ

= (

τ

_n +

τ

_p)/2,

where

τ

_n is the pull-down delay and

τ

_p is the pull up delay

100 200 300 400 500

0

is the pull-up delay.

100 200 300 400 500

Bias Point Trajectories

4

Vin = 0

IP

Pull down

Pull up

4 Vin = 0 I 2 m A) 0.5 1.0 P 2 m A) 0.5 1.0 IP 0 n si st o r c u rre n t ( m 1.5 Vin = 1.0 0 n sisto r cu rren t ( m 1.5 Vin = 1.0 -2 Tr an 1.5 2.0 I -2 Tr an 1.5 2.0 0 0.5 1 1.5 2 2.5 -4

Output node voltage (V) 2.5 −IN

0 0.5 1 1.5 2 2.5

-4

Output node voltage (V) 2.5 −IN

Output node voltage (V) Output node voltage (V)

Delay Equation

200 Fan-out = Wn=10 μm Wp=25 μm 3 Delay equation: 150 de la y (ps) 2 1 R_sw: Switching Resistance ( d /dC )

FO

τ

=

R

_sw

×

(

C

_out

+

×

C

_in

+

C

_L

)

50 100 Inv e rt er Slope=Rsw (≡d

τ

/dC_L)

C_in: Input Capacitance (to next stage)

C : Output Capacitance

0 0.05 0.1 0.15 0.2 0.25

0

Load capacitance (pF)

τint=Rsw(Cin+Cout) Cout: Output Capacitance

FO: Number of Fan-Out’s Load capacitance (pF)

The delay equation not only allows the delay to be calculated for any fan-out and loading conditions, but also decouples the two important factors that govern CMOS performance: the two important factors that govern CMOS performance: current and capacitance.

Input and Output Capacitance

p+ n-well V_dd V_dd V_dd V_dd I_P p-substrate n+ p+ In Out Out In I C+ C− n+ I_N

C : For switching n/p gates of the receiving stage C_in: For switching n/p gates of the receiving stage. C_out: For switching n/p drains of the sending stage.

Gate Cg Cov Cd Cov Gate Drain Source CJ _C J

Switching Resistance

Switching resistance R

_sw

is a direct indicator of

the current drive capability of the logic gate.

the current drive capability of the logic gate.

If we define R

_swn

≡ d

τ

_n

/dC

_L

and R

_swp

≡ d

τ

_p

/dC

_L

,

then R

= (R

+ R

)/2 and we can write

then R

_sw

= (R

_swn

+ R

_swp

)/2 and we can write

R

k

V

W I

swn n dd

=

R

k

V

W I

swp p dd p p

=

where I

_n

, I

_p

are maximum on currents at V

_ds

= V

_g

= V

_dd

, and k

_n

, k

_p

are numerical fitting parameters.

W I

_{n n p p}

dd

,

n

,

p

g p

For step inputs with zero rise time, k

_n

= k

_p

= 0.5.

Delay Sensitivity to n/p Width Ratio

100

Note that for equal pull-up 80

s)

τp and pull-down delays (

τ

_n =

τ

_p) and therefore symmetric transfer curve and best

i i W /W 2 5 40 60 ins ic del ay ( p s τ noise margin, Wp/Wn = 2.5.

Minimum CMOS delay (

τ

20 40 Int ri τn Table 5.2 value

Minimum CMOS delay, (

τ

_n +

τ

_p)/2, however, occurs at W_p/W_n = 1.5.

0 0.5 1 1.5 2 2.5 3 3.5

0

Buffer Stage for Heavy Loads

For a given W_p/W_n ratio, if both widths are increased by a factor of k, then R_sw→R_sw/k, C_in→kC_in, C_out→kC_out. No change in

intrinsic delay,

_τ

₌

_R

_×

₍

_C

₊

_C

₎

intrinsic delay,

But driving capability is improved.

Consider a CMOS inverter driving a large capacitive load:

τ

_int

=

R

_sw

×

(

C

_in

+

C

_out

)

If C_L >> C_in, C_out, the delay can be improved by inserting a buffer stage k (> 1) times wider than the original inverter The

two-τ

=

R

_sw

(

C

_out

+

C

_L

)

stage k (> 1) times wider than the original inverter. The two stage delay is

which has a minimum

τ_{b sw out in} sw out L sw out in L R C kC R k kC C R C kC C k = ( + )+ ( + ) = (2 + + )

which has a minimum when k = (C_L/C_in)1/2_.

M ltiple stage b ffers can be sed for er hea loads

τ _bmin = R_sw(2C_out +2 C C_{in L} )

Multiple-stage buffers can be used for very heavy loads (Problem 5.8-10).

Delay Sensitivity to Channel Length

20 000 2 3 aci ta n ce ( fF /µm ) 15,000 20,000 ( ) WpRswp Ω -μ m 0 1 0 15 0 2 0 25 0 3 0 4 0 5 1 1.5 Inp ut, o u tp ut c ap a Cin/(Wn+Wp) Cout/(Wn+Wp) 6,000 7,000 8,000 9,000 10,000 ing resistance ( _{0.1 0.15 0.2 0.25 0.3 0.4 0.5} Channel length (µm) I 80 90 100 3 000 4,000 5,000 S w itc h i WnRswn 40 50 60 70 sic d ela y ( p s) 0.1 0.15 0.2 0.25 0.3 0.4 0.5 3,000 Channel length (µm) 30 40 In tr in s 0.1 0.15 0.2 0.25 0.3 0.4 0.5 20

Delay Sensitivity to Oxide Thickness

15,000 3 W R 8 000 9,000 10,000 2 ) _{e (f} F /µm ) Cin/(Wn+Wp) WpRswp Ω -μ m 100 150 6,000 7,000 8,000 ing re sistan ce ( tput capaci ta nc e Cout/(Wn+Wp) Ω 70 100 erte r de la y (ps) CL=0.1 pF 4 000 5,000 1 S w itch i Input , o u t WnRswn 50 In v e Wn=10 μm Wp=25 μm CL=0 4 5 6 7 8 9 10 11 3,000 4,000 0.7 4 5 6 7 8 9 10 11 30

Gate oxide thickness (nm)

p μ

Delay Sensitivity to V

_dd

and V

_t

8 Delay sensitivity to V 6 O S Dela y ~ _{V /V} t dd 0.7 1 Delay sensitivity to Vdd

and V_t is mainly in the R_sw factor. 2 4 m al ized CM O

Note that the

dependence is stronger 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 2 No rm p g than I_on ∝ 1 − V_t /V_dd, due to the finite input rise time.

V /V_{t dd}

CMOS Performance and Power

Higher

active

~CV

_dd2

f

active

power

a

ge

CV f

_dd

Higher

standby

power

Increasing

p

ply

volt

a

power

g

performance

o

we

r s

u

p

V /V

_{t dd}

~0.7

qV /mkT)

_t

~exp(

P

o

Threshold voltage

Threshold voltage

CMOS Power vs. Delay Trade-off

100 V = 2.0 V_dd 0.1 μm CMOS 101 t i t 10 a ge (uW ) 1.0 V 1.5 V 101-stage inverter 1 P ow e r/s ta 0.7 V 0.5 V 0.4 V P ~ f3 10 30 100 300 0.1 P P ~ f W = 3 μm W = 4 μm n p

Significant power savings by trading off performance and

10 30 100 300

Delay/stage (ps)

g p g y g p

Overlap Capacitance and Miller Effect

Consider driving 3 capacitors with respect to different voltages:

V dd C i V V1 V2 C1 C2 V3 C3 i = C d V( −V1) + C d V( −V2) +C d V( −V3) i C dt C dt C dt = ₁ + ₂ + ₃ i C dV dt C dV dt C dV dt C dV dt = ₁ + ₂ − ₂ 2 + 3 If dV₂/dt = −dV/dt, then

C appears do bled to the dri ing so rce

i C C C dV

dt

= ( ₁ +2 ₂ + ₃)

Components of C

_in

and C

_out

Cg Cov Cov Gate CJ Cd CJ Drain Source Input capacitance Output capacitance

Intrinsic gate oxide

_57%

_14%

Intrinsic gate oxide capacitance (n & p)

57%

14%

Overlap capacitance

43%

35%

capacitance Junction capacitance (non-f ld d)

---

51%

folded)

Two Input (Two-way) NAND

P2 P1

V dd

Top (N1) switching: Effective gate drive is V_in1 − V_x, threshold is V + (m 1)V due to P2 P1 N1 V_out V in1 threshold is V_t + (m − 1)V_x due to body effect.

Bottom (N2) switching: Has

N2 Vx

V in2

Bottom (N2) switching: Has

more capacitance (of N1) to pull down. 2.5 age ( V )

2-way NAND (Top Switching)

Vout

2-way NAND (Bottom Switching) 2.5 tag e ( V ) Vout Vx 0 1.25 Node v o lt a Vin Vx 0 1.25 Nod e v o lt Vin 100 200 300 400 500 100 200 300 400 500

Two Input (Two-way) NAND

V dd 150 200 ) Top switching Bottom switching 2-way NAND

{

P2 P1 V_out 100 150 g at io n dela y ( p s) N1 N2 Vx V in1 V in2 0 50 Pro p ag Fan-out=1 Wn=10 μm Wp=20 μm Inverter 0 0.05 0.1 0.15 0.2 0 Load capacitance (pF)

⇒ Delay is about 30% worse than inverter.y (Fan-in > 3 rarely used.)

dd p dsat dd n sw I W V k I W V V k R 2 2 ) 1 FI ( − ₊ + ≈ p p n n sw I W I W 2 2

MOSFETs in RF Circuits

MOSFETs in RF Circuits

Drain

+

Gate

_Body

+

Body

+

v

gs

i

ds

i

gs

v

ds

v

bs

Source

-gs g

-Small signal linear equivalent circuit:

v =

|v |e

jα

means

δ

V = Re(

|v |e

j(ωt+α)

) =

|v |cos(

ω

t+

α

) etc

Equivalent RF Circuit of MOSFETs

Equivalent RF Circuit of MOSFETs

Gate Cgd Drain + + Body Cdb C_gb C_gs g_mbv_bs g_mv_gs g_d + v_gs i_gs + v_ds i_ds Source C_bs gmb bs gm gs gds

-

-bs ds V V gs ds m

I

V

g

≡

(

∂

/

∂

)

_, bs gs V V ds ds ds

I

V

g

≡

(

∂

/

∂

)

_,

)

/

(

∂

∂

ds gs V V bs ds mb

I

V

g

≡

(

∂

/

∂

)

_,

Simplified Equivalent RF Circuit

Simplified Equivalent RF Circuit

C

_gd

Gate

Drain

i

gs

C

gs

+

v

_ds

i

ds

g

_ds

C

_db

v

_gs

+

g v

_{m gs} g g

-ds

Source

g

_ds gs

-g

_{m gs} Kirchhoff’s laws:

⎥

⎦

⎤

⎢

⎣

⎡

⎥

⎦

⎤

⎢

⎣

⎡

+

+

−

−

+

=

⎥

⎦

⎤

⎢

⎣

⎡

ds gs gd db ds gd m gd gd gs ds gs

v

v

C

j

C

j

g

C

j

g

C

j

C

C

j

i

i

ω

ω

ω

ω

ω

(

)

Unity Current Gain Frequency

Unity Current Gain Frequency

⎥

⎤

⎢

⎡

⎥

⎤

⎢

⎡

+

−

=

⎥

⎤

⎢

⎡

i

gs

j

ω

(

C

gs

C

gd

)

j

ω

C

gd

v

_gs

⎥

⎦

⎢

⎣

⎥

⎦

⎢

⎣

−

+

+

⎥

⎦

⎢

⎣

i

ds

g

m

j

ω

C

gd

g

ds

j

ω

C

db

j

ω

C

gd

v

ds

Current gain with output shorted i e v_d = 0:

)

(

0 gd m v ds

C

C

j

C

j

g

i

i

ds

+

−

=

=

₌

ω

ω

β

Current gain with output shorted, i.e., v_ds 0:

)

(

_{gs gd} gs

j

C

C

i

ω

+

Solve

|

β

| = 1 for f

_T

=

ω

/2

π

:

)

(

2

2

2

2 gs gd m gd gs gs m T

C

C

g

C

C

C

g

f

+

≈

+

=

π

π

Effect of Transport Parameters

Effect of Transport Parameters

c sd b sat a eff sw

v

R

R

∝

μ

− − where a + b + c = 1. 2 u e) μ eff (n,p):

0.1 μm CMOS _{ƒ CMOS devices are}

t l it 1.5 ce (r el at iv e v al u ff v (n,p):sat 1/R (n,p):sd not as velocity

saturated as one might think (due to mobility degradation) 0.7 1 tching resistan c _{degradation).} ƒ Strained engineered high mobility MOSFETs

0.2 0.3 0.5 1 2 3

0.5

R i T bl 5 2 l

Swi

t high mobility MOSFETs

offer performance benefits.