Training Program. Advanced Design Program in Semiconductors Technology

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Unidad Guadalajara

Training Program

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Unidad Guadalajara

PADTS

A program supported by the Jalisco State Governement

• Consejo Estatal de Ciencia y Tecnología “CoecytJal”

A program hosted by Cinvestav-CTS

• Centro de Tecnología de Semiconductores “CTS”

PADTS objectives

• To train 500 ASIC-MPU embedded-SoC design engineers in a period of 5 years

• To impel the development of the design industry in the region

• To attract new investments to the region

• To seed the grains of the future High-Tech Jalisco’s companies

Design & Education Center

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Unidad Guadalajara

Organization Chart

J. Luis Leyva

Direc

tor

Acad

Acadeemic mic Counselor Counselor

Manuel Ramírez

CTS

CTSR&D ManagerR&D Manager

Jorge Gamboa

General

General AdministratAdministratoror

Rosa Michel

Acc

Accoouuntabntablele

Veronica Muñoz

Planning

Francisco. de la Torre

Comput

Computer Sc. Coord.er Sc. Coord.

Felix Ramos

Autom.

Autom. Control Control CoordCoord..

Antonio Ramírez

Electr

Electronic Des. Coord.onic Des. Coord.

Federico Sandoval

Power Eng. Coord.

J. Manuel Rodriguez Reception Reception Aurora Corona Facilities Services Facilities Services Elvia López

CTS

DIECC

VoIP

VoIPProProjjectectManagerManager

Miguel Ramírez

3M

3MProProjjectectManagerManager

Rodrigo Morones

HP

HPProProjjectectManagerManager

Carlos López

Phogenix Project Manager

Javier Rico

S

Software Project CDSoftware Project CDS

Felix Ramos

Telecom.

Telecom.Coord.Coord.

Deni Torres

Library Resp.

Aracely Calzado

Administra

tio

n

Messanger & Driver

Messanger & Driver

Patricio Mata

Assistant

Carolina Mata

PADTS, 500 ASIC

PADTS, 500 ASIC--SoC SoC

Designers

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Unidad Guadalajara

Why CTS?

CTS has 15 years experience in the field supporting the electronic industry

Support to R&D groups

Experience of developing products for the industry

Creation of new companies

Semiconductors & SW Applications

Design House

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Unidad Guadalajara

Mission of PADTS

Create a semiconductor technology educational center in Guadalajara

•

Leadership in the formation of world class high performance designers

- Continues formation of professional designers

- Keep up with cutting edge technologies and design methodologies

- Keep up a program driven by technology, market and business tre nds

- Funding by developing industry projects

•

Contribute in the development of the economy of semiconductors design

industry in Mexico.

- Keep up with the best practices in high technology business

- Incubate and spin off new semiconductors design houses

500 designers

Spin off Design Houses

2008

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Unidad Guadalajara

Business model and new CTS organization

• Reinforce the current CTS lab infrastructure

• Develop CTS intellectual property (IP)

• Develop marketing, business, finance and sales forces

• Develop Business Plan and involve Venture Capital

• Incubate new design houses in the region

PADTS is the educational program while CTS-R&D lab is the Hands on industry projects partner

Strategy

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Unidad Guadalajara

Schedule

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 B C D E F G H I J K L M N O P Q R S 2002 2003 2004 2005 2006 2007 2008 2009 2010 H1-02 H2-02 H1-03 H2-03 H1-04 H2-04 H1-05 H2-05 H1-06 H2-06 H1-07 H2-07 H1-08 Phase 1

Conceptualization and program set up

25 Associated Designers 25 Associated Designers 100 Designers (TBD) 100 Designers (TBD) 125 Designers (TBD) 125 Designers (TBD)

Develop Business Infrastructure

Creation of new DESIGN HOUSES Phase 6

Business ramp up & IP generation Phase 2 Phase 3 Phase 4 Phase 5

PADTS Program

New CTS Program

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Unidad Guadalajara

Budget

Program set up Sep-02 to Feb-03

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Unidad Guadalajara

Training strategy

Based in teaching the Know-How

First 6 months

• Review of a set of theoretical courses

• Learn the use of the design automation tools

• Learn the ASIC design Know-How based in uProcessor structures

Following months

• Work in CTS design projects for industry

It is our objective that at the end of first six months, the trainee could be

incorporated in CTS design projects under the tutoring of a Seni or engineer

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Unidad Guadalajara

Training strategy (model)

Scientific Designer Level

Engineering level

requirements

Engineering level

requirements

Associated Designer Level

System Designer Level

Design Leader Level

Specialization

lectures and

seminars

Specialization

lectures and

seminars

Industry projects

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Unidad Guadalajara

Training strategy (cont.)

Scientific Designers

Design Leaders/ Design Mgr.

CTS System Designer

Associated Designer

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Unidad Guadalajara

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Unidad Guadalajara

PADTS program

Prerequisites courses

• Calculus and differential equations

• Electric circuits

• Object programming (C++ and JAVA reference)

• Personality development

Regular courses

•

Linear algebra, Taylor and Fourier series and Fourier transforms

• Semiconductors fundaments

• Boolean algebra and digital design

• Micropocessors and computer architectures

• RTOS fundamentals (Linux)

• PLC, design specs and quality concepts

• Emotional intelligence development dynamics

• English

1 month…

2 months….

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Unidad Guadalajara

PADTS program (cont.)

•

ASIC design

(ASIC design flow …from modeling to net list generation)

•

MPU 8 bits design

(“Design for” …methodologies and clues)

•

Design project

•

Industry projects (

be part of a design team working on real industry projects)

4 months

Following

months

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Unidad Guadalajara

Scholarship program

Covers:

• 100% of the cost of lectures and seminars

• labs usage and lab’s material

• library usage

Prerequisites to be accepted and obtain the scholarship

• Pass all prerequisites courses exams with a minimum note of 8.0

• Pass interviews round with instructors and PADTS personnel

• Full time availability

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Unidad Guadalajara

Key dates

• Information sessions at CINVESTAV campus GDL

- January 29 (12:00pm)

- February 1 (12:00 pm)

•Students sign up starting January 29

•Interviews Feb 3-13

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Unidad Guadalajara

Information

• Aida Iruegas, PADTS Academic Coordinator

- Email [email protected]

- Tel (33) 3134-5570 x 2036

• Jesús Vázquez, Special Seminars & Lectures Coordinator

- Email [email protected]

- Tel (33) 3134-5570 x2012

• Francisco de la Torre, CINVESTAV University Liaison

-

Email

[email protected]

- Tel (33) 3134-5570 x 2079

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Unidad Guadalajara

Industry Sponsors

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Unidad Guadalajara

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• ECSI

European “Electronic Chips & System Integration”

• SED

Indian School of Electronics Design (Sirius)

• VDEC

Japan VLSI Design & Education Center

• ISLI

Scotland Institute for System Level Integration

• IDEC

Korean “IC Design Education Center”

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Industry

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Unidad Guadalajara