1. The decimal number + 122 is expressed in 2’s complement form as:
A. 01111010 B. 11111010 C. 10000101 D. 10000110
2. The binary number (10001101010001101111)2 in hexa-decimal form is :
A. (AD467)16 B. (8C46F)16 C. (8D46F)16 D. (AE46F)16
3. Flip-Flops operate as a ………… devices :
A. Mono-Stable B. Bi-Stable C. Oscillator D. A Stable
4. Commutative law can be represented as:
A. A(B+C)=AB+AC B. A’ . A= 0 C. (A+B)=(B+A) D. None of All 5. The AND operation can be produced with:
A. 2-NAND Gates B. 3-NANS Gates C. 2-NOR Gates D. 3-NOR Gates 6. The basic element in comparator circuits is:
A. NOR Gate B. OR Gate C. XNOR Gate D. XOR Gate
7. Latch outputs characterized by: A. Edge Triggered B. Level
Triggered C. A+ B D. None of All
8. In Master-Slave D Flip-Flop, Qslave looks like it is a :
A. Negative Triggered
B. Positive
Triggered C. A + B D. Toggle
9. Data selectors are basically the same as:
A. Decoder B. Multiplexer C. Encoder D.
De-Multiplexer
1
2
3
4
5
6
7
8
9
10
A. Alphabetic and
Data B. Symbols C. Letters D. All of them
11. A 3 variable karnaugh map has:
A. Four Cells B. Three Cells C. Sixteen Cells D. Eight Cells 12. A de-multiplexer with two data selectors has:
A. One Output B. Two Inputs C. One Input D. Two Outputs
13. T Flip- Flop states are :
A. (RESET, SET) B. (NC, Toggle) C. (NC, RESET) D. (SET, Toggle) 14. This operation 11100 + 01111 need :
A. 5 Half Adders B. 4-Bit Adder C. 1 Half Adder +
4 Full Adders D. All are True 15. The binary number (10001101111)2 in octal form is :
A. (2157)8 B. (1157)8 C. (0157)8 D. (10157)8
16. The BCD number 10011000 in binary form is :
A. (0100010)2 B. (1100110)2 C. (1101010)2 D. (1100010)2 17. Negative AND gate has the same truth table as positive:
A. NAND Gate B. NOR Gate C. OR Gate D. NOT Gate
18. Implementation of the function F= A (B + C) has:
A. 2- Level B. 1- Level C. 3 - Level D. 4 - Level
19. Odd Function is:
A. F = X’Y’+XY B. F = X’Y+XY’ C. F = X’+Y D. F = X+Y’
20. (A. A’) is always equal to:
ةرورض
حت
تامسرلا ىلع طوطخلا ديد
يف جرخلا مسر دنع
( دنب صخي ام
2
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4
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5
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6
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1.
Implement a logic circuit to convert a 5-bit binary number to its equivalent gray code then use the circuit to convert (10101)2. (3 Pt)2.
For the following multiplexer logic circuit, if S2 S1 S0 given as below, draw the output Y.(2 Pt)S0 S1 S2 S0 S1 S2
4.
Draw the Q and Q’ outputs relative to the clock for the D-Flip flip with the inputs as shown below. Assume D-Flip-Flop initially is RESET. (3 Pt)Flip with the inputs as shown below. Assume Q initially is Low. (3 Pt)
6.
Draw the Q and Q’ outputs relative to the clock for the J-K Flip-Flip with the inputs as shown below. Assume Q initially is Low. (3 Pt)F(x) = A’B’C’ + A’B’C+ A’BC’+ ABC + AB’C’ +AB’C D(x) = ∑(6, 10) 1 1 1 1 1 1 1 F(x) = ∑(0,2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14) 1 1 1 X X 1 1 1
level output. Then verify the output for a binary input of A2 A1 A0 = 100. (10 Pt)
(a) Design (4 Pt.)
(b) Implementation and Verification (3 Pt.)
Y; and one output Z, is specified by the following next- state and output equations: (10 Pt)
(a) Draw the logic diagram of the circuit (2 Pt.)
(b) Derive the state table (4 Pt.)
Present State Next State Output Inputs (XY) 00 01 10 11 A B A B A B A B A B Z
Question Five:
Design a BCD to Excess -3 converter combinational circuit. (15 Pt)Design (10 Pt.)
Truth Table K MAP and Equations
Implementation
(5 Pt.)
