Electroplating aspects in 3D IC Technology

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Electroplating aspects in 3D IC

Technology

Dr. A. Uhlig

Atotech Deutschland GmbH

Semiconductor R&D

(2)

Packaging stacking (PoP, PiP)

Die stacking (SiP)

(wire bonding & FC)

Miniaturization in size and weight

Integration of heterogeneous technologies and complex multi-chip systems

Short vertical interconnects

Reduced power consumption and parasitics

Increased performance and functionality

3D integration with TSVs

(W2W, C2W, C2C)

3D Advanced Packaging

(3)

3D Chip stacking

Proposed Applications

IBM ECTC 2008

IME ECTC 2008

SFT ECTC 2008

Application determines TSV size; type of

interconnection, handling sequence, …

(4)

TSV

Conductive paste printing

50 < d < 100µm

Copper plating

1 < d < 70 µm

CVD W, poly Si

0,1 < d < 1µm

Bumping

Cu-RDL/Screen printed solder paste

150 µ < pitch < 400µm

Copper pillar/E-plated bumbs

30 µm < pitch < 100 µm

E-plated microbumps

10 µm < pitch < 30 µm

Metal to Metal

pitch < 20 µm

Conductive adhesive

Sputtering (also C4NP)

10 µm < pitch < 100 µm

RDL

Al PVD

Copper electroplating plating

TSV seed layer

Sputtered Cu, W, …; CVD; ALD

E’grafting

E’less copper

3D plating applications

& Outline

e

c

(5)

• conformal/ bottom up plating

• status

(6)

TSV plating principles

„bottom up“

„conformal“

Drilling/ etching Barrier/ Seedlayer Copper plating/ CMP Wafer thinning Drilling/ etching Barrier Attach to conductive Support wafer Copper Plating CMP/detach

(7)

Galvanic plating principles

„Panel-plating“

Galvanic deposition Barrier & plating base deposition

conformal TSV; DD

Photo-resist

coating & structuring

Galvanic deposition

„Through-mask-plating“

bottom up TSV; RDL; Pillar

(8)

Copper Sulphate

35 – 50 g/l

Sulphuric Acid

170-100 g/l

Chloride

30-100 g/l

Brightener

• adsorbs on Copper

• disables

Cu-deposition

Carrier

• desorbs Brightener

• enables

Cu-deposition

Leveller

• adsorbs on copper

• surpress

Cu-deposition

Copper Electrolyte Composition

Microscopic level

Macroscopic level

(9)

Bottom Up TSV electroplating: Status

Dimensions

20 x 500 µm

200 x 450 µm

Done in collaboration

(10)

Copper Pillar: Spherolyte Leveller UF

Profile

4,4 % 4,4 %

6,3 %

uniformity

1 µm/min

2 µm/min

2.5 µm/min

Profile uniformity

80 µm array bump

- Pillar plating know how to be adopted to very high A/R

- TSV related targets?

(11)

• Plating targets

1 void free filling

2 fast

3 low overburden

4 low dimple

5 low stress

5 low additive consumption

• Main impacting factors

• Electrolyte/ Additives

• Current profile

• Flow (equipment)

• Via shape

• Seed layer resistivity

1

3

4

1 TSV Copper plating targets & main impact

factors

Risk of „pinch off“

(12)

Copper electrolyte

• Leveller: - strong Copper plating inhibitor

- diffusion controlled enrichment

δ

_N

TSV

Electrolyte

Leveler

Leveler inhibits copper deposition at via aperture preventing pinch off

Not one recipe for all TSV dimensions

Role of Additives for pinch off: Leveler

Concentration Spherolyte Leveller AT = 10 ml/l

(13)

Pulse reverse prevents pinch off & reduce overburden

Roughness impact for CMP?

Role of Current schema: DC versus AC

Same Electrolyte/ plating time

DC

AC

TSV

time

current

1

2 1 Cu

2+

_{+ 2e}

-

→ Cu

2 Cu

→ Cu

2+

_{+ 2e}

-Reverse Pulse

(14)

Conformal TSV electroplating: Status

A/R: wide range fillable

Speed: 10 x 65 µm in 45 min @ Semitool CFD3

Diameter [µm]

Aspect R

a

tio

40 µm

2 20 µm

5 10 µm

8 Electrolytic

copper filling

of through

silicon vias in

different

aspect ratio

Investigated on

different seed

layer types

(15)

Bottom of TSV: Cu

+

_{+ e}

-

→ Cu

Top of TSV: Cu

+

_{+ e}

-

→ Cu

Fe

3+

_{+ e}

-

→ Fe

2+

2Fe

3+

+ 2Cu → 2Fe

2+

_+Cu

2+

Distance x

δ

_N

x = 0

c(Me

z+

₎

Electrode

Electrolyte

c

0

_(Fe

3+

₎

x *= 0

c

S

_(Fe

3+

₎

Atotech’s Fe

2/3+

_system

- Fe

3+

_{: reduces overburden}

- Hardware & electrolyte modification required

(16)

(17)

Adhesive

Electroplated

10 < d < 100µm

Printed

100 < d <400µm

Evaporated

5 < d < 20µm

Solder

_{Metal-to-Metal}

Microbumping

• Sn on copper

• SnAu

• CoSn

• Pillar

• ....

Bumping

• SnAg

• SnAgAu

• Sn

• SnPb

• ..

Assembly for 3D

(18)

Tin

_{(10 µm/min)}

on < 5 µm TSV

⇒

to large grain size

Micro bumbs - Grain size

Pure Tin/ SnAg

_3%

grain size comparison

Tin

221°C

After deposition (40 µm pads)

After reflow

235°C

(19)

2,5 µm

Micro bumps - Assembly

5 µm

reflow

Impact of Wafer bow ?

5 µm

reflow

Risk of Electrical shorts

Geometrical aspects

(20)

Microbumps - Reliability

Source: Eric Beyne IMEC

Solder joint reliability for fine pitch

• IMC consumes solder

• (CuSnCu): EM might lead to spalling

Source: Kim ECTC 2008 Source: Kim ECTC 2008

(21)

Electromigration: reduce local current density

Alternatives: Pillar/ RDL

Copper

Tin

500 µm

Pil

lar

Redi

strib

_ution

Source: Lai (ASE) ECTC 2008

(Cu, Ni, Pd)

₆

Sn

₅

Ni(P)

Galvanic Ni/Pd UBM

E‘less Ni/Pd UBM

Kirkendahl voids: Under Bump Metallisation

+ printed solder

+ e-plated solder

(22)

Copper Pillar

• Status

(23)

Copper/Tin Pillar

Cu(Ni-P)Sn Pillar

30µm Cu 2µm Ni-P 10µm Sn

Cross section of Cu/Ni/Sn Pillar

Source: Atotech

50x80 µm copper pillar/ 20 µm Sn; 80 µm pitch

Source: IME Singapore using Atotech chemistry

• Reliability data for Cu/(Ni-P)/Sn microbumps?

• Thickness, P-content etc

• Target costs?

• process time ?

(24)

• Status RDL

• e’less UBM

• Ni/Pd solder & bond reliability

• Equipment solutions

(25)

Cu-RDL: Spherolyte Leveller UF

Deposition rate…..

0.4 µm/min

0.6 µm/min

0.8 µm/min

1.0 µm/min

Within dye uniformity

Roughness < 7 nm

(26)

E’less UBM for soldering

Ni(P)/Pd process flow

Ni

Pd

Etch

Activator

Postdip

Cu pad:

Process on Cu (d >50 µm) pads industrialized

E’less = mask less process

⇒

cost advantage

E‘less

_{Metal Pad}

_{Sur. Pretreatment}

_{Metal dep.}

Metal Pad

_{PR process}

_{Metal dep.}

_{PR strip}

PVD

(27)

E’less Ni/Pd UBM: Soldering

Shear strength: multiple reflow test

Solder Mechanism: IMC Ni/Pd

0

10

20

30

40

50

60

70

80

1

5

10 3um Ni/0,1umPd/30nm Au

3um Ni/0,1umPd

Number of Reflow Cycle

Lot’s of experience available (Flip chip)

Solder Shear fore: 10x RF; 1000h HAST passed

So

lder

Ball She

a

r

Force [g]

(Cu, Ni, Pd)

6

Sn

5

Ni(P)

(Cu, Ni,Pd)

₆

Sn

₅

Ni(P)

_{( Ni, Cu)}

3

Sn

4

1x RF

(28)

E’less Ni/Pd UBM: Wire Bonding

Bond mechanism

Ni

Au

Pd

300nm

SEM EDS after 1000h @ 150°C

Shear strength: HAST

0,0

5,0

10,0

15,0

20,0

25,0

30,0

35,0

40,0

45,0

50,0

55,0

0 hr

250 hrs

500 hrs

1000 hrs

0.3 um Pd / 3 um Ni

Time @ 150C

Au Ball Shear

Force [g]

Required minimum strength

(29)

Semitool “Raider”

“Cintillio”

Single wafer tool

• Batch tool

10 Wafer/h

• 100 Wafer/h

Commercialized

• α-Tool @ Atotech/ Germany

Single wafer immersion & Batch spray tool

Tools available for

• low/ high through put

(30)

• conformal plating

• through mask plating

(31)

Galvanic plating principles

„Panel-plating“

Galvanic deposition Barrier & plating base deposition

conformal TSV; DD

Photo-resist

coating & structuring

Galvanic deposition

„Through-mask-plating“

(32)

Atotech Additive

conformal

bottom up

10 x 60 µm

Spherolyte

• Brightener

• Leveller B

• Leveller AT

Copper Electrolyte Composition

60 x 70 µm

Electrolyte TSV

≠

TSV/Pillar = RDL

Spherolyte

• Brightener

• Leveller UF

40 x 50 µm

(33)

Copper Electrolyte Composition

Copper plating of TSV and RDL will require different Chemistry

(34)

TSV Seed layer

• Requirements

• e’less deposition

(35)

Seed layer for TSV

Effect of inhomogene seed layer

_{Effect of inhomogene seed layer}

TSV diameter µm]

+

C u f il li n g d ep th [µm ]

• Seed layer target

• on wafer: d > 200 nm for good within wafer homogenity

• inside TSV

• continuous

• thickness target tbd (plating speed: the thicker the faster)

• wettable

• adhesion to barrier layer

PVD/ CVD show steep learning curve

(36)

35 x 100 µm

Electroless copper on SiON

40/40um

Electroless copper on Photoresist

(+ galvanic copper)

Electroless copper seed layer

• Feasibility of barrier/ seed layer

• long way to go

• Is there really a PVD limitation?

• Relevant TSV dimensions?

• Road map harmonisation appreciated!

(37)

Summary

• Atotech

fully supports TSV

• direct collaboration with semiconductor industry

• 200/300 mm plater for e‘less & galvanic processes in Berlin/ Germany

• “plating for semiconductor” dedicated R&D team

• participation in related academic/ industrial consortia

• understand needs; performance feed back

• Copper TSV

• initial target (void free ; < 1h) √

• target reinforcement required

• e.g. within wafer distribution, overburden, stress, < 30 min, CTE, CoO…

• high quality/quantity TSV wafer supply is a must

• discussion about Atotech’s Fe

2/3+

_{process to reduce Cu-overburden}

• Bumping

• matured technology pieces available, but need to define 3D technology chain

• 3D stacking dedicated performance to be investigated

• reliability: academic consortia; cost target: industry

• e’less seed/ barrier

• infant status

• required: target definition, wafer supply, how to evaluate, …

• SC industry: road map

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Thank you for your attention

Electroplating aspects in 3D IC Technology