Computer Architecture. Mehran Rezaei

Computer Architecture

Mehran Rezaei

Welcome

• Office Hours:

– TBA

• Office: Eng-Building, Last Floor, Room

344

• Tel: 0313 793 4533

• Course Web Site:

Text book

Computer

Organization &

Design:

The

Hardware/Software

Interface

David A. Patterson and John E. Hennessy

5th _{Edition, Morgan Kaufmann,}

2013

http://booksite.elsevier.com/97 80124077263/

Overview

• Intro to Computer Architecture

• Administrative Matters

• Course Style, Philosophy and Structure

• High Level, Assembly, and Machine

Language

• Anatomy of computer system

What is “Computer Architecture”

What is “Computer Architecture”

Computer Architecture =

Instruction Set Architecture +

Machine Organization

Instruction Set Architecture

... the attributes of a [computing] system as seen by the

programmer, i.e. the conceptual structure and

functional behavior, as distinct from the organization

of the data flows and controls the logic design, and

the physical implementation. Amdahl, Blaaw, and

Brooks, 1964

SOFTWARE

-- Organization of Programmable Storage

-- Data Types & Data Structures: Encodings & Representations -- Instruction Set

-- Instruction Formats

-- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions

The Instruction Set: a Critical Interface

instruction set software

hardware

Example ISAs (Instruction Set Architectures)

Alpha (v1, v3, … , ev8)

1992-2003

HP PA-RISC

(v1.1, v2.0) 1986-2003

Sun Sparc (v8, v9)

1987-2003

SGI MIPS(MIPS I, …, IV, V)

1986-96

Intel

1971-2003

(4004, …, 8086, … 80486, Pentium, MMX,

PII, …, PIV, Itanium, Xeon)

MIPS R3000 Instruction Set Architecture

• Instruction Categories

– Computational – Jump and Branch – Floating Point • coprocessor – Memory Management – Special R0 - R31 PC HI LO OP OP OP rs _rt rd sa funct rs _{rt immediate} jump target 3 Instruction Formats: all 32 bits wide

Organization

• Capabilities & Performance Characteristics of

Principal Functional Units

(e.g., Registers, ALU, Shifters, Logic Units, ...)

• Ways in which these components are interconnected

• Information flows between components

Data path

• Logic and means by which such information flow is

controlled.

Control unit

What is “Computer Architecture”?

Coordination of many levels of abstraction

Under a rapidly changing set of forces

Design, Measurement, and Evaluation

I/O system Instr. Set Proc.

Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware

Datapath & Control

Layout

Course Style (overview handout)

• Grade breakdown

– Exams:

60%

– Projects

30%

– Homework Assignments:

20%

• No late homework

• Passing Grade

– Projects + Homework :

necessary requirements

Academic Honesty vs. Cheating

• Don’t cheat

– If you submit something, it should be your own work – Scholarly work

• Give credit to whom you get the idea from

– Plagiarizing is forbidden

• What happens if you cheat

• Department • Provost

• I will give you an F

Course Materials (Systematically)

• Instruction Set Architecture

• CPU design, single cycle and pipelined CPU

• Memory Systems

• Measuring the performance of computer

system

Where are we?

• Intro to Computer Architecture

• Administrative Matters

• Course Style, Philosophy and Structure

• High Level, Assembly, Machine Language

• Anatomy of computer system

High Level Language Program Assembly Language Program Machine Language Program Control Signal Specification Compiler Assembler Machine Interpretation 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 ° °

ALUOP[0:3] <= InstReg[9:11] & MASK

High Level, Assembly, Machine language, and

control signals

Levels of Organization

(computer Anatomy)

25% of cost on Processor 25% of cost on Memory (minimum memory size) Rest on I/O devices,

power supplies, box

Another view

CPU

Cache

Bridge

Controller ControllerVideo ControllerKeyboard

NIC

I/O

Expa-nsion

Secondary

Storage Video

Monitor Keyboard Network

Memory Controller

Example Organization

TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20

Floating-point Unit Integer Unit Inst Cache Ref MMU Data Cache Store Buffer Bus Interface SuperSPARC L2 $ CC MBus Module MBus L64852 MBus control M-S Adapter SBus DRAM Controller SBus DMA SCSI Ethernet STDIO serial kbd mouse audio RTC Boot PROM Floppy SBus Cards

Execution Cycle

Obtain instruction from program storage

Determine required actions and instruction size

Locate and obtain operand data

Compute result value or status

Deposit results in storage for later use

DLQ

(final thoughts) Forces on Computer

Architecture

Technology

History

Applications

A Prediction by Gordon Moore

Courtesy of the graph – Cramming more components

onto integrated circuits, Electronics, 38(8), April 1965

The Growth in CPU Speed

(lately)

Sources: J. S. Emer. “Simultaneous Multithreading: Multiplying Alpha's

Performance”, 12 th Microprocessor Forum, October 1999.

R. E. Kessler. “The Alpha 21264 Microprocessor”, IEEE Micro,

19(2), pp. 2436, March/April 1999.

V. A. Klauser. “Trends in HighPerformance Microprocessor

Design”, Telematik, 7(1), pp. 1221, April 2001.

Chip's nam e 21064 - EV4 21164 - EV5 21264 - EV6 21364 - EV7 21464 - EV8

Introduced 1992 1995 1998 X X

Technology 0.75 - 0.5 m m 0.5 - 0.35 m m 0.35 m m 0.18 m m 0.125 m m

Transistors 1.68 M 9 M 15 M 152 M 250 M

Frequency 150 - 275 MHz 300 - 600 MHz 0.6 - 1 GHz 1.2 - 1.4 GHz 1.2 - 2 GHz Architecture 2-Way In-Order 4-Way In-Order 4-Way Out-Of-Order 4-Way Out-Of-Order 8-Way Out-Of-Order

Pace In Memory Speed

Column Access Strobe (CAS)/

Year of Slowest Fastest data transfer Cycle

Introduction Chip Size DRAM (ns) DRAM (ns) time (ns) time (ns)

1980 64K bit 180 150 75 250 1983 256K bit 150 120 50 220 1986 1M bit 120 100 25 190 1989 4M bit 100 80 20 165 1992 16M bit 80 60 15 120 1996 64M bit 70 50 12 110 1998 128M bit 70 50 10 100 2000 256M bit 65 45 7 90 2002 512M bit 60 40 5 80

Row Access Strobe (RAS)

Courtesy of the table:J. L. Hennessy and D. A. Patterson. ``Computer Architecture: A Quantitative Approach'', Morgan Kaufmann Publishers, Third

CPU-Memory Speed Gap

Courtesy of the Graph:J. L. Hennessy and D. A. Patterson. ``Computer Architecture A Quantitative Approach'', Morgan Kaufmann Publishers, Third

Edition 2003.

Ever-increasing CPU-Mem S-Gap

DLQ

• 5 Stages of Instruction Execution?

• 5 main Components of any computer

system?