Shwetha.M, IJRIT-301 (IJRIT)
www.ijrit.com ISSN 2001-5569
Implementation of I2C/UART Master bus controller
Shwetha.M
M.Tech Student,VLSI Design & Embedded Systems, Srinivas Institute Of Technology, Mangalore, India [email protected]
BhimaShastry
Prof,Head of Dept Electronics & Communication, Srinivas Institute Of Technology, Mangalore, India [email protected]
Abstract — This paper deals with serial data communications using I2C master bus controller. I2C bus replaces complex parallel interfaces with a serial structure and brings a new revolution in chip-to-chip communications.Inter integrated circuit Master bus controller is interfaced with a real time clock called as MAXIM DS1307. This device is considered to be as slave device. The incoming data is multiplexed to 2wire (I2C and UART) communication lines This module is designed in VHDL and Verilog and they are compared in terms of area, timing constraints and resource utilization by synthesizing using Xilinx ISE Design Suit 14.2. I2C can be interfaced with A/D, EEPROM, motherboard or other electronic
Keywords— Real time clock, EEPROM, I2C, master, slave, Spartan3A Xilinx,UART,memory card,aurdino boards.
I. INTRODUCTION
For serial data communication there are many protocols such as RS232, SPI, Microwire etc where these protocols require more pin connection in IC for communication to take place .But as the physical size of the IC reduces less amount of pin connections are required for communication. Hence in order to overcome these problems I2C protocol has been introduced.
I2C is two-wire and bidirectional serial bus which provides data exchange between devices and suitable for communication over short distance.I2C standard is multi master bus which provides collision detection and arbitration and also prevents data corruption if two or more masters attempt to control the bus simultaneously. Transmission speeds supported by I2C are normal (100Kbps), Fast (400Kbps), High speed (3.5Mbps).
I2C is the medium for communication where master controller is used to send data and receive the data from the slave. Slave device can be RTC, EEPROM or any low speed peripherals.
Fig -1 Block diagram of I2C master controller with slave DS1307
Real Time Clock (Slave device) I2CMaster
bus controller in
Spartan3 SCL
SDA addr(7:0)
data(7:0) CLK RST_N
RD WR
Shwetha.M, IJRIT-302 II. PROPOSEDWORK
A. I2C Protocol
I2C bus supports many devices and each device is recognized by its unique address. In figure above data line is of 8 bits and address line is 8 bits. Clock, Reset, RD and WRare the inputs where RD and WR indicates whether master or slave has to transmit the data during communication.
The bus will have SCL: Clock line, SDA: Data line. They are bi-directional lines, connected to a positive supply voltage via a current-source or pull-up resistor [1].Values of pull up resistors depends on supply voltage, bus capacitance. Pull-up resistors maintain the SDA and SCL lines a HIGH level when the bus is free and ensure the signal are pulled up from a LOW to a HIGH level within the required rise time.
The I2C bus is said to be idle when SCL,SDA are at logic1 level.Inorder to start with the communication between master controller and slave device a START sequence i.e High to low transition in SDA and SCL at high level as shown in fig below .
Fig – 2 “START” and “STOP” Sequence B. Modes of Operation
The I2C bus has master transmission and master receiver mode. In transmission mode master sends slave address once after START sequence is generated which includes a direction bit(R/w`). If the address of slave is matched then master will send the actual data once after it receives ACK signal from the corresponding slave device. If ACK bit is high then slave is not ready for acceptance of data from the master. Master will perform write to the slave in this mode.
Fig – 3 Master Transmission Mode
In master receiver mode, first byte is received as seen in transmission mode. However direction bit data transmission in reverse direction In this mode master will read from the slave devices.
Fig – 4 Master Receiver Mode
Fig – 5 Acknowledgement on I2C Bus
Shwetha.M, IJRIT-303 The DS1307 serial real-time clock (RTC) is a low power, full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are transferred serially through an I2C; bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The DS1307 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply. Timekeeping operation continues while the part operates from the backup supply [2].
Fig -6 Pin Assignment of DS1307
Fig – 7 Operating circuit of DS1307
Fig – 8 DS1307 connected to I2C Bus
D. UART
A serial communication protocol that sends parallel data through a serial line. The UART includes both a transmitter and receiver.
The transmitter is a special shift register that loads data in parallel and then shifts it out bit-by-bit. The receiver shifts in data bit-by- bit and reassembles the data byte.[8]
Shwetha.M, IJRIT-304 Fig – 9 Block diagram of UART
III. SOFTWAREIMPLEMENTATION
I2C master controller is designed using Verilog HDL [4] based on Finite State Machine (FSM) [5]. FSM is a sequential circuit that uses a finite number of states to keep track of its history of operations, and based on history of operation and current input, determines the next state. The controller is also designed using VHDL [3] and the resource utilization is noted. Logic utilization includes no of LUTS, Flip-flops GCLKS. However the percentage of these usage while designing using VHDL is more than the controller design using verilog. The data stream which is to be transmitted either in UART or I2C bus is done using multiplexing technique is done .There are several states in obtaining the result.
Algorithm
State 0 : The data is to be transmitted in I2C or UART if bit after address bits is 1 or 0 respectively.
State1 : An idle condition: I2C bus doesn’t perform any operation. (SCL and SDA remains high).
State 2 : Start condition: master initiates data transmission by providing START (SCL is high and SDA is from high to low).
State 3 : Slave address - write: master sends the slave address-write (11010000) to the slave.
State 4 : If the slave address matches with the slave, it sends an acknowledgement bit in response to the master.
State 5 : 8 Bit Register Address[12] will be transmitted to the slave. Again acknowledgement is sent to the master by the slave.
State 6 : Data to be transmitted is sent to the slave by the master. After receiving the data, slave acknowledges the master.
State 7 : Stop condition: Slave sends a stop bit to the master to terminate the communication (SCL is high and SDA is from Low to high).
For performing read operation, write operation is performed first and then read operation is done.
State 8 : Master transmits slave address for read operation to the slave.
State 9 : Master receives the data from the slave and acknowledges the slave.
State 10 : Master sends a STOP bit to terminate the connection
Shwetha.M, IJRIT-305 Fig – 10 Flow Chart for I2C and UART with the slave device
The simulated Verilog and VHDL coding is synthesized on Spartan 3AN through Xilinx ISE Design Suite14.2 [7]. The Spartan-3AN FPGA platform offers non-volatile pin-compatible versions of the Spartan-3A FPGA platform. The Spartan-3AN FPGAs support the same external programming sources as Spartan-3A FPGAs, but add an additional internal SPI [6]Flash programming mode. The internal SPI Flash can also be used for user data. The Spartan-3A/3AN Starter Kit Board supports both external and Spartan-3AN internal configuration options.
Initialize the ports
Set up the clock frequency
Is data Txd/Rxd?
Transmit the data
Is data available at Rx
Receive the data B
B
B A
No
Yes
Yes
No Is I2C or UART?
If reset Deassert
ed
Initialization of register,address,Ack
Idle bus START
Positive edge of Clk
Send START condition (SCL=Logic high,
SDA=HIGH to LOW)
Send 7 bit slave address&W bit
Get Ack from the slave
If Ack is low
Send 8 bit Register address to slave
slave
If Ack low
RW=0
Write data to the slave
Get Ack from the slave
If Ack low
Continue to send the data
address followed by R bit
Read data from the slave
Get Ack from the master
STOP A
NO NO No
NO
No
NO Ye
Yes
Yes
Yes
Shwetha.M, IJRIT-306 Fig – 11 Simulation result for WRITE operation
Fig – 12 Simulation result for READ operation
Shwetha.M, IJRIT-307 Fig – 13 Xilinx Device Utilization summary for Verilog Design
Fig – 14 Xilinx Device utilization Summary for VHDL Design
1V. HARDWARE IMPLEMENTATION
The hardware implementation is done by interfacing DS 1307 with the arduino boards as master devices. It is an 8 pin DIP. A power supply of 5V is given to the slave. Pin 4 is connected to the ground (GND) and pin 8 is connected to the VCC. Pins 5 and 6 are connected to SDA and SCL of I2C master bus in Spartan 3AN. Both SDA and SCL are open drained lines. When multiple masters are connected, both SDA and SCL are in need to be pulled up with a 5.6kΩ resistor to the VCC.
V. RESULTS AND ANALYSIS
In this work, Verilog HDL and VHDL have been used. Logic synthesis and simulation are done in Xilinx 12.2 and Xilinx ISE Simulator.The results are displayed in fig 11 and fig 12. The comparison shows the difference in device utilization. Thus, proposed method outperforms conventional method in terms of area.
Shwetha.M, IJRIT-308 Fig – 15 RTL diagram for READ operation
Fig – 16 RTL diagram for WRITE operation
V1. CONCLUSION
This project shows how master transmits and receives data to and from slave devices .Slave devices can be RTC,memory card,stepper motor,EEPROM,or any low speed peripheral devices. In future,this can also be implemented by using multiple masters or single master multiple slave devices using clock synchronization techniques.
Shwetha.M, IJRIT-309 [1] Philips Semiconductor “I2C Bus Specification” version 2. 1, January 2000
.
[2] Maxim integrated “DS1307 64 x 8, Serial, I2C Real Time Clock”, 2008.
[3] Prof. Jai Karan Singh “Design and Implementation of
I2c master controller on FPGA using VHDL,” IJET,Vol 4 No 4 Aug-Sep 2012.
[4] Stuart Sutherland, “Verilog® HDL Quick Reference Guide”, IEEE Std 1364-2001
[5] MR. J. J PATEL, 2 PROF B. H. SONI 1 P.G. Student, E.C. Dept., 2 Faculty, E.C. Dept.,1, 2 U.V. Patel College of Engineering, kherva [email protected]
[6] A.K. Oudjida, M.L. Berrandjia, R. Tiar, A. Liacha, K. Tahraoui Microelectronics and Nanotechnology Division Centre de Développement des Technologies Avancées, CDTA Algiers, Algeria Email: [email protected]
[7] Xilinx “Spartan-3A/3AN FPGA Starter Kit Board User Guide,”version 1.1,2008
[8] www.avrbeginners.net/architecture/uart/uart.htm
