Lenovo Z50-70 NM-A273 ACLUA_MB_20131231.pdf

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A A B B C C D D E E 1 1 2 2 3 3 4 4

Intel Haswell/Broadwell U-Processor with DDRIIIL + NV (N15V-GM/N15S-GT) GPU

ACLUA M/B Schematics Document

2013-12-26

REV:0.3

LCFC Confidential

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

Cover Page

Custom 1 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

Cover Page

Custom 1 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

Cover Page

Custom 1 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Confidential

(2)

A B C D E

1 1

2 2

3 3

4 4

File Name : ACLUA

LCFC confidential

DPx2 Lane

SATA Gen1

SATA ODD

RTL8106EUL (10M/100M)

RTL8111GUL (1G)

Codec

UP TO 8G x 2

DDR3L-SO-DIMM X2

Page 14,15

SD/MMC Conn.

8MB

PCI-Express

USB Board

POWER BOARD

Sub-board ( for 15")

ODD Board

USB Board

POWER BOARD

Sub-board ( for 14")

SPK Conn.

Touch Screen

NV (N15V-GM/N15S-GT)

DDR3L*8 4GB/2GB/1GB

VRAM 256/128*16

Broadwell U 15W

BGA-1168

40mm*24mm

Cardreader Realtek

RTS5170

EC

ITE IT8586E-LQFP

Touch Pad

Int.KBD

Thermal Sensor

NCT7718W

HDMI Conn.

4x Gen2

USB Left

USB 2.0 2x

USB Right

USB 3.0 1x

NGFF Card

WLAN&BT

USB 2.0 1x

PCIe 1x

SATA Gen3

SATA HDD

Conexant CX20752

HD Audio

Int. MIC Conn.

HP&Mic Combo Conn.

SPI ROM

SPI BUS

PCIe 1x

LAN Realtek

RJ45 Conn.

Memory BUS (DDR3L)

Dual Channel

1.35V DDR3L 1600 MT/s

USB2.0 1x

USB 3.0 Port1

Intel MCP

HDMI

GB2B-64 Package

DP to VGA

Parade PS8613

VGA Conn.

USB Board

USB Board

eDP x2 Lane

eDP Conn

USB2.0 1x

USB2.0 1x

USB 2.0 1x

USB2.0 Port5

SATA Port0

Int. Camera

SATA Port1

PCIe Port3

USB2.0 Port4

USB2.0 Port0

USB2.0 Port3

USB2.0 Port6

PCIe Port4

Page 18~28

Page 24~27

Page 34

Page 35

Page 36

Page 33

Page 42

Page 42

Page 37

Page 38

Page 43

Page 43

Page 33

Page 40

Page 07

Page 45

Page 45

Page 44

Page 39

Page 3~13

Page 41

USB 2.0 Port1

USB 2.0 Port2

Haswell U 15W /

SPI ROM 4MB

Page 07

for reserve

PCIe Port5

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

Block Diagram

Custom 2 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

Block Diagram

Custom 2 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

Block Diagram

Custom 2 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Confidential

(3)

A A B B C C D D E E 1 1 2 2 3 3 4 4

VGA

V

X

X

SODIMM

BATT

IT8586E

Thermal

Sensor

PCH

WLAN

WiMAX

S5 S4/AC Only

S3

S0

PCH

IT8586E

+3VS

B+

S5 S4

AC & Battery

don't exist

S5 S4

Battery only

V

+1.35V

+5VALW

+3VALW

+3VALW_PCH

O

O

O

O

X

O

O

O

O

+3VGS

V

EC_SMB_DA2

EC_SMB_CK2

X

X

O

X

X

X

V

X

X

X

X

PCH_SMB_CLK

SMBUS Control Table

+3VALW_PCH

V

V

X

TP

Module

V

X

X

X

X

X

14@

For 15" part

X

X

15@

For 14" part

X

X

BOM Structure

BTO Item

BOM Structure Table

X

+3VS

+3VS

+3VALW_PCH

X

+3VS

+3VS

, X --> Means OFF )

( O --> Means ON

PCH 0001 0010 b Charger Wlan Rsvd need to update

O

S3

Battery only

+3VALW_PCH

O

X

O

O

O

O

X

X

X

AOAC@

AOAC support part

100M LAN Part

100M@

N15SGT@

ME@

UMA@

OPT@

GIGA@

TS@

N15VGM@

RANKB@

RANKA@

Not stuff

ME part(connector, hole)

UMA SKU part

Discrete GPU SKU part

GIGA LAN Part

@

For support touch panel sku part

For N15V-GM part

For VRAM RankB part

For VRAM RankA part

For N15S-GT GPU part

4

LAN

2

3

5

1

USB Port1 (Left Side)

PCIE PORT LIST

WLAN

Device

Port

Camera

USB 2.0

USB 3.0

USB Port (Right Side)

5

4

2

1

0

7

6

EHCI1

USB Port Table

NGFF(WLAN)

XHCI

3

0x41(default) VGA

TOUCH PANEL

Cardreader

USB Port2 (Left Side)

Discrete GPU

6

2

1

X

PCH_SMB_DATA

USB Port1 (Left Side)

4

3

+0.95VGS

+1.5VS

O

+3VALW

V

V

charger

V

+3VGS

+1.35VGS

+0.675VS

X

EC_SMB_DA1

EC_SMB_CK1

IT8586E

SOURCE

+3VALW

SLP_S5#

SLP_S4#

SLP_S3#

SLP_S1#

S5 (Soft OFF)

S4 (Suspend to Disk)

S3 (Suspend to RAM)

S1(Power On Suspend)

Full ON

SIGNAL

STATE

ON

ON

ON

ON

ON

ON

ON

Voltage Rails

Clock

+VS

+V

+VALW

LOW

LOW

LOW

LOW

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

ON

ON

ON

HIGH

HIGH

HIGH

HIGH

HIGH

HIGH

HIGH

HIGH

HIGH

LOW

LOW

LOW

LOW

LOW

LOW

LOW

State

O

Power Plane

CPU_CORE

+5VS

+3VS

HIGH

PCH SM Bus address

1010 010Xb DDR DIMMB 1010 000Xb DDR DIMMA

Device

EC SM Bus1 address

1001_100xb Thermal Sensor NCT7718W

+VGA_CORE

+1.05VS

+1.8VGS

+1.35VS

0X16 Smart Battery

Device

EC SM Bus2 address

Address

Address

Device

GC62.0 support part

GC6@

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

Notes List

Custom 3 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

Notes List

Custom 3 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

Notes List

Custom 3 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Confidential

(4)

5 4 3 2 1 D D C C B B A A DDPx_CTRLDATA

The signal has a weak internal pull-down. H Port is detected.

L Port is not detected.

*

DP TO VGA Converter

+VCCIOA_OUT & EDP_COMP : Trace Width: 20mil Space: 25mil Max length: 100mil

HDMI CLK

HDMI D0

HDMI D1

HDMI D2

Reserve for NV GPU

After confirm with vendor, HPD

has internal pull-down ~100K at

PS8613, just reserve in case.

RC37 can be removed next phase

if no issue.

EDP_COMP LCD_BKLT_CTRL_R PCI_PIRQD# PCI_PIRQB# PCI_PIRQA# PCI_PIRQC# CPU_EDP_AUX CPU_EDP_AUX# CPU_EDP_TX0-CPU_EDP_TX0+ CPU_EDP_TX1+ CPU_EDP_TX1-DDPB_CLK DDPB_DATA HDMI_HPD EDP_HPD EDP_HPD PCH_EDP_PW M PCH_ENVDD GPIO52 PXS_PW REN PXS_PW REN_R PXS_RST#_R PXS_RST#_R PXS_RST# VGA_TX1+ VGA_TX0+ VGA_TX1- VGA_TX0-VGA_AUX VGA_AUX# GPIO53 PXS_PW REN_R GPIO52 GPIO53 DDPC_CLK DDPC_DATA PCH_ENBKL PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# HDMI_TX2-HDMI_TX2+ HDMI_TX1+ HDMI_TX0+ HDMI_CLK-HDMI_CLK+ HDMI_TX1- HDMI_TX0-BOARD_ID3 PXS_RST#_R PXS_PW REN_R GPIO52 GPIO53 VGA_HPD DDPB_DATA DDPB_CLK DDPC_CLK DDPC_DATA INVT_PW M 33 CPU_EDP_AUX# 33 CPU_EDP_AUX 33 CPU_EDP_TX0- 33 CPU_EDP_TX0+ 33 CPU_EDP_TX1+ 33 CPU_EDP_TX1- 33 DDPB_DATA 34 HDMI_HPD 34 CPU_EDP_HPD 33 PCH_ENBKL 33 PCH_ENVDD 33 PCH_EDP_PW M 33 PXS_PW REN 21,58 PXS_RST# 19 VGA_AUX# 35 VGA_AUX 35 VGA_HPD 35 DDPB_CLK 34 HDMI_TX2-34 HDMI_TX2+ 34 HDMI_TX1-34 HDMI_TX1+ 34 HDMI_TX0-34 HDMI_TX0+ 34 HDMI_CLK-34 HDMI_CLK+ 34 VGA_TX0-35 VGA_TX0+ 35 VGA_TX1-35 VGA_TX1+ 35 VGA_GATE# 44 BOARD_ID3 9 GPIO53 19 GPIO52 19 +VCCIOA_OUT +3VS +3VS +3VS +3VS +3VS

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (DDI,EDP)

Custom 4 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (DDI,EDP)

Custom 4 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (DDI,EDP)

Custom 4 59 Thursday, December 26, 2013 2013/08/08 2013/08/05 RC27 1 @ 2 10K_0402_5% RC37 100K_0402_5% @ 1 2 RC17 2 @ 1 100K_0402_5% RC170 0_0402_5% @ 1 2 RC9 1M_0402_5% @ 1 2 RC30 1 @ 2 10K_0402_5% CC96 .1U_0402_10V6-K @ 1 2 TC1 PAD @ 1 G D S QC13 2N7002KW _SOT323-3 @ 2 1 3 RPC19 2.2K_0804_8P4R_5% 1 8 2 7 3 6 4 5 G D S QC4 2N7002KW _SOT323-3 @ 2 1 3 RC1 1 224.9_0402_1% RC8 1 OPT@20_0402_5% RC7 1 OPT@21K_0402_5% RC10 10K_0402_5% N15VGM@ 1 2 RC18 2 1 100K_0402_5% RC13 100K_0402_5% 1 2 RC11 1 2 10K_0402_5% RC2 1 @ 20_0402_5% RPC1 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC14 1 2 10K_0402_5% RC16 0_0402_5% @ 1 2 HSW_ULT_DDR3L eDP SIDEBAND PCIE DISPLAY 9 OF 19 UC1I HASWELL-ULT-DDR3L_BGA1168 DDPC_AUXN B6 DDPC_AUXP A6 DDPB_AUXP B5 EDP_BKLEN A9 GPIO53 L4 GPIO51 R5L3 GPIO54 GPIO52 L1 GPIO55 U7 PME AD4N2 PIRQD/GPIO80 PIRQC/GPIO79 N4 DDPB_CTRLCLK B9 DDPB_CTRLDATA C9 DDPC_CTRLCLK D9 DDPC_CTRLDATA D11 DDPB_HPD C8 EDP_HPD D6 DDPC_HPD A8 DDPB_AUXN C5 EDP_VDDEN C6 EDP_BKLCTL B8 PIRQA/GPIO77 U6 PIRQB/GPIO78 P4 HSW_ULT_DDR3L EDP DDI 1 OF 19 UC1A HASWELL-ULT-DDR3L_BGA1168 DDI1_TXN0 C54 DDI1_TXP0 C55 DDI1_TXN1 B58 DDI1_TXP1 C58 DDI1_TXN2 B55 DDI1_TXP2 A55 DDI1_TXN3 A57 EDP_TXP0 B46 EDP_TXN0 C45 EDP_TXN1 A47 EDP_TXP1 B47 EDP_TXN2 C47 EDP_TXP2 C46 EDP_TXN3 A49 EDP_TXP3 B49 EDP_AUXP B45 EDP_AUXN A45 DDI1_TXP3 B57 DDI2_TXP1 B54 DDI2_TXP0 C50 DDI2_TXN0 C51 DDI2_TXN1 C53 DDI2_TXN2 C49 DDI2_TXP2 B50 DDI2_TXN3 A53 DDI2_TXP3 B53 EDP_RCOMP D20 EDP_DISP_UTIL A43 RC15 1 @ 2 10K_0402_5%

Confidential

(5)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A H_PROCHOT#_R PROC_DETECT# CPU_PROCPWRGD SM_RCOMP_1 SM_RCOMP_2 SM_RCOMP_0 SM_PG_CNTL1 CATERR# XDP_TCLK XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PREQ# XDP_PRDY# XDP_BPM3# XDP_BPM5# XDP_BPM2# XDP_BPM1# XDP_BPM0# XDP_BPM4# XDP_BPM6# XDP_BPM7# DDRA_ODT0 DDRA_ODT1 DDR_ODT DDRB_ODT0 DDRB_ODT1 H_PECI SM_RCOMP_0 SM_RCOMP_2 SM_RCOMP_1 SM_PG_CNTL1 CPU_DRAMRST#_R H_PECI 44 H_PROCHOT# 44,51,52 CPU_DRAMPG_CNTL 55 DDRA_ODT0 14 DDRA_ODT1 14 DDRB_ODT0 15 DDRB_ODT1 15 CPU_DRAMRST# 14,15 +3VALW +1.35V +1.05V_VCCST +1.35V +1.35V

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

MCP (MISC,THERMAL,JATG)

Custom 5 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

MCP (MISC,THERMAL,JATG)

Custom 5 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

MCP (MISC,THERMAL,JATG)

Custom 5 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

TC11 PAD@ 1 CC1 0.01U_0402_25V7K 1 2 TC4 PAD@ 1 RD4 1 2 66.5_0402_1% RC23 0_0402_5% @ 1 2 RC21 10K_0402_5% 1 2 RC28 100K_0402_5% 1 2 E B C QC14 MMBT3904WH_SOT323-3 2 3 1 TC5 PAD@ 1 TC12 PAD@ 1 TC16 PAD@ 1 RC26 200_0402_1% 2 1 RD3 1 2 66.5_0402_1% DDR3L HSW_ULT_DDR3L MISC THERMAL PWR JTAG 2 OF 19 UC1B HASWELL-ULT-DDR3L_BGA1168 BPM#4 K59 BPM#5 H63 BPM#6 K60 SM_RCOMP0 AU60 BPM#7 J61 BPM#3 H62 BPM#1 H60 BPM#2 H61 BPM#0 J60 PROC_TDO F62 PROC_TDI F63 PROC_TMS E61 PECI N62 CATERR K61 PROCPWRGD C61 PROCHOT K63 PROC_TRST E59 PROC_TCK E60 PRDY J62 PREQ K62 SM_PG_CNTL1 AV61 SM_DRAMRST AV15 SM_RCOMP2 AU61 SM_RCOMP1 AV60 PROC_DETECT D61 TC6 PAD@ 1 TC2@ 1 RC3 1K_0402_5% 1 2 RC22 470_0402_5% 1 2 TC7 PAD@ 1 TC14 PAD@ 1 TC8 PAD@ 1 RC25 121_0402_1% 2 1 RC24 100_0402_1% 2 1 TC18 PAD@ 1 RD2 1 2 66.5_0402_1% TC17 PAD@ 1 RC29 10K_0402_5% @ 1 2 TC9 PAD@ 1 RC20 56_0402_5% 1 2 RD1 1 2 66.5_0402_1% TC10 PAD@ 1 TC15 PAD@ 1 CD1 .1U_0402_10V6-K @ 1 2 RC31 0_0402_5% @ 1 2 RC19 62_0402_1% 1 2 G D S QC5 PJA138K_SOT23-3 2 1 3 TC3@ 1 TC13 PAD@ 1

Confidential

(6)

5 4 3 2 1 D D C C B B A A

WIDTH:20MIL

SPACING: 20MIL

SMVREF

SB_ODT0 SA_ODT0 DDRA_MA15 DDRA_MA0 DDRA_MA14 DDRA_MA5 DDRA_MA4 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA9 DDRA_MA7 DDRA_MA6 DDRA_MA12 DDRA_MA13 DDRA_MA8 DDRA_MA11 DDRA_MA10 DDRB_MA15 DDRB_MA9 DDRB_MA7 DDRB_MA0 DDRB_MA13 DDRB_MA2 DDRB_MA4 DDRB_MA11 DDRB_MA3 DDRB_MA5 DDRB_MA6 DDRB_MA10 DDRB_MA8 DDRB_MA1 DDRB_MA12 DDRB_MA14 DDRA_DQ4 DDRA_DQ7 DDRA_DQ1 DDRA_DQ5 DDRA_DQ6 DDRA_DQ8 DDRA_DQ3 DDRA_DQ0 DDRA_DQ2 DDRA_DQ10 DDRA_DQ14 DDRA_DQ15 DDRA_DQ9 DDRA_DQ13 DDRA_DQ12 DDRA_DQ11 DDRA_DQ16 DDRA_DQ26 DDRA_DQ27 DDRA_DQ31 DDRA_DQ25 DDRA_DQ24 DDRA_DQ20 DDRA_DQ30 DDRA_DQ18 DDRA_DQ23 DDRA_DQ29 DDRA_DQ28 DDRA_DQ19 DDRA_DQ21 DDRA_DQ17 DDRA_DQ22 DDRA_DQ43 DDRA_DQ42 DDRA_DQ46 DDRA_DQ47 DDRA_DQ35 DDRA_DQ45 DDRA_DQ44 DDRA_DQ39 DDRA_DQ34 DDRA_DQ37 DDRA_DQ36 DDRA_DQ38 DDRA_DQ40 DDRA_DQ41 DDRA_DQ33 DDRA_DQ32 DDRA_DQ62 DDRA_DQ63 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ56 DDRA_DQ60 DDRA_DQ61 DDRA_DQ48 DDRA_DQ51 DDRA_DQ54 DDRA_DQ55 DDRA_DQ53 DDRA_DQ52 DDRA_DQ49 DDRA_DQ50 DDRB_DQ14 DDRB_DQ10 DDRB_DQ13 DDRB_DQ4 DDRB_DQ0 DDRB_DQ11 DDRB_DQ15 DDRB_DQ3 DDRB_DQ7 DDRB_DQ9 DDRB_DQ8 DDRB_DQ2 DDRB_DQ6 DDRB_DQ1 DDRB_DQ12 DDRB_DQ5 DDRB_DQ24 DDRB_DQ29 DDRB_DQ26 DDRB_DQ21 DDRB_DQ27 DDRB_DQ25 DDRB_DQ23 DDRB_DQ30 DDRB_DQ18 DDRB_DQ19 DDRB_DQ17 DDRB_DQ28 DDRB_DQ22 DDRB_DQ31 DDRB_DQ20 DDRB_DQ16 DDRB_DQ42 DDRB_DQ33 DDRB_DQ43 DDRB_DQ34 DDRB_DQ44 DDRB_DQ46 DDRB_DQ40 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ47 DDRB_DQ39 DDRB_DQ45 DDRB_DQ32 DDRB_DQ38 DDRB_DQ41 DDRB_DQ63 DDRB_DQ59 DDRB_DQ53 DDRB_DQ55 DDRB_DQ57 DDRB_DQ49 DDRB_DQ48 DDRB_DQ50 DDRB_DQ60 DDRB_DQ56 DDRB_DQ51 DDRB_DQ52 DDRB_DQ62 DDRB_DQ54 DDRB_DQ61 DDRB_DQ58 DDRA_DQS#7 DDRA_DQS#4 DDRA_DQS#1 DDRA_DQS#3 DDRA_DQS#5 DDRA_DQS#2 DDRA_DQS#0 DDRA_DQS#6 DDRA_DQS0 DDRA_DQS2 DDRA_DQS7 DDRA_DQS3 DDRA_DQS4 DDRA_DQS5 DDRA_DQS6 DDRA_DQS1 DDRB_DQS#4 DDRB_DQS#5 DDRB_DQS#7 DDRB_DQS#1 DDRB_DQS#2 DDRB_DQS#6 DDRB_DQS#3 DDRB_DQS4 DDRB_DQS5 DDRB_DQS0 DDRB_DQS1 DDRB_DQS7 DDRB_DQS6 DDRB_DQS2 DDRB_DQS3 DDRB_DQS#0 DDRA_DQS#[0..7] DDRA_DQS[0..7] DDRB_DQS#[0..7] DDRB_DQS[0..7] DDRB_BS1# 15 DDRB_BS0# 15 DDRB_BS2# 15 DDRB_CAS# 15 DDRB_RAS# 15 DDRB_W E# 15 DDRB_CLK0# 15 DDRB_CLK0 15 DDRB_CLK1 15 DDRB_CKE0 15 DDRB_CLK1# 15 DDRB_CKE1 15 DDRB_CS1# 15 DDRB_CS0# 15 DDR_SB_VREFDQ 15 DDR_SM_VREFCA 14 DDRA_DQ[0..15] 14 DDRA_CKE0 14 DDRA_CLK0 14 DDRA_CLK0# 14 DDRA_CLK1 14 DDRA_CLK1# 14 DDRA_CKE1 14 DDRA_CS0# 14 DDRA_CS1# 14 DDRA_RAS# 14 DDRA_W E# 14 DDRA_CAS# 14 DDRA_BS0# 14 DDRA_BS1# 14 DDRA_BS2# 14 DDRA_MA[0..15] 14 DDR_SA_VREFDQ 14 DDRA_DQ[32..47] 14 DDRB_MA[0..15] 15 DDRB_DQ[0..15] 15 DDRA_DQ[16..31] 14 DDRB_DQ[16..31] 15 DDRA_DQ[48..63] 14 DDRB_DQ[32..47] 15 DDRB_DQ[48..63] 15 DDRA_DQS#[0..7] 14 DDRA_DQS[0..7] 14 DDRB_DQS#[0..7] 15 DDRB_DQS[0..7] 15

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (DDR3L)

Custom 6 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (DDR3L)

Custom 6 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (DDR3L)

Custom 6 59 Thursday, December 26, 2013 2013/08/08 2013/08/05 TC20PAD@ 1 HSW_ULT_DDR3L DDR CHANNEL A 3 OF 19 UC1C HASWELL-ULT-DDR3L_BGA1168 SM_VREF_DQ0 AR51 SM_VREF_DQ1 AP51 SM_VREF_CA AP49 SA_DQSP7 AL49 SA_DQSP5 AW53 SA_DQSP6 AL42 SA_DQSP2 AN58 SA_DQSP3 AN55 SA_DQSP4 AW57 SA_DQSP0 AJ62 SA_DQSP1 AN61 SA_DQSN6 AL43 SA_DQSN7 AL48 SA_DQSN4 AV57 SA_DQSN5 AV53 SA_DQSN3 AM55 SA_DQSN1 AN62 SA_DQSN2 AM58 SA_DQSN0 AJ61 SA_MA15 AU42 SA_MA13 AR35 SA_MA14 AV42 SA_MA10 AP35 SA_MA12 AU41 SA_MA11 AW41 SA_MA8 AY39 SA_MA9 AU40 SA_MA6 AV40 SA_MA7 AW39 SA_MA5 AR36 SA_MA4 AU39 SA_MA3 AP36 SA_MA2 AR38 SA_MA0 AU36 SA_MA1 AY37 SA_BA2 AY41 SA_BA1 AV35 SA_BA0 AU35 SA_WE AW34 SA_CAS AU34 SA_RAS AY34 SA_ODT0 AP32 SA_CS#0 AP33 SA_CS#1 AR32 SA_CKE3 AY43 SA_CKE0 AU43 SA_CKE1 AW43 SA_CKE2 AY42 SA_DQ15 AP60 SA_DQ63 AK51 SA_DQ62

AM51AK48 SA_DQ61 SA_DQ60 AM48AK49 SA_DQ59 SA_DQ58 AM49AK46 SA_DQ57 SA_DQ56

AM46 SA_DQ55

AM42 SA_DQ54

AM40AK43 SA_DQ53 SA_DQ52

AK45 SA_DQ51

AM45 SA_DQ50

AM43AK42 SA_DQ49 SA_DQ48 AK40 SA_DQ47 AU52 SA_DQ46 AV52 SA_DQ45 AU54 SA_DQ44 AV54 SA_DQ43

AW52AY52 SA_DQ42 SA_DQ41 AW54AY54 SA_DQ40 SA_DQ39

AU56 SA_DQ38

AV56 SA_DQ37

AU58 SA_DQ36

AV58 SA_DQ35

AW56AY56 SA_DQ34 SA_DQ33 AW58AY58 SA_DQ32 SA_DQ31 AN54 SA_DQ30 AR54 SA_DQ29 AK55 SA_DQ26 AM54 SA_DQ27 AK54 SA_DQ24 AP55 SA_DQ23 AN57 SA_DQ22 AR57 SA_DQ21 AK58 SA_DQ20 AL58 SA_DQ19 AK57 SA_DQ18

AM57AR58 SA_DQ17 SA_DQ16 AP58

SA_DQ14

AP61 SA_DQ13

AM60 SA_DQ12

AM61AP62 SA_DQ11 SA_DQ10

AP63 SA_DQ9

AM62 SA_DQ8

AM63AK60 SA_DQ7 SA_DQ6 AK61 SA_DQ5 AH60 SA_DQ3 AK62 SA_DQ2 AK63 SA_DQ1 AH62 SA_DQ0 AH63 SA_CLK#0 AU37 SA_CLK0 AV37 SA_CLK#1 AW36 SA_CLK1 AY36 SA_DQ28 AL55 SA_DQ25 AR55 SA_DQ4 AH61 HSW_ULT_DDR3L DDR CHANNEL B 4 OF 19 UC1D HASWELL-ULT-DDR3L_BGA1168 SB_DQ14 AV25 SB_DQSN5 AV18 SB_DQSN7 AN18 SB_DQSP4 AV22 SB_DQSP5 AW18 SB_DQSP6 AM21 SB_DQSP3 AM25 SB_DQSP7 AM18 SB_DQSP2 AM28 SB_DQSP0 AV30 SB_DQSP1 AW26 SB_DQSN6 AN21 SB_DQSN2 AN28 SB_DQSN3 AN25 SB_DQSN4 AW22 SB_DQSN1 AV26 SB_DQSN0 AW30 SB_MA14 AR46 SB_MA15 AP46 SB_MA13 AK33 SB_MA9 AU46 SB_MA10 AK36 SB_MA11 AV47 SB_MA8 AY47 SB_MA12 AU47 SB_MA4 AR45 SB_MA5 AP45 SB_MA6 AW46 SB_MA3 AR42 SB_MA7 AY46 SB_MA2 AP42 SB_MA0 AP40 SB_MA1 AR40 SB_BA2 AU49 SB_WE AK35 SB_CAS AM33 SB_BA0 AL35 SB_BA1 AM36 SB_RAS AM35 SB_CS#1 AK32 SB_ODT0 AL32 SB_CS#0 AM32 SB_CKE1 AU50 SB_CKE2 AW49 SB_CKE3 AV50 SB_CKE0 AY49 SB_CK#1 AK38 SB_CK1 AL38 SB_CK0 AN38 SB_CK#0 AM38 SB_DQ61 AM20 SB_DQ63 AP18 SB_DQ62 AR18 SB_DQ57 AR20 SB_DQ56 AN20 SB_DQ58 AK18 SB_DQ59 AL18 SB_DQ60 AK20 SB_DQ51 AM22 SB_DQ52 AN22 SB_DQ53 AP21 SB_DQ54 AK21 SB_DQ55 AK22 SB_DQ46 AV17 SB_DQ47 AU17 SB_DQ48 AR21 SB_DQ49 AR22 SB_DQ50 AL21 SB_DQ45 AU19 SB_DQ41 AW19 SB_DQ42 AY17 SB_DQ43 AW17 SB_DQ44 AV19 SB_DQ40 AY19 SB_DQ36 AV23 SB_DQ37 AU23 SB_DQ38 AV21 SB_DQ39 AU21 SB_DQ35 AW21 SB_DQ31 AL25 SB_DQ32 AY23 SB_DQ33 AW23 SB_DQ30 AK25 SB_DQ34 AY21 SB_DQ26 AR25 SB_DQ25 AR26 SB_DQ27 AP25 SB_DQ28 AK26 SB_DQ29 AM26 SB_DQ20 AR29 SB_DQ21 AN29 SB_DQ22 AR28 SB_DQ23 AP28 SB_DQ24 AN26 SB_DQ15 AU25 SB_DQ16 AM29 SB_DQ17 AK29 SB_DQ18 AL28 SB_DQ19 AK28 SB_DQ10 AY25 SB_DQ11 AW25 SB_DQ13 AU27 SB_DQ5 AU31 SB_DQ7 AU29 SB_DQ8 AY27 SB_DQ9 AW27 SB_DQ0 AY31 SB_DQ1 AW31 SB_DQ2 AY29 SB_DQ3 AW29 SB_DQ4 AV31 SB_DQ12 AV27 SB_DQ6 AV29 TC19PAD@ 1

Confidential

(7)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A IREF&RCOMP Width: 12-15Mil Space:12Mil Length: 500Mil

DIMM1, DIMM2, NGFF

INTVRMEN

H Integrated VRM enable (Default) L Integrated VRM disable (INTVRMEN should always be pull high.)

*

CRYSTAL

1, Space 15MIL 2, No trace under crystal

3, Place on oppsosit side of MCP for temp influence

HDA_SDO This signal has a weak internal pull-down. 0 = Enable security measures defined in the Flash Descriptor. 1 = Disable Flash Descriptor Security(override). This strap should only be asserted high during external pull-up in manufacturing/debug environments ONLY.

*

For EMI

HDD

ODD

GPU, EC, Thermal Sensor

1. If support DS3, connect to +3VS and don't support EC mirror code; 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

+3V_SPI

*

ODD_DETECT# SATA2GP SATA3GP PCH_JTAG_TCK SM_INTRUDER# SRTC_RST# RTC_RST# HDA_SDIN0 SATALED# HDA_RST# HDA_SYNC HDA_BCLK INTVRMEN SATA0GP HDA_SDOUT RTC_X2 RTC_X1 SML0_ALERT# SML0_CLK SML0_DATA SML1_ALERT# PCH_SML1_CLK PCH_SML1_DAT PCH_SMB_DATA PCH_SMB_CLK SMB_ALERT# RTC_X2 RTC_X1 HDA_SDIN0 HDA_SDOUT PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAGX PCH_JTAG_TRST# SATA_RCOMP SPI_CS0# SPI_CLK SPI_CLK_R SPI_CS0#_R SPI_SO SPI_SI SPI_SO_R SPI_SI_R SRTC_RST# RTC_RST# SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PRX_DTX_P1 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PRX_DTX_N1 SPI_CS0# SPI_SO SPI_W P# SPI_HOLD# SPI_CLK SPI_SI SPI_W P#_R SPI_HOLD#_R PCH_SMB_DATA PCH_SMB_CLK PCH_SML1_DAT PCH_SML1_CLK SML0_DATA SML0_CLK SMB_ALERT# SML1_ALERT# SML0_ALERT# SPI_CLK_1 SPI_CLK_1 SPI_CS1#_R SPI_CS1# SPI_CS1# SPI_SI_1 SPI_SO_1 SPI_SI_1 SPI_SO_1 SPI_HOLD#_R SPI_W P#_R SPI_W P#_1 SPI_HOLD#_1 SPI_W P#_1 SPI_HOLD#_1 SPI_W P#_R SPI_HOLD#_R SPI_W P# SPI_HOLD# SATA2GP SATA3GP ODD_DETECT# SATA0GP HDA_BITCLK_AUDIO 43 HDA_SYNC_AUDIO 43 HDA_RST_AUDIO# 43 HDA_SDIN0 43 HDA_SDOUT_AUDIO 43 LPC_AD0 44 LPC_AD1 44 LPC_AD2 44 LPC_AD3 44 LPC_FRAME# 44 ME_FLASH 44 SATA_PTX_DRX_N0 42 SATA_PRX_DTX_P0 42 SATA_PRX_DTX_N0 42 SATA_PTX_DRX_P0 42 SATA_PTX_DRX_P1 42 SATA_PTX_DRX_N1 42 SATA_PRX_DTX_P1 42 SATA_PRX_DTX_N1 42 ODD_DETECT# 42 SPI_CLK 44 SPI_CS0# 44 SPI_SI 44 SPI_SO 44 SMB_CLK_S3 14,15,40 SMB_DATA_S3 14,15,40 EC_SMB_CK2 19,39,44 EC_SMB_DA2 19,39,44 +1.05VS_PSATA3PLL +3VS +3VALW _PCH +3V_SPI VCCRTC VCCRTC +3V_SPI +3VS +3VALW _PCH +3VS +3VS +3VALW _PCH +3VS +3VALW _PCH +3VS +3VALW _PCH +3V_SPI +3V_SPI +3V_SPI

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (RTC&AUDIO&SATA&SMBUS)

C 7 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (RTC&AUDIO&SATA&SMBUS)

C 7 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (RTC&AUDIO&SATA&SMBUS)

C 7 59 Thursday, December 26, 2013 2013/08/08 2013/08/05 TC24 @1 TC22 @1 RC1761 @ 233_0402_5% RC1741 @ 20_0402_5% RC47 1 @ 21K_0402_5% RC451 233_0402_5% RC56 2.2K_0402_5% 1 2 RC180 1K_0402_5% @ 1 2 RC48 2 13.01K_0402_1% CC7 10P_0402_50V8J @1 2 RC551 @ 233_0402_5% RC421 233_0402_5% RC49 1 @ 210K_0402_5% CC4 15P_0402_50V8J 1 2 TC28 @1 RC35 2 12.2K_0402_5% RC51 0_0402_5% @ 1 2 JME1 SHORT PADS @ 1 2 RC501 215_0402_5% G D S QC3A 2N7002KDW H_SOT363-6 2 6 1 UC6 W 25Q32FVSSIG_SO8 @ CS 1 DO(IO1) 2 WP(IO2) 3 GND 4 VCC 8 HOLD/RST(IO3) 7 CLK 6 DI(IO0) 5 RPC2 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 JCMOS1 SHORT PADS @ 1 2 RC1731 @ 233_0402_5% TC21 @1 TC33 @1 RC36 2 12.2K_0402_5% G D S QC3B 2N7002KDW H_SOT363-6 5 3 4 RC61 1K_0402_5% 1 2 TC32 @1 RC62 2.2K_0402_5% 1 2 RC541 @ 233_0402_5% RC171 0_0402_5% 1 2 RC46 0_0402_5% @ 1 2 RC1751 @ 233_0402_5% RC172 0_0402_5% @ 1 2 RC521 215_0402_5% RC33 1 220K_0402_1% RC63 2.2K_0402_5% 1 2 RC1781 @ 233_0402_5% RC1771 @ 233_0402_5% RC57 2.2K_0402_5% 1 2 HSW_ULT_DDR3L JTAG RTC AUDIO SATA 5 OF 19 UC1E HASWELL-ULT-DDR3L_BGA1168 RSVD3 L11 RSVD4 K10 PCH_TMS AD62 PCH_TDO AE61 PCH_TDI AD61 PCH_TCK AE62 PCH_TRST AU62 HDA_DOCK_RST/I2S1_SFRM AV10 HDA_DOCK_EN/I2S1_TXD AW10 HDA_SDI1/I2S1_RXD AU12 HDA_SDO/I2S0_TXD AU11 HDA_SDI0/I2S0_RXD AY10AU8 HDA_RST/I2S_MCLK HDA_SYNC/I2S0_SFRM AV11AW8 HDA_BCLK/I2S0_SCLK

RSVD2 AC4 RSVD1 AL11 RSVD0 AV2 I2S1_SCLK AY8 SATALED U3 JTAGX AE63 RTCX2 AY5 SATA_RCOMP C12 SATA_IREF A12 SATA3GP/GPIO37 AC1 SATA2GP/GPIO36 V6 SATA1GP/GPIO35 U1 SATA0GP/GPIO34 V1 SATA_TP3/PETP6_L0 D17 SATA_TN3/PETN6_L0 C17 SATA_RP3/PERP6_L0 E5 SATA_RN3/PERN6_L0 F5 SATA_TP2/PETP6_L1 C15 SATA_TN2/PETN6_L1 B14 SATA_RN2/PERN6_L1 J6 SATA_RP2/PERP6_L1 H6 SATA_TP1/PETP6_L2 B17 SATA_TN1/PETN6_L2 A17 SATA_RN1/PERN6_L2 J8 SATA_RP1/PERP6_L2 H8 SATA_TP0/PETP6_L3 A15 SATA_TN0/PETN6_L3 B15 SATA_RP0/PERP6_L3 H5 SATA_RN0/PERN6_L3 J5 RTCX1 AW5 RTCRST AU7 SRTCRST AV6 INTVRMEN AV7 INTRUDER AU6 TC34 @1 RC34 1 220K_0402_1% TC23 @1 HSW_ULT_DDR3L LPC SMBUS C-LINK SPI 7 OF 19 UC1G HASWELL-ULT-DDR3L_BGA1168 CL_RST AF4 CL_DATACL_CLK AD2 AF2 SML1CLK/GPIO75 AU3 SML1DATA/GPIO74 AH3 SML1ALERT/PCHHOT/GPIO73SML0DATA AU4 AK1 SML0CLK AN1 SMBDATA AH1 SML0ALERT/GPIO60 AL2 SMBCLK AP2 SMBALERT/GPIO11 AN2 SPI_IO3 AF1Y6 SPI_IO2SPI_MISO AA4 SPI_MOSI AA2 SPI_CS2 AC2Y4 SPI_CS1 SPI_CLK AA3 SPI_CS0 Y7 LFRAME AV12 LAD3 AW11AY12 LAD2LAD1 AW12AU14 LAD0

RC179 1K_0402_5% @ 1 2 YC1 32.768KHZ_12.5PF_200458-PG14 1 2 RC32 2 110M_0402_5% CC8 .1U_0402_10V6-K 1 2 G D S QC2A 2N7002KDW H_SOT363-6 2 6 1 RC531 215_0402_5% RC431 233_0402_5% TC26 @1 RC58 2.2K_0402_5% 1 2 RC41 2 1330K_0402_5% CC97 .1U_0402_10V6-K @ 1 2 CC3 1U_0402_10V6K 1 2 RC441 233_0402_5% TC25 @1 G D S QC2B 2N7002KDW H_SOT363-6 5 3 4 RC60 1K_0402_5% 1 2 RC39 2 11M_0402_5% RC59 2.2K_0402_5% 1 2 RPC22 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 UC3 W 25Q64FVSSIG_SO8 CLK 6 GND 4 DI 5 DO 2 WP# 3 VCC 8 HOLD# 7 CS# 1 CC6 1U_0402_10V6K 1 2 CC5 18P_0402_50V8J 1 2 TC30 @1

Confidential

(8)

5 4 3 2 1 D D C C B B A A

Width: 12-15Mil

Space:12Mil

Length: 500Mil

DIFFCLK_BIASREF

LAN

WLAN

PCIE CLK2

PCIE CLK3

PCIE CLK4

GPU

*

DSWODVREN - On Die DSW VR Enable

H Enable

L Disable

Reserve for DS3 Reserve for DS3 Reserve for DS3 XTAL24_OUT XTAL24_IN XTAL24_IN XTAL24_OUT DIFFCLK_BIASREF MCP_TESTLOW2 MCP_TESTLOW4 MCP_TESTLOW1 MCP_TESTLOW3 SYS_PWROK_R PCH_GPIO72 PM_SLP_SUS#_R SUSCLK APWROK PCIE_CLKREQ0# PCIE_CLKREQ1# SYS_RESET# DSWODVREN PM_CLKRUN# SUS_STAT# PM_SLP_S5# SUSACK#_R SUSWARN#_R SUSWARN#_R PBTN_OUT#_R PM_SLP_S4#_R PM_SLP_S3#_R CLK_PCIE_LAN# CLK_PCIE_LAN LAN_CLKREQ# WLAN_CLKREQ# CLK_PCIE_WLAN CLK_PCIE_WLAN# CLK_PCIE_GPU# CLK_PCIE_GPU GPU_CLKREQ# CLK_PCI_EC_R PCH_RSMRST#_R WAKE# PLT_RST#_R PCIE_CLKREQ5# SYS_RESET# AC_PRESENT_R AC_PRESENT_R PCH_GPIO72 WAKE# DSWODVREN MCP_TESTLOW3 MCP_TESTLOW2 MCP_TESTLOW4 MCP_TESTLOW1 EC_RSMRST# PCH_DPWROK_R PCH_PWROK_R WLAN_CLKREQ# LAN_CLKREQ# PCIE_CLKREQ5# PM_CLKRUN# GPU_CLKREQ# PLT_RST#_R PCH_DPWROK_R SUSCLK PCH_PWROK PCH_RSMRST#_R GPU_CLKREQ# PCH_GPIO72 PCIE_CLKREQ1# PCIE_CLKREQ0# AC_PRESENT_R SYS_PWROK PCH_DPWROK_R PCH_PWROK SUSACK# 44 SYS_PWROK 44 PCH_PWROK 10,44 EC_RSMRST# 44 PLT_RST# 19,37,40,44 PBTN_OUT# 44 PM_SLP_SUS# 44 PM_SLP_S4# 44 PM_SLP_S3# 44 SUSWARN# 44 CLK_PCI_EC 44 DPWROK_EC 44 PCIE_WAKE# 9,37,40,44 CLK_PCIE_LAN# 37 CLK_PCIE_LAN 37 CLK_PCIE_WLAN# 40 CLK_PCIE_WLAN 40 CLK_PCIE_GPU# 19 CLK_PCIE_GPU 19 LAN_CLKREQ# 37 WLAN_CLKREQ# 40 GPU_CLKREQ# 19 SUSCLK 40 PM_SLP_S5# 44 AC_PRESENT 44 ACIN# 44,53 +1.05VS_PLPTCLKPLL +3VALW_PCH +3VS +3VALW VCCRTC

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

MCP (Clock,PM)

Custom 8 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

MCP (Clock,PM)

Custom 8 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

ACLUA

1.0

MCP (Clock,PM)

Custom 8 59 Thursday, December 26, 2013

2013/08/08

2013/08/05

CC11 4.7P_0402_50V8-J 1 2 TC40 PAD @ 1 RC94 100K_0402_1%2 @ 1 RC182 1 2 0_0402_5% CC101 1000P_0402_50V7K @ 1 2 RC77 330K_0402_5% 1 2 TC39 PAD @ 1 RC86 1 2 0_0402_5% RC92 100K_0402_5%2 1 RC82 1 @ 2 0_0402_5% RC73 2 122_0402_5% RC126 1 @ 2 0_0402_5% RC81 1 @ 2 0_0402_5% RC140 1 @ 2 0_0402_5% RC89 1 @ 2 0_0402_5% RC83 1 @ 2 0_0402_5% RC80 330K_0402_5% @ 1 2 RC71 2 11M_0402_5% RPC4 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC141 1 @ 2 0_0402_5% RC84 1 @ 2 0_0402_5% RC139 1 @ 2 0_0402_5% RC85 1 @ 2 0_0402_5% RC79 1 @ 2 0_0402_5% G D S QC8 2N7002KW_SOT323-3 @ 2 1 3 RC87 1 @ 2 0_0402_5% RC72 3.01K_0402_1% 1 2 YC2 24MHZ_6PF_7V24000032 OSC1 1 GND1 2 OSC2 3 GND2 4 RPC5 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 CC103 1000P_0402_50V7K @ 1 2 RC88 1 @ 2 0_0402_5% RPC21 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 HSW_ULT_DDR3L SYSTEM POWER MANAGEMENT

8 OF 19 UC1H HASWELL-ULT-DDR3L_BGA1168 SLP_A AL5 SLP_SUS AP4 SLP_LAN AJ7 SLP_S3 AT4 SLP_S5/GPIO63 AP5 SLP_S4 AJ6 SUSCLK/GPIO62 AE6 CLKRUN/GPIO32 V5 SUS_STAT/GPIO61 AG4 WAKE AJ5 DSWVRMEN AW7 DPWROK AV5 SLP_WLAN/GPIO29 AM5AF3 SLP_S0 SUSWARN/SUSPWRDNACK/GPIO30 AV4 PWRBTN AL7 BATLOW/GPIO72 AN4AJ8 ACPRESENT/GPIO31

RSMRST AW6 PCH_PWROK AY7 SUSACK AK2 PLTRST AG7AB5 APWROK

SYS_PWROK AG2AC3 SYS_RESET

RPC3 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 CC104 1000P_0402_50V7K @ 1 2 TC37 @ 1 RC76 1 2 10K_0402_5% RC74 1 2 10K_0402_5% RC911 2 10K_0402_5% RC75 1 @ 2 10K_0402_5% TC38 PAD @ 1 RC120 1 2 10K_0402_5% RC90 1 2 10K_0402_5% RC105 10K_0402_5% 2 @ 1 CLOCK SIGNALS HSW_ULT_DDR3L 6 OF 19 UC1F HASWELL-ULT-DDR3L_BGA1168 CLKOUT_PCIE_N1 B41 CLKOUT_PCIE_P1 A41 PCIECLKRQ1/GPIO19 Y5 PCIECLKRQ0/GPIO18 U2 CLKOUT_PCIE_P0 C42 CLKOUT_ITPXDP B35 CLKOUT_LPC_0 AN15 CLKOUT_LPC_1 AP15 PCIECLKRQ4/GPIO22 U5 CLKOUT_PCIE_P4 B39 CLKOUT_PCIE_N4 A39 PCIECLKRQ3/GPIO21 N1 CLKOUT_PCIE_N0 C43 XTAL24_OUT B25 XTAL24_IN A25 PCIECLKRQ5/GPIO23 T2 CLKOUT_PCIE_P5 A37 CLKOUT_PCIE_N5 B37 CLKOUT_PCIE_P3 C37 CLKOUT_PCIE_N3 B38 PCIECLKRQ2/GPIO20 AD1 CLKOUT_PCIE_N2 C41 CLKOUT_PCIE_P2 B42 DIFFCLK_BIASREF C26 RSVD5 K21 RSVD6 M21 TESTLOW_C35 C35 TESTLOW_C34 C34 TESTLOW_AK8 AK8 TESTLOW_AL8 AL8 CLKOUT_ITPXDP_P A35 RC78 1 2 10K_0402_5% CC12 4.7P_0402_50V8-J 1 2 RC95 1K_0402_5% 1 @ 2

Confidential

(9)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A BOARD_ID2 BOARD_ID3 Reserve Description BOARD_ID0 BOARD_ID1 0 GPIO66, Internal 20K PD

1: Enable Top Swap Mode *0: Disable Top Swap Mode(default)

GPIO86, Internal PD 1: LPC *0: SPI OPI_RCOMP Width 20Mil Space 15Mil Length 500Mil USBRBIAS Width 20Mil Space 15Mil Length 500Mil PCIE_RCOMP&PCIE_IREF Width 12~15Mil Space >12Mil Length 500Mil WLAN LAN PCIE3 PCIE4 PCIE5

Camera

LEFT USB (3.0)

LEFT USB (2.0)

Card reader

RIGHT USB (2.0)

Touch panel

BT

LEFT USB (3.0)

GPU

1: Enabled No Reboot Mode *0: Disable No Reboot Mode

GPIO81, No Reboot, Internal PD GPIO15, Internal PD

1: INTEL ME TLS W/ Confidentiality *0: INTEL ME TLS W/O Confidentiality

N15S-GT single rank 1 N15S-GT Dual rank 0 14’ panel 1 15’ panel Reserve Reserve Reserve Reserve Reserve Reserve Reserve KBRST# SERIRQ OPI_COMP PCIE_RCOMP PCH_GPIO25 PCH_GPIO46 PCH_GPIO13 PCH_GPIO83 PCH_GPIO76 PCH_GPIO15 VGA_PWRGD PCH_GPIO9 PCH_GPIO10 PCH_GPIO69 PCH_GPIO67 PCH_GPIO66 PCH_GPIO65 PCH_GPIO64 PCH_GPIO0 PCH_GPIO1 PCH_GPIO2 PCH_GPIO3 ODD_EN PCH_WLAN_OFF# PCH_GPIO89 PCH_GPIO44 PCH_GPIO49 PCH_BT_OFF# PCH_GPIO14 PCH_GPIO4 PCH_GPIO5 PCH_GPIO70 PCH_GPIO58 PCH_GPIO6 PCH_GPIO59 PCH_GPIO90 PCH_GPIO38 BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID0 BOARD_ID2 BOARD_ID1 PCH_GPIO86 PCH_GPIO26 PCH_GPIO28 DS3_WAKE# PCH_GPIO56 PCH_GPIO57 PCH_GPIO45 PCH_GPIO47 PCH_GPIO92 ODD_DA# PCH_GPIO50 PCH_GPIO33 PCH_GPIO91 PCH_GPIO85 USB20_P0 USB20_N0 USB20_N3 USB20_P3 USB20_P2 USB20_N2 USB20_N6 USB20_P6 USB20_N4 USB20_P4 USB_OC1# USB_OC2# USB_OC3# USB_OC0# USB20_P1 USB20_N1 USB20_P5 USB20_N5 PCH_GPIO12 PCH_BEEP PCH_WLAN_OFF# PCH_BT_OFF# PCH_GPIO66 PCH_GPIO86 PCH_GPIO7 PCH_GPIO71 PCH_GPIO94 PCH_GPIO93 PCIE_PTX_DRX_P3 PCIE_PTX_DRX_N3 PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 PCIE_PTX_DRX_N4 PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 PCIE_PTX_DRX_P4 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_C_GRX_N0 PCIE_CTX_GRX_P0 PCIE_CTX_C_GRX_P0 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_C_GRX_N1 PCIE_CTX_GRX_P1 PCIE_CTX_C_GRX_P1 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_C_GRX_N2 PCIE_CTX_GRX_P2 PCIE_CTX_C_GRX_P2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_C_GRX_N3 PCIE_CTX_GRX_P3 PCIE_CTX_C_GRX_P3 USB30_RX_N1 USB30_TX_N1 USB30_TX_P1 USB30_RX_P1 CMOS_ON# USBRBIAS USB_OC0# USB_OC1# PCH_GPIO12 DS3_WAKE# PCH_GPIO28 PCH_GPIO26 PCH_GPIO58 PCH_GPIO59 PCH_GPIO13 PCH_GPIO14 PCH_GPIO25 PCH_GPIO45 PCH_GPIO46 PCH_BEEP PCH_GPIO8 EC_SMI# PCH_GPIO8 PCH_GPIO15 PCH_GPIO14 ODD_EN PCH_GPIO49 PCH_GPIO50 PCH_GPIO85 PCH_GPIO89 PCH_GPIO91 PCH_GPIO90 PCH_GPIO92 PCH_GPIO93 PCH_GPIO4 PCH_GPIO5 PCH_GPIO67 PCH_GPIO69 VGA_PWRGD PCH_GPIO71 SERIRQ BOARD_ID3 PCH_GPIO38 PCH_GPIO3 PCH_GPIO2 PCH_GPIO94 PCH_GPIO0 PCH_GPIO1 PCH_GPIO9 PCH_GPIO10 USB_OC2# USB_OC3# PCH_GPIO64 PCH_GPIO7 PCH_GPIO6 PCH_GPIO65 PCH_GPIO70 PCH_GPIO83 CMOS_ON# KBRST# PCH_GPIO56 PCH_GPIO57 PCH_GPIO44 PCH_GPIO47 PCH_GPIO33 PCH_GPIO76 H_THRMTRIP#_R H_THRMTRIP#_R ODD_DA# USB20_N0 45 USB20_P0 45 USB20_P3 45 USB20_N2 41 USB20_P2 41 USB20_N3 45 USB20_N4 33 USB20_P4 33 USB20_N6 40 USB20_P6 40 USB_OC1# 41 USB20_N1 41 USB20_P1 41 USB20_N5 33 USB20_P5 33 PCH_BEEP 43 KBRST# 44 SERIRQ 44 PCH_BT_OFF# 40 PCH_WLAN_OFF# 40 CMOS_ON# 33 USB_OC2# 45 PCIE_PRX_DTX_N3 37 PCIE_PTX_C_DRX_N3 37 PCIE_PRX_DTX_P3 37 PCIE_PTX_C_DRX_P3 37 PCIE_PRX_DTX_N4 40 PCIE_PRX_DTX_P4 40 PCIE_PTX_C_DRX_N4 40 PCIE_PTX_C_DRX_P4 40 PCIE_CRX_GTX_N[0..3] 19 PCIE_CRX_GTX_P[0..3] 19 PCIE_CTX_C_GRX_N[0..3] 19 PCIE_CTX_C_GRX_P[0..3] 19 USB30_TX_N1 41 USB30_RX_P1 41 USB30_RX_N1 41 USB30_TX_P1 41 ODD_DA# 42 PCIE_WAKE# 8,37,40,44 ODD_EN 42 EC_SCI# 44 EC_LID_OUT# 44 H_THRMTRIP# 19 VGA_PWRGD 22,44 EC_SMI# 44 BOARD_ID3 4 +1.05VS_PUSB3PLL +3VS +3VALW_PCH +3VS +3VS +3VS +3VS +3VALW_PCH +3VALW +3VS +3VALW_PCH +3VALW_PCH +1.05V_VCCST

Size Document Number Rev

Date: Sheet of

Security Classification LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (GPIO,USB,PCIE)

Custom 9 59 Monday, December 30, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (GPIO,USB,PCIE)

Custom 9 59 Monday, December 30, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (GPIO,USB,PCIE)

Custom 9 59 Monday, December 30, 2013 2013/08/08 2013/08/05 RPC10 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 CC251 2.1U_0402_10V6-K RC114 1 @ 21K_0402_5% RC124 0_0402_5% @ 1 2 RC104 1K_0402_5% 1 2 RC107 10K_0402_5% @ 1 2 RC97 1 @ 210K_0402_5% RPC16 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC112 0_0402_5% @ 1 2 RPC8 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC121 10K_0402_5% @ 1 2 RC116 2 @ 11K_0402_5% RPC13 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 CC16 .1U_0402_10V6-K OPT@1 2 RPC17 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RPC15 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC96 0_0402_5% 1 2 RC109 10K_0402_5% 1 2 RC123 10K_0402_5% 1 2 RC106 2 149.9_0402_1% CC14 .1U_0402_10V6-K OPT@ 1 2 RC101 10K_0402_5% 15@ 1 2 RC181 1 210K_0402_5% RC99 1 210K_0402_5% CC17 .1U_0402_10V6-K OPT@1 2 RC108 10K_0402_5% 14@ 1 2 DC2 SDM10U45LP-7_DFN1006-2-2 @ 2 1 CC15 .1U_0402_10V6-K OPT@ 1 2 HSW_ULT_DDR3L PCIE USB 11 OF 19 UC1K HASW ELL-ULT-DDR3L_BGA1168 RSVD12AM10 RSVD11AN10 USB2P1 AT7 USB2P0 AM8 PERN3 G11 PETN5_L0 C23 USBRBIASAJ10 USBRBIASAJ11 PETN5_L1 B23 PETP5_L1 A23 USB2N7AR13 USB2P7 AP13 USB2N6AP11 USB2P5 AN13 USB2N5AM13 USB2P6 AN11 USB2P4 AL15 USB2N4AM15 USB2P3 AT10 USB2N3AR10 USB2P2 AP8 USB2N2AR8 USB2N1AR7 USB2N0AN8 PETP4 A29 PERP4 G13 PERN5_L3 E6 PERP5_L3 F6 PETN5_L2 B21 PERP5_L2 G10 PERN5_L2 H10 OC0/GPIO40AL3 OC1/GPIO41AT1 OC2/GPIO42AH2 OC3/GPIO43AV3 PETN3 C29 PERP3 F11 PERN5_L1 F8 PETN5_L3 B22 PETP5_L3 A21 PERP5_L1 E8 PETN4 B29 PETP5_L0 C22 PERP5_L0 E10 PERN5_L0 F10 PERN4 F13 PETP3 B30 PCIE_IREF B27 PCIE_RCOMP A27 RSVD10 E13 PETP5_L2 C21 PERP1/USB3RP3 F17 PERN1/USB3RN3 G17 RSVD9 E15 PETP1/USB3TP3 C31 PETN1/USB3TN3 C30 PERN2/USB3RN4 F15 PETP2/USB3TP4 A31 PETN2/USB3TN4 B31 PERP2/USB3RP4 G15 USB3RN1G20 USB3RP1H20 USB3TN1 C33 USB3TP1 B34 USB3RN2E18 USB3RP2F18 USB3TN2 B33 USB3TP2 A33 CC231 2.1U_0402_10V6-K RPC12 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC103 1 210K_0402_5% CC18 .1U_0402_10V6-K OPT@1 2 RPC14 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 TC41 @ 1 CC102 .0 1 U _ 0 4 0 2 _ 1 6 V 7 -K @ 1 2 RC119 2 13.01K_0402_1% RC122 1 210K_0402_5% CC19 .1U_0402_10V6-K OPT@ 1 2 RPC18 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 CC241 2.1U_0402_10V6-K RC118 22.6_0402_1% 1 2 RC111 0_0402_5% @ 1 2 RC102 10K_0402_5% @ 1 2 RPC9 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC115 2 @ 11K_0402_5% CC20 .1U_0402_10V6-K OPT@ 1 2 RC113 1 @ 21K_0402_5% CC21 .1U_0402_10V6-K OPT@1 2 RPC11 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC110 0_0402_5% @ 1 2 RC100 10K_0402_5% @ 1 2 CC221 2.1U_0402_10V6-K RC125 1 210K_0402_5% RPC6 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 HSW_ULT_DDR3L SERIAL IO GPIO MISC CPU/ 10 OF 19 UC1J HASW ELL-ULT-DDR3L_BGA1168 RSVD8 AB21 RSVD7 AF20 SERIRQ T4 LAN_PHY_PWR_CTRL/GPIO12 AM7 GPIO58 AL4 GPIO44 AK4 BMBUSY/GPIO76 P1 GPIO8 AU2 GPIO15 AD6 GPIO17 T3 GPIO16 Y1 GPIO59 AT5 GPIO48 U4 GPIO47 AB6 GPIO49 Y3 GPIO50 P3 HSIOPC/GPIO71 Y2 GPIO13 AT3 GPIO25 AM4AH4 GPIO14 GPIO46 AG3 GPIO10 AM2 GPIO9 AM3 DEVSLP0/GPIO33 P2 SDIO_POWER_EN/GPIO70 C4 DEVSLP1/GPIO38 L2 SPKR/GPIO81 V2 DEVSLP2/GPIO39 N5 THRMTRIPD60 RCIN/GPIO82 V4 GSPI0_CS/GPIO83 R6 GSPI0_MISO/GPIO85 N6 GSPI0_CLK/GPIO84L6 GSPI0_MOSI/GPIO86 L8 GSPI1_CS/GPIO87 R7 GSPI1_CLK/GPIO88L5 GSPI_MOSI/GPIO90K2 GSPI1_MISO/GPIO89 N7 UART0_RXD/GPIO91J1 UART0_RTS/GPIO93 J2 UART0_TXD/GPIO92 K3 UART0_CTS/GPIO94 G1 UART1_TXD/GPIO1G2 UART1_RXD/GPIO0 K4 I2C0_SCL/GPIO5 F3 I2C1_SDA/GPIO6 G4 I2C1_SCL/GPIO7 F1 SDIO_CMD/GPIO65F4 SDIO_CLK/GPIO64 E3 SDIO_D0/GPIO66 D3 SDIO_D3/GPIO69 E2 SDIO_D2/GPIO68 C3 SDIO_D1/GPIO67 E4 GPIO28 AD7 GPIO57 AP1 GPIO56 AG6 GPIO45 AG5 GPIO24 AD5 GPIO27 AN5 GPIO26 AN3 UART1_RST/GPIO2J3 I2C0_SDA/GPIO4 F2 UART1_CTS/GPIO3J4 PCH_OPI_RCOMPAW15 RC98 1 210K_0402_5% RPC7 10K_0804_8P4R_5% 1 8 2 7 3 6 4 5 RC117 2 @ 11K_0402_5%

Confidential

(10)

5 4 3 2 1 D D C C B B A A VCC_SENSE

Length Match: <25Mil Space: More Than 25Mil GND Reference

SVID

1, Stripline Line, No More Than 6000Mil 2, Alert# Route Between CLK and Data 3, CLK Length<Data Length<CLK Length + 2000Mil 4, Space at least 18Mil

VCCST(0.1A)

1.35V_CPU(1.4A)

HW 4PCS 2.2UF CAP Mounted HW 6PCS 10UF CAP Mounted PWR 2PCS 470U Near VR Output

For cost down, change to X5R.

For RF

For RF

Need short

CPU_SVID_CLK_R CPU_SVID_DAT_R CPU_SVID_CLK_R CPU_SVID_DAT_R CPU_SVID_ALERT#_R VCCST_PW RGD PW R_DEBUG CPU_VR_READY CPU_SVID_ALERT#_R CPU_VR_ON CPU_VR_READY CPU_VR_ON VCCST_PW RGD CPU_SVID_DAT 59 CPU_VR_ON 59 CPU_VCC_SENSE 59 CPU_SVID_CLK 59 CPU_SVID_ALERT# 59 PCH_PW ROK 8,44 VR_CPU_PW ROK 44,59 +1.35V_CPU +1.05V_VCCST +1.05VS CPU_CORE +1.05VS +VCCIO_OUT CPU_CORE +1.05VS CPU_CORE +VCCIOA_OUT CPU_CORE +1.35V_CPU +1.35V_CPU +1.35V +3VALW +1.05V_VCCST +3VALW +1.05V_VCCST

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (Power)

Custom 10 59 Monday, December 30, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (Power)

Custom 10 59 Monday, December 30, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (Power)

Custom 10 59 Monday, December 30, 2013 2013/08/08 2013/08/05 C C 2 8 2 .2 U _ 0 6 0 3 _ 1 0 V 6 -K 1 2 C C 3 4 1 0 U _ 0 6 0 3 _ 6 .3 V 6 M 1 2 TC47 @ 1 RC128 1 @ 20_0402_5% C C 2 7 2 .2 U _ 0 6 0 3 _ 1 0 V 6 -K 1 2 TC45 @ 1 CC39 22U_0805_6.3V6M 1 2 RC146 10K_0402_5% 1 2 RC129 2 @ 1150_0402_1% CC36 4.7U_0603_10V6-K @ 1 2 CC141 100P_0402_50V8J @ 1 2 TC56 @ 1 TC48 @ 1 TC46 @ 1 C C 3 1 1 0 U _ 0 6 0 3 _ 6 .3 V 6 M 1 2 RC134 0_0402_5% @ 1 2 TC57 @ 1 CC49 0.01U_0402_16V7K @ 1 2 CC140 1000P_0402_50V7K @ 1 2 RC132 130_0402_1% 1 2 C C 3 2 1 0 U _ 0 6 0 3 _ 6 .3 V 6 M 1 2 TC54 @ 1 RC135 0_0402_5% @ 1 2 JC1 JUMP_43X79 @ 1 1 2 2 TC58 @ 1 + CC 4 1 3 3 0 U _ 2 .5 V _ M @ 1 2 G D S QC7B 2N7002KDW H_SOT363-6 5 3 4 TC59 @ 1 RC130 10K_0402_5% 1 2 RC136 10K_0402_5% 1 2 TC55 @ 1 TC60 @ 1 HSW_ULT_DDR3L HSW ULT POWER 12 OF 19 UC1L HASWELL-ULT-DDR3L_BGA1168 VCCIO_OUT A59 VCCIOA_OUT E20 RSVD18 AD23 RSVD17 AB23 RSVD16 AC58 VCC1 F59 VDDQ10 AY44 VDDQ9 AY40 VDDQ8 AY35 RSVD24 AA59 RSVD28 U59 RSVD29 V59 RSVD27 AG58 RSVD26 AC59 RSVD25 AE60 RSVD23 AD59 VCCST1 AC22 VDDQ11 AY50 RSVD15 N58 VCC_SENSE E63 RSVD19 AA23 RSVD20 AE59 VCCST_PWRGD B59 VR_READY C59 VR_EN F60 VDDQ7 AR48 VDDQ6 AP43 VDDQ5 AN33AJ37 VDDQ4 VDDQ3 AJ33 VDDQ2 AJ31 VDDQ1 AH26 RSVD14 J58 RSVD13 L59 VCC5 C24 VCC6 C28 VCC7 C32 VCC4 AG57 VCC68 W57 VCC67 U57 VCC64 M23 VCC65 M57 VCC66 P57 VCC63 L22 VCC62 K57 VCC59 H23 VCC60 J23 VCC57 G55 VCC58 G57 VCC54 G49 VCC55 G51 VCC56 G53 VCC52 G45 VCC53 G47 VCC51 G43 VCC49 G39 VCC50 G41 VCC48 G37 VCC47 G35 VCC46 G33 VCC44 G29 VCC45 G31 VCC43 G27 VCC42 G25 VCC41 G23 VCC39 F52 VCC40 F56 VCC38 F48 VCC37 F44 VCC36 F40 VCC33 F28 VCC34 F32 VCC35 F36 VCC32 F24 VCC31 E57 VCC28 E51 VCC29 E53 VCC30 E55 VCC26 E47 VCC27 E49 VCC23 E41 VCC24 E43 VCC25 E45 VCC21 E37 VCC22 E39 VCC18 E31 VCC19 E33 VCC20 E35 VCC16 E27 VCC17 E29 VCC13 C56 VCC14 E23 VCC15 E25 VCC11 C48 VCC12 C52 VCC8 C36 VCC9 C40 VCC10 C44 VCC61 K23 VCC3 AD57 VCC2 AB57 VCCST3 AE23 VCCST2 AE22 VIDSOUT L63 VIDSCLK N63 VIDALERT L62 VSS345 P62 RSVD_TP1 P60 RSVD_TP2 P61 RSVD_TP3 N59 RSVD_TP4 N61 RSVD21 T59 RSVD22 AD60 VSS344 D63 PWR_DEBUG H59 C C 2 6 2 .2 U _ 0 6 0 3 _ 1 0 V 6 -K CD@ 1 2 TC50 @ 1 TC61 @ 1 CC2 33P_0402_50V8J@ 1 2 TC51 @ 1 RC144 10K_0402_5% 1 2 RC137 1K_0402_5% 1 2 RC138 0_0402_5% @ 1 2 CC46 0.01U_0402_16V7K @ 1 2 TC62 @ 1 RC133 2 143_0402_5% RC147 0_0402_5% @ 1 2 TC52 @ 1 G D S QC7A 2N7002KDW H_SOT363-6 2 6 1 C C 3 5 1 0 U _ 0 6 0 3 _ 6 .3 V 6 M 1 2 RC148 0_0402_5% @ 1 2 TC63 @ 1 TC53 @ 1 RC131 75_0402_1% 1 2 RC145 10K_0402_5% @ 1 2 C C 3 7 3 3 P _ 0 4 0 2 _ 5 0 V 8 J @ 1 2 C C 3 3 1 0 U _ 0 6 0 3 _ 6 .3 V 6 M 1 2 LC1 UPB100505T-121Y-N 1 2 G D S QC6A 2N7002KDW H_SOT363-6 2 6 1 C C 3 8 3 3 P _ 0 4 0 2 _ 5 0 V 8 J @ 1 2 TC64 @ 1 CC40 1U_0402_10V6K 1 2 C C 3 0 1 0 U _ 0 6 0 3 _ 6 .3 V 6 M CD@ 1 2 C C 2 9 2 .2 U _ 0 6 0 3 _ 1 0 V 6 -K 1 2 CC42 .1U_0402_10V6-K @ 1 2 G D S QC6B 2N7002KDW H_SOT363-6 5 3 4 RC127 100_0402_1% 1 2

Confidential

(11)

5 5 4 4 3 3 2 2 1 1 D D C C B B A A VCCHSIO 1.838A VCCDSW 114mA VCCSUS3_3[1:5] 65mA VCCHDA 11mA VCCSPI 18mA VCCRTC 1mA VCC3_3[1:4] 41mA VCCSDIO 17mA VCCASW[1:5] 658mA VCCTS1_5 3mA VCC1_05[1:9] 1.741A +1.05VS_PLPTVCC1P05 185mA +1.05VS_POPIPLL 57mA +1.05VS_PLPTCLKPLL 31mA +1.05VS_PUSB3PLL 41mA +1.05VS_PSATA3PLL 42mA

For RF

For Intel recommend, place one 0.47uF

capacitor to address temporary inrush

current.(DOC.489999)

Need short

+DCPRTC +PCH_DCPSUSBYP +1.05VS_DCPSUS2 +1.05VS_DCPSUS3 +1.05VS_DCPSUS1 VCCHDA VCCDSW 3_3 VCCSPI VCCDSW 3_3 +PCH_DCPSUSBYP +1.05VS_DCPSUS4 +1.5VS +3VS +1.05VS +3VALW _PCH +1.05VS_VCCHSIO +1.05VS_POPIPLL VCCSPI +1.05VS_PLPTCLKPLL +1.05VS +1.05VS_PLPTVCC1P05 +1.05VS +1.05VS +3VS +3VALW _PCH +3VALW _PCH +3VALW +3VS +3VL +3VALW _PCH +1.05VS_PLPTVCC1P05 +1.05VS_POPIPLL +1.05VS_PLPTCLKPLL +1.05VS +1.05VS_VCCHSIO +1.05VS_PSATA3PLL +1.05VS_PUSB3PLL +3VS VCCDSW 3_3 VCCHDA +1.05VS +3V_SPI +3VS +1.05VS_PSATA3PLL +1.05VS_PUSB3PLL +1.05VS VCCRTC +1.05VS

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (Power2)

Custom 11 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (Power2)

Custom 11 59 Thursday, December 26, 2013 2013/08/08 2013/08/05

Size Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date Deciphered Date

Title

ACLUA

1.0

MCP (Power2)

Custom 11 59 Thursday, December 26, 2013 2013/08/08 2013/08/05 RC150 0_0402_5% 1 2 CC88 22U_0805_6.3V6M 1 2 CC73 1U_0402_10V6K @ 1 2 CC901 20.47U_0402_25V6K CC93 47U_0805_4V6-M @ 1 2 CC86 22U_0805_6.3V6M 1 2 RC151 0_0402_5% @ 1 2 CC95 22U_0805_6.3V6M 1 2 CC91 33P_0402_50V8J @ 1 2 CC92 47U_0805_4V6-M @ 1 2 C C 6 92 2 U _ 0 8 0 5 _ 6 .3 V 6 M @ 1 2 CC81 22U_0805_6.3V6M 1 2 CC87 1U_0402_10V6K 1 2 C C 6 7 2 2 U _ 0 8 0 5 _ 6 .3 V 6 M 1 2 CC98 22U_0805_6.3V6M 1 2 RC154 0_0402_5%2 @ 1 LC4 2.2UH_CIG10W 2R2MNC_20% 1 2 CC99 22U_0805_6.3V6M 1 2 C C 5 1 1 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 RC149 0_0402_5% @ 1 2 CC61 1U_0402_10V6K 1 2 C C 7 7 1 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 CC100 22U_0805_6.3V6M 1 2 C C 5 3 1 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 CC59 1U_0402_10V6K @ 1 2 TC67 @1 CC85 22U_0805_6.3V6M 1 2 C C 5 4 1 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 CC94 1U_0402_10V6K 1 2 CC83 22U_0805_6.3V6M 1 2 RC153 0_0402_5% @ 1 2 TC66 @1 C C 7 4 1 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 LC2 2.2UH_CIG10W 2R2MNC_20% 1 2 LC5 2.2UH_CIG10W 2R2MNC_20% 1 2 CC66 1U_0402_10V6K @ 1 2 CC50 1U_0402_10V6K 1 2 LC6 0_0603_5% @ 1 2 CC80 1U_0402_10V6K 1 2 JC2 JUMP_43X79 @ 1 1 2 2 RC152 0_0402_5%2 @ 1 C C 7 0 1 U _ 0 4 0 2 _ 1 0 V 6 K @ 1 2 CC79 22U_0805_6.3V6M 1 2 CC84 1U_0402_10V6K 1 2 CC60 1U_0402_10V6K @ 1 2 CC89 1U_0402_10V6K 1 2 C C 6 4 1 U _ 0 4 0 2 _ 1 0 V 6 K CD@ 1 2 CC52 0.1U_0402_10V7K 1 2 CC 5 71 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 C C 6 8 1 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 USB2 THERMAL SENSOR HSIO HSW_ULT_DDR3L USB3 OPI RTC GPIO/LPC VRM HDA SERIAL IO SUS OSCILLATOR SPI LPT LP POWER CORE 13 OF 19 UC1M HASWELL-ULT-DDR3L_BGA1168 VCCHDA AH14 VCCTS1_5 J15 DCPSUS1[2] AD8 DCPSUS1[1] AD10 DCPSUSBYP[2] AG20 DCPSUSBYP[1] AG19 DCPSUS4 AB8 VCCASW[3] AE9 VCCASW[4] AF9 VCCASW[5] AG8 VCCSUS3_3[5] AH11 VCCRTC AG10 DCPRTC AE7 VCCSPI Y8 VCCASW[1] AG14 VCCASW[2] AG13 VCC3_3[4] K16 VCC3_3[3] K14 VCCSDIO[2] T9 VCCSDIO[1] U8 DCPSUS3 J13 VCCAPLL[2] W21 VCCHSIO[1] K9 VCCHSIO[2] L10 VCCHSIO[3] M9 VCCAPLL[1] AA21Y20 RSVD30 VCCSATA3PLL B11 VCCUSB3PLL B18 VCC1_05[1] N8 VCC1_05[2] P9 VCC1_05[3] J11 VCC1_05[4] H11 VCC1_05[5] H15 VCC1_05[6] AE8 VCC1_05[7] AF22 VCCSUS3_3[4] AE21 VCCSUS3_3[3] AE20V21 RSVD33RSVD32 M20K18 RSVD31VCCCLK[5] T21 VCCCLK[4] R21J17 VCCCLK[3] VCCACLKPLL A20 VCC3_3[2] W9V8 VCC3_3[1] VCCDSW3_3 AH10 VCCSUS3_3[1] AC9 RSVD34 AC20 VCCSUS3_3[2] AA9 DCPSUS2 AH13 VCC1_05[8] AG16 VCC1_05[9] AG17 VCCCLK[1] J18 VCCCLK[2] K19 C C 5 8 0 .1 U _ 0 4 0 2 _ 1 0 V 7 K @ 1 2 CC82 22U_0805_6.3V6M 1 2 C C 7 6 1 U _ 0 4 0 2 _ 1 0 V 6 K CD@ 1 2 C C 6 51 0 U _ 0 6 0 3 _ 6 .3 V 6 M 1 2 C C 5 6 0.1 U _ 0 4 0 2 _ 1 0 V 7 K 1 2 C C 7 1 2 2 U _ 0 8 0 5 _ 6 .3 V 6 M 1 2 CC 7 2 0 .1 U _ 0 4 0 2 _ 1 0 V 7 K 1 2 C C 7 5 1 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 C C 6 31 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 CC78 22U_0805_6.3V6M 1 2 C C 6 2 1 U _ 0 4 0 2 _ 1 0 V 6 K 1 2 C C 5 50.1 U _ 0 4 0 2 _ 1 0 V 7 K 1 2 LC3 2.2UH_CIG10W 2R2MNC_20% 1 2

Confidential

Figure

Updating...

References

  1. www.pdffactory.com
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