Advanced 8086 Microprocessor Trainer
Nvis 5586A
Learning Material Ver 1.0
Designed & Manufactured by:
Advanced 8086 Microprocessor Trainer Nvis 5586A Table of Contents 1. Introduction 4 2. Technical Specifications 5 3. Safety Instructions 6 4. Theory 7 5. Capabilities 34 6. Hardware Description 35 7. Command Description 36
8. Memory Address & Port Address 65
9. Subroutines 68
10. Serial Communication 95
11. MASM Macro Assembler 100
12. Sample Programs 104
13. On-Board Interface 163
14. Parallel Communication between two Nvis 5586A 168 Trainers using 8255 in I/O mode
15. Serial Communication between two Nvis 5586A 169 Trainers
16. Connector Details 170
17. Jumper/DIP switch Details 178
18. Frequently Asked Questions 180
19. Warranty 188
20. List of Service Centers 189
Introduction
General Description:
Nvis 5586A is a single board microprocessor training/development kit configured around the Intel‘s 16 bit Microprocessor 8086. This kit can be used to train engineers, to control any industrial process and to develop software for 8086 systems.
The kit has been designed to operate in the maximum mode. Co-processor 8087 and I/O Processor 8089 can be added on board.
The kit communicates with the outside world through an IBM PC compatible Keyboard with 20x2 LCD Display. The kit also has the capacity of interacting with PC.
Nvis 5586A is packed up with powerful monitor in 128K Bytes of factory programmed EPROMS and 32K Bytes of Read/Write Memory. The total memory on the board is 144K Bytes. The system has 72 programmable I/O lines. The serial I/O Communication is made possible through 8251.
For control applications, three 16 bit Timer/Counters are available through 8253. For real time applications, the 8 level of interrupt are provided through 8259. Nvis 5586A provides onboard battery backup for onboard RAM. This saves the user‘s program in case of power failure.
The onboard resident system monitor software is very powerful. It provides various software commands like BLOCK MOVE, SINGLE STEP, EXECUTE, FILL etc which are helpful in debugging/developing software. An onboard line assembler provides user to write program in assembling language.
Technical Specifications
Central Processor : 8086, 16 bit Microprocessor operating in max. mode. Co-Processor Support: Support 8087 Numeric Data Processor.
I/O Processor Support: Support 8089 I/O Processor.
EPROM : 128K Bytes of EPROM Loaded with monitor program.
RAM : 32K bytes of CMOS RAM with Battery Backup using 3.6V Ni-Cd Battery.
Parallel : 72 I/O lines using three nos. of 8255. Serial : RS-232-C Interface using 8251. Interrupt : 8 different level interrupt using 8259. Timer/Counter : Three 16 bit Timer/Counter using 8253. Keyboard & Display : 105 IBM PC Keyboard & 20x2 LCD Display.
BUS : All address, data and control signals (TTL Compatible) available at 50 Pin & 20 Pin FRC Connector.
Power Supply : 5V/ 2 Amps, ±12V/250mA Physical Size : 32.6cm x 25.2cm Operating Temp. : 0 to 50°C. Included Accessories 26 Pin FRC Cable 3 No 50 Pin FRC Cable 1 No RS232 Cable 1 No SMPS Supply 1 No Jumpers 4 No
Phoenix Connector 1No
Keyboard 1No
Keyboard Adaptor 1No
Safety Instructions
Read the following safety instructions carefully before operating the instrument. To avoid any personal injury or damage to the instrument or any product connected to the instrument.
Do not operate the instrument if suspect any damage to it. The instrument should be serviced by qualified personnel only.
For your safety:
Use proper Mains cord : Use only the mains cord designed for this instrument. Ensure that the mains cord is suitable for your country.
Ground the Instrument : This instrument is grounded through the protective earth conductor of the mains cord. To avoid electric shock, the grounding conductor must be connected to the earth ground. Before making connections to the input terminals, ensure that the instrument is properly grounded..
Use in proper Atmosphere : Please refer to operating conditions given in the manual.
1. Do not operate in wet / damp conditions. 2. Do not operate in an explosive atmosphere. 3. Keep the product dust free, clean and dry.
Theory
It is a 16 bit microprocessor. 8086 has a 20 bit address bus can access upto 220 memory locations (1 MB). It can support upto 64K I/O ports. It provides 14, 16-bit registers. It has multiplexed address and data bus AD0- AD15 and A16 – A19. It requires single phase clock with 33% duty cycle to provide internal timing. 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. It is a 40 pin dual in line package.
Minimum and Maximum Modes:
The minimum mode is selected by applying logic 1 to the MN / MX* input pin. This is a single microprocessor configuration.
The maximum mode is selected by applying logic 0 to the MN / MX* input pin. This is a multi microprocessor configuration.
Pin diagram of 8086
Internal Architecture of 8086
8086 has two blocks BIU and EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes
instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, and Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.
Bus Interface Unit:
It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions: Instruction fetching,
Instruction queuing, Operand fetch and storage,
Address relocation and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement pipeline architecture. This queue permits prefetch of up to six bytes of instruction code. Whenever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction. These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.
The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory, these intervals of no bus activity, which may occur between bus cycles, are known as idle state.
If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.
For example, the physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.
The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.
Execution Unit:
The Execution unit is responsible for decoding and executing all instructions. The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue.
When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.
Minimum Mode Interface
When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interface. The minimum mode signal can be divided into the following basic groups: address/data bus, status, control, interrupt and DMA.
Address/Data Bus: These lines serve two functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 represents the LSB. A 20-bit address gives the 8086 a 1Mbyte memory address space.
More over it has an independent I/O address space which is 64K bytes in length. The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and D0 is the LSB.
When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller.
Status signal:
The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3. These status bits are output on the bus at the same time that data are transferred over the other bus lines.
Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers is used to generate the physical address that was output on the address bus during the current bus cycle.
Code S4S3 = 00 identifies a register known as extra segment register as the source of the segment address.
Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level.
Control Signals: The control signals are provided to support the 8086 memory I/O interfaces. They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system bus.
ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE. Another control signal that is produced during the bus cycle is BHE i.e. bank high enable. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These lines also serve a second function, which is as the S7 status line. Using the M/IO* and DT/R* lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. The logic level of M/IO* tells external circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation. The direction of data transfer over the bus is signaled by the logic level output at DT/R*. When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are either written into memory or output to an I/O device. On the other hand, logic 0 at DT/R* signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input port. The signals read RD and write WR indicate that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to intimate external device about valid write or output data are on the bus. On the other hand, RD indicates that the 8086 is performing a read of data of the bus. During read operations, one other control signal is also supplied. This is DEN (data enable) and it signals external devices when they should put data on the bus. There is one other control signal that is involved with the memory and I/O interface. This is the READY signal. READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods. This signal is provided by an external clock generator device and can be supplied by
the memory or I/O subsystem to signal the 8086 when they are ready to permit the data transfer to be completed.
Interrupt signals: The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge (INTA). INTR is an input to the 8086 that can be used by an external device to signal that it needs to be serviced. Logic 1 at INTR represents an active interrupt request. When an interrupt request has been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0 at the INTA output. The TEST input is also related to the external interrupt interface. Execution of a WAIT instruction causes the 8086 to check the logic level at the TEST input. If the logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086 no longer executes instructions; instead it repeatedly checks the logic level of the TEST input waiting for its transition back to logic 0. As TEST switches to 0, execution resume with the next instruction in the program. This feature can be used to synchronize the operation of the 8086 to an event in external hardware. There are two more inputs in the interrupt interface: the non-maskable interrupt NMI and the reset interrupt RESET. On the 0-to-1 transition of NMI control is passed to a non-maskable interrupt service routine. The RESET input is used to provide a hardware reset for the 8086. Switching RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service routine.
DMA Interface signals: The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA signals. When an external device wants to take control of the system bus, it signals to the 8086 by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE, M/IO*, DT/R*, RD, WR, DEN and INTR are all in the high Z state. The 8086 signals external device that it is in this state by switching its HLDA output to logic 1 level.
Maximum Mode Interface: When the 8086 is set for the maximum-mode configuration; it provides signals for implementing a multiprocessor / coprocessor system environment. By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program. Usually in this type of system environment, there are some system resources that are common to all processors. They are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resources.
Coprocessor also means that there is a second processor in the system. In this, both processors does not access the bus at the same time. One passes the control of the system bus to the other and then may suspend its operation. In the maximum-mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor.
8086 Maximum Mode Block Diagram
8288 Bus Controller – Bus Command and Control Signals: 8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt interfaces. Specially the WR*, M/IO*, DT/R*, DEN, ALE and INTA, signals are no longer produced by the 8086. Instead it outputs three status signals S0*, S1*, S2* prior to the initiation of each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow. S2*S1*S0* are input to the external bus controller device, the bus controller generates the appropriately timed command and control signals.
The 8288 chip receive the status signal S2*, S1* and S0* and the clock from 8086. Theses status signals are decoded to generate MRDC* (Memory read command), MWTC* (memory write command), IORC* (I/O read command), IOWC* (I/O write command), INTA* (Interrupt acknowledgement) signal. In addition, it can generate advanced memory and I/O write signals AMWC* (Advanced memory write command), AIOWC* (Advanced I/O write command) that are enabled one clock cycle earlier than the normal write control signals because some device require wider cycle.
MRDC* Memory ReaD Command MWTC* Memory WriTe Command IORC* Input/Output Read Command IOWC* Input/Output Write Command INTA* INTerrupt Acknowledge
AMWC* Advanced Memory Write Command AIOWC* Advanced Input/Output Write Command
CEN Command Enable
IOB Input/output Bus only
MCE/PDEN* Master Cascade/Peripheral Data Enable
The 8288 also can generate bus control signals DEN, DT/R*, ALE, MCE/ (PDEN)* i.e. Master Cascade/Peripheral Data Enable. The function of the 1 st three signals are the same as those in the minimum mode. The signal MCE/ (PDEN)* has 2-functions depending on the mode in which 8288 is operating. The 8288 can either operate in I/O bus mode or system bus mode. When CEN (command enable) and IOB (I/O bus) input pin are wired high, the 8288 operate in I/O bus mode. In this mode, the signal PDNE* functions in the same way as DEN but it is active only during I/O instruction. This facility enables 8288 to control 2 set of buses: System bus and I/O bus separately
With AEN* (Address enable) and CEN inputs low, the 8288 functions in system bus mode. When multiple processors are sharing the same bus, active processors can be selected by
enabling the corresponding 8288 via AEN* input. In this mode, the signal MCE (Master cascade enable) is used for selecting the appropriate interrupt controller.
Bus Status Codes:
The 8288 produces one or two of these eight command signals for each bus cycles. For instance, when the 8086 outputs the code S2*S1*S0* equals 001; it indicates that an I/O read cycle is to be performed. In the code 111 is output by the 8086, it is signaling that no bus activity is to take place. The control outputs produced by the 8288 are DEN, DT/R* and ALE. These 3 signals provide the same functions as those described for the minimum system mode. This set of bus commands and control signals is compatible with the Multibus and industry standard for interfacing microprocessor systems.
Queue Status Signals: Two new signals that are produced by the 8086 in the maximum-mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0.
Local Bus Control Signal: Request / Grant Signals:
In a maximum mode configuration, the minimum mode HOLD, HLDA interface is also changed. These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a prioritized bus access mechanism for accessing the local bus.
Minimum Mode 8086 System
In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX* pin to logic 1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transreceiver, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system. Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. Transreceiver are the bidirectional buffers and sometimes they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals. They are controlled by two signals namely, DEN and DT/R*. The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. Usually, EPROM is used for monitor storage, while RAM for user‘s program storage. A system may contain I/O devices. The clock generator generates the clock from the crystal oscillator and then shapes it and divides to make it more precise so that it can be used as an accurate timing reference for the system. The clock generator also synchronizes some external signal with the system clock.
It has 20 address lines and 16 data lines; the 8086 CPU requires three octal address latches and two octal data buffers for the complete address and data separation. The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations. The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M/IO* signal. During the negative going edge of this signal, the valid address is latched on the local bus. The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/IO* signal indicates a memory or I/O operation. At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD)* control signal is also activated in T2. The read (RD)* signal causes the address device to enable its data bus drivers. After RD* goes low, the valid data is available on the data bus. The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers.
Read Cycle Timing Diagram for Minimum Mode
A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO* signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location. The data remains on the bus until middle of T4 state. The WR* becomes active at the beginning of T2 (unlike RD* is somewhat delayed in T2 to provide time for floating). The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. The M/IO*, RD* and WR* signals indicate the type of data transfer as specified in table below.
Write Cycle Timing Diagram for Minimum Mode Hold Response sequence:
The HOLD pin is checked at leading edge of each clock pulse. If it is received active by the processor before T4 of the previous cycle or during T1 state of the current cycle, the CPU activates HLDA in the next clock cycle and for succeeding bus cycles, the bus will be given to another requesting master. The control of the bus is not regained by the processor until the requesting master does not drop the HOLD pin low. When the request is dropped by the requesting master, the HLDA is dropped by the processor at the trailing edge of the next clock.
Bus Request and Bus Grant Timings in Minimum Mode System Maximum Mode 8086 System
In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In this mode, the processor derives the status signal S2*, S1*, S0*. Another chip called bus controller derives the control signal using this status information. In the maximum mode, there may be more than one microprocessor in the system configuration. The components in the system are same as in the minimum mode system. The basic function of the bus controller chip IC8288, is to derive control signals like RD* and WR* (for memory and I/O devices), DEN, DT/R*, ALE etc. using the information by the processor on the status lines. The bus controller chip has input lines S2*, S1*, S0* and CLK. These inputs to 8288 are driven by CPU. It derives the outputs ALE, DEN, DT/R*, MRDC*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*. The AEN, IOB and CEN pins are specially useful for multiprocessor systems. AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN* output depends upon the status of the IOB pin. If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral data enable used in the multiple bus configurations. INTA* pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device. IORC*, IOWC* are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the address port. The MRDC*, MWTC* are memory read command and memory write command signals respectively and may be used as memory read or write signals. All these command signals instructs the memory to accept or send data from or to the bus. For both of these write command signals, the advanced signals namely AIOWC* and AMWC* are available. They also serve the same purpose, but are activated one clock cycle earlier than the IOWC* and MWTC* signals respectively.
The maximum mode system timing diagrams are divided in two portions as read (input) and write (output) timing diagrams. The address/data and address/status timings are similar to the minimum mode. ALE is asserted in T1, just like minimum mode. The only difference lies in the status signal used and the available control and advanced command signals.
Maximum Mode 8086 System
Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals. R0, S1*, S2* are set at the beginning of bus cycle. 8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R* pin during T1. In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC* or IORC*. These signals are activated until T4. For an output, the AMWC* or AIOWC* is activated from T2 to T4 and MWTC* or IOWC* is activated from T3 to T4. The status bit S0* to S2* remains active until T3 and become passive during T3 and T4. If reader input is not activated before T3, wait state will be inserted between T3 and T4.
Timings for RQ/ GT* Signals: The request/grant response sequence contains a series of three pulses. The request/grant pins are checked at each rising pulse of clock input. When a request is detected and if the conditions for HOLD request are satisfied, the processor issues a grant pulse over the RQ/GT* pin immediately during T4 (current) or T1 (next) state. When the requesting master receives this pulse, it accepts the control of the bus; it sends a release pulse to the processor using RQ/GT* pin.
Memory Write Timing in Maximum Mode
8086 CPU Registers
The 8086 has four groups of the user accessible internal registers. They are the instruction pointer, four data registers, four pointer and index register, four segment registers. The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register, with 9 of bits implemented for status and control flags. Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX and DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS(Load pointer using data segment) instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES (Load pointer using extra segment) instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix.
All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are:
Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.
Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing.
Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used in Loop, shift/rotate instructions and as a counter in string manipulation.
Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bitregister DX. When combined, DL register contains the low-order byte of the word, and DH contains the high order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.
The following registers are both general and index registers: Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.
Other registers:
• Instruction Pointer (IP) is a 16-bit register.
• Overflow Flag (OF): set if the result is too large positive number, or is too small negative number to fit into destination operand.
• Direction Flag (DF): If set then string manipulation instructions will auto-decrement index register. If cleared then the index registers will be auto-incremented.
• Interrupt-enable Flag (IF): Setting this bit enables maskable interrupts.
• Single-step Trap Flag (TF): If set then single-step interrupt will occur after the next instruction.
• Sign Flag (SF): Set if the most significant bit of the result is set. • Zero Flag (ZF): Set if the result is zero.
•Auxiliary carry Flag (AF): Set if there was a carry from or borrow to bits 0-3 in the AL register.
• Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.
• Carry Flag (CF) - set if there was a carry from or borrows to the most significant bit during last result calculation.
• Auxiliary carry Flag (AF) - set if there was a carry from or borrows to bits 0-3 in the AL register.
• Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.
• Carry Flag (CF) - set if there was a carry from or borrows to the most significant bit during last result calculation.
The 8086 Addressing Modes
Addressing mode indicates a way of locating data or operands. The addressing modes describe the types of operands and the way they are accessed for executing an instruction. 1. Immediate Addressing Mode: In this addressing mode, the data is provided in the
instruction.
Example: MOV AX, 0006H
2. Direct Addressing Mode: In this addressing mode, the instruction operand specifies the memory address where data is located.
Example: MOV AX, [7000H]
3. Register Addressing Mode: In this addressing mode, the data is stored in a register and it is referred using the particular register. All the registers, except IP, may be used in this mode.
Example: MOV BX, AX
4. Register indirect Addressing Mode: In this addressing mode, the offset address of data is in either BX or SI or DI registers. The default segment is either DS or ES.
Example: MOV AX, [BX]
Here data is present in a memory location in DS whose offset address is in BX.
5. Register Relative Addressing Mode: In this addressing mode, the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the default (either DS or ES) segment. Example: MOV AX, 50H [BX]
6. Indexed Addressing Mode: In this addressing mode, the offset of the operand is stored in one of the index registers. DS and ES are the default segments for index registers SI and DI respectively. 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Example: MOV AX, [SI]
7. Based Indexed Addressing Mode: In this addressing mode, the effective address of data is formed by adding content of a base register (any one of BX or BP) to the content of an index register (any one of SI or DI), the resulting value is a pointer to location where data resides. The default segment register may be ES or DS.
Example: MOV AX, [BX] [SI]
8. Relative Based Indexed Addressing Mode: The effective address is formed by adding an 8-bit or 16-bit displacement with the sum of to the contents of a base register (BX or BP) and index register (SI or DI), in a default segment.
Example: MOV AX, 50 [BX] [SI]
In Nvis 5586A Register relative, Based indexed and Relative based indexed addressing modes are only supported by entering opcode.
Instruction Set of 8086:
1. Data Copy/ Transfer Instructions: This type of instructions is used to transfer data from source operand to destination operand. All the store, move, load, exchange, input and output instructions belong to this category.
2. Arithmetic and Logical Instructions: All the instructions performing arithmetic, logical, increment, decrement, compare and scan instructions belong to this category.
3. Branch Instructions: These instructions transfer control of execution to the specified address. All the call, jump, interrupt and return instructions belong to this class.
4. Loop Instructions: If these instructions have REP prefix with CX used as count register, they can be used to implement unconditional and conditional loops. The LOOP, LOOPNZ and LOOPZ instructions belong to this category. These are useful to implement different loop structures.
5. Machine Control Instructions: These instructions control the machine status. NOP, HLT, WAIT and LOCK instructions belong to this class.
6. Flag Manipulation Instructions: All the instructions which directly affect the flag register, come under this group of instructions. Instructions like CLD, SYD, CLI, STI etc. belong to this category of instructions.
7. Shift and Rotate Instructions: These instructions involve the bitwise shifting or rotation in either direction with or without a count in CX.
8. String Instructions: These instructions involve various string manipulation operations like load, move, scan, compare, store etc. These instructions are only to be operated upon the strings.
Memory
Program, data and stack memories occupy the same memory space. As the most of the processor instructions use 16-bit pointers, the processor can effectively address only 64 KB of memory.
• To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory. • 16-bit pointers and data are stored as:
Address+1: high-order byte
• 32-bit addresses are stored in "segment: offset" format as: Address: low-order byte of segment
Address+1: high-order byte of segment Address+2: low-order byte of offset Address+3: high-order byte of offset
• Physical memory address pointed by segment: offset pair is calculated as: Address = (<segment> * 16) + <offset>
Program memory: Program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 to -127 bytes from current instruction.
Data memory: The processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks).
Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment).Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommended for performance reasons.
Reserved locations:
• 0000H - 03FFH are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment: offset.
• FFFF0H - FFFFFH - after RESET the processor always starts program execution at the FFFF0H address.
Interrupts
The dictionary meaning of the word ‗interrupt‘ is to break the sequence of operation. While the CPU is executing a program, an ‗interrupt‘ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR). After executing ISR, the control is transferred back again to the main program which was being executed at the time of interruption.
Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them properly, it is said to have multiple interrupt processing capability. In 8086s, there are two interrupt pins, NMI and INTR.
The NMI is a non maskable interrupt input pin which means that any interrupt request at NMI input cannot be masked or disabled by any means. The INTR is of 256 types. The INTR types may be from 00 to FFH. If more than one type of INTR interrupt occurs at a time, then an external chip called Programmable interrupt controller is required to handle them. Interrupt Service Routines (ISRs) are the programs to be executed by interrupting the main program execution of the CPU, after an interrupt request appears. After the execution of ISR, the main program continues its execution further from the point at which it was interrupted. Broadly there are two types of interrupt in the 8086 microprocessor. The first out of them is external interrupt and second is internal interrupt. In external interrupt, an external device or a signal interrupts the processor from outside or, in other words, the interrupt is generated outside the processor, for example, a keyboard interrupt. The internal interrupt, on the other hand, is generated internally by the processor circuit, or by the execution of an interrupt instruction. The examples of this type are divide by zero interrupt, overflow interrupt, interrupts due to INT instructions, etc.
Non-Maskable Interrupt
The processor 8086 has a non maskable interrupt input pin (NMI) that has the highest priority among the external interrupts. TRAP is an internal interrupt having the highest priority amongst all the interrupts except the Divide by Zero (Type0) exception.
The NMI pin should remain high for at least two clock cycles and is not needed to be synchronized with the clock for being sensed. When NMI is activated, the current instruction being executed is completed, and then the NMI is served.
Maskable Interrupts
The processor can inhibit certain types of interrupts by use of a special interrupt mask bit. This mask bit is part of the flags/condition code register, or a special interrupt register. In the 8086 microprocessor if this bit is clear, and an interrupt request occurs on the Interrupt Request input, it is ignored.
The processor 8086 also provides a pin INTR, which has lower priority as compared to NMI. Further the priorities, within the INTR types are decided by the type of the INTR signal, which is to be passed to the processor through data bus by some external device like the Programmable Interrupt Controller (8255). The INTR signal is level triggered and can be masked by resetting the interrupt flag. It is internally synchronized with the high transition of CLK. For the INTR signal, to be responded to in the next instruction cycle, it must go high in the last clock cycle of the current instruction or before that. The INTR requests appearing
the next instruction. The status of the pending interrupts is checked at the end of each instruction cycle
Capabilities
Keyboard Mode:
1. Examine/Modify the memory byte locations.
2. Examine/Modify the contents of any of internal register of 8086. 3. Move a block of Data/Program from one location to another location. 4. Fill a particular memory area with a constant.
5. To execute the program in full clock speed.
Installation
To install Nvis 5586A the following additional things are required.
1. Connect the External SMPS Power Supply to AC Power and 5 pin connector to the left side on Nvis 5586A Kit.
2. Switch on the Power Supply at the rear end of SMPS supply.
3. A message – NV5586A 8086 Mic.Tr. will come on display (Press RESET if you do not get - NV5586A 8086 Mic.Tr.
4. Now Nvis 5586A Kit is ready for the user's experiments for Keyboard Mode commands.
Hardware Description
CPU:
8086 is a 16 bit, third generation microprocessor and is suitable for an exceptionally wide spectrum of microcomputer applications. This flexibility is one of most outstanding characteristics.
8086 has got 16 data lines and 20 address lines. The lower 16 address lines are multiplexed with 16 data lines. Hence it becomes necessary to latch the address lines. This is done by using 74 LS 373. In fact several of the 40 CPU pins have dual functions that are selected by a strapping pin. In this kit 8086 is used in the max. mode (MN/MX input held logically low). The 8088 is designed with an 8-bit external path to memory and I/O. Except that the 8086 can transfer 16 bits at a time, the two processors & software are identical in almost every respect. Software identical in almost every respect. Software written for one CPU will execute on the other without alteration. The two processors are designed to operate with the 8089 I/O processors and other processors in multiprocessing and distributed processing systems.
The INTR, TEST & Hold Inputs to 8086 are pulled down and are brought out at PCB FRC connector.
The mask able interrupt INTR is available to the peripheral circuits through the expansion Bus. To use the mask able interrupt an interrupt vector pointer must be provided on the data bus when INTA is active. An interrupt Controller Circuit is provided to take care of more than one source of interrupt.
Co-Processor 8087:
The 8087 Co-processor ―hooks‖ have been designed into the 8086 and 8088 so that these types of processor can be accommodated in the future. A co-processor differs from an independent processor in that it obtains its instructions from another processor, called a host. The co-processor monitors instructions fetched by the host and recognizes certain of these as its own and executes them. A co-processor, in effect, extends the instruction set of its host computer.
I/O Processor 8089:
The 8086 and 8088 are designed to be used with the 8089 in high performance I/O applications. The 8089 in conceptually resembles a microprocessor with two DMA channels and an instruction set specifically tailored for I/O operations. Unlike simple DMA controllers, the 8089 can service I/O devices directly, removing this task from the CPU. In addition, it can transfer data on its own bus or on the system bus, can match 8-bit or 16-bit peripherals to 8-bit or 16-bit buses, and can transfer data from memory to memory and from I/O devices to I/O device. 8089 has been used here in local mode. The system bus, can match 8-bit or 16-bit peripherals to 8-bit or 16-bit buses, and can transfer data from memory to memory and from I/O devices to I/O device. 8089 has been used here in local mode. Clock Generation:
The clock generator circuit is an Intel‘s 8284 clock generator/driver. The circuit accepts a crystal input which operates at a fundamental frequency of 6.144 MHz. (6.14 MHz was selected since this frequency is a multiple of the baud rate clock and also provides a suitable frequency for the CPU). The clock generator/driver divides the crystal frequency by three to produce the 2MHz CLK signal required by the CPU. Additionally, the clock generator performs a further divide-by-two output called PCLK (peripheral clock) which is the primary clock signal used by the remainder of the circuits.
The clock generator/driver provides two control signal outputs which are synchronized (internally) to the 2 MHz CLK signal; RDY (ready) and RST (reset). RST is used to reset the Nvis 5586A to an initialized state that occurs when the RES input goes low (when power first is applied or when the SYSTEM RESET key is pressed). The RDY output is active (logically high) when the RDY 1 input from the wait state generator is active. As will be explained in the next section, the RDY 1 input is active whenever onboard memory is addressed or when a selected number of ―wait states‖ occurs.
The system can operate at either 2 MHz or 1 MHz. This is selected by a set of jumpers JP3 on the right hand side of the 8284 clock generator as shown below:
1. 2 MHz (UPPER) 2. CLK
3. 1 MHz (LOWER)
The Nvis 5586A is supplied in 2 MHz configuration. Bus Controller:
The 8288 is a Bus Controller which decodes status signals output by an 8089, or a maximum mode 8086. When these signals indicate that the processor is to run a bus cycle, the 8288 issues a bus command that identifies the bus cycle as memory read, memory write, I/O read, I/O write, etc. It also provides a signal that strobes the address into latches. The 8288 provides the drive level needed for the bus control lines in medium to large systems.
Memory:
Nvis 5586A provides 128K Bytes of EPROM loaded with monitor and 32K bytes of CMOS RAM. The total onboard memory can be configured as follows:
EPROM - 128K Bytes of EPROM using two 27C512. RAM - 32K Bytes of RAM.
The system provides two 28 Pin sockets for the EPROM area named as EVEN-ROM & ODD-ROM and two 28 Pin sockets for the RAM area named as EVEN-RAM & ODD-RAM. EVEN-ROM & ODD-ROM can be defined to have EPROM 27512.
With the 20 bit address of 8086, a total of 1 Mega Bytes of memory can be addressed with the address slot as 00000 to FFFFF. Although the total onboard memory capacity is 180K Bytes 128K Bytes of EPROM and 32K Bytes of RAM.
8255:
8255 is a programmable peripheral interface (PPI) designed to use with 8086 Microprocessor. This basically acts as a general purpose I/O component to interface
peripheral equipments to the system bus. It is not necessary to have an external logic interface with peripheral devices since the functional configuration of 8255 is programmed by the system software. It has got three input/output ports of 8 lines each (A, PORT-B and PORT-C). Port-C can be divided into two ports of 4 lines each named as Port-C upper and C lower. Any Input/Output combination of A, B, C upper and Port-C lower can be defined using the appropriate software commands. The Port addresses for these ports are given here. Nvis 5586A provides nine Input/Output ports of 8 lines each using three 8255 chips. These ports are brought out at connectors.
8253:
This chip is a programmable interval timer/counter and can be used for the generation of accurate time delays under software control. Various other functions that can be implemented with this chip are programmable rate generator. Event Counter, Binary rate multiplier, real time clock etc. This chip has got three independent 16 bit counters each having a count rate of up to 2 MHz. The CLK, GATE & OUT signals of these timers are brought out at the connector.
8251:
This chip is a programmable communication interface and is used as a peripheral device. This device accepts data characters from the CPU in parallel form and then converts them into a continuous serial data stream for transmission. Simultaneously it can receive serial data stream and converts them into parallel data characters for the CPU. This chip will signal the CPU whenever it can accept a new character for transmission or whenever it has received a character for the CPU. The CPU can read the complete status of it at any time. 8251 has been utilized in Nvis 5586A for RS-232-C serial interface.
8259:
The 8259 is a device specifically designed for use in real time, interrupt driven microcomputer systems. It manages eight levels of requests and has built in features for expandability to other 8259‘s. It is programmed by system‘s software as an I/O peripheral. A selection of priority modes in which the requests are processed by 8259 can be configured to match his system requirements. The priority modes can be changed or reconfigured dynamically at any time during the main program.
Battery Backup:
The Nvis 5586A provides a battery backup for the onboard RAM area using 3.6V Ni-Cd Rechargeable battery. Nvis 5586A has facility for connecting +5V to the RAM area if the Ni-Cd battery fails. The selection for +5V or Battery supply Jumper (JP2).
Display:
This display contains 2 lines and each line consists of 20 words (20x2). This is a cursor LCD display modular. The CPU receives each 8 bits letter which is locked into the internal display data of RAM (data display of RAM 80 bytes (D.D.RAM) allows 80 characters to be stored), and transfer to 5x7 dot of array word and appear on the displayed.
This LCD modular contains the word generator ROM that will supply 160 different 5x7 dot of array word and also a 64 bytes word generator RAM. Users can define 8 types 5x7 dot of array word.
The position of word display goes into the LCD Modular through the data bus in CPU. Next through the instruction register and finally write the words into the data register to display on a specific location. The LCD Modular will automatically increase or decrease the words in order to move to different addresses. The user can therefore continue sending in word code. The cursor as to moved around or moved in the right of left direction.
Specification of Display :
Display data RAM : 80 x 8 BLT (80 words) Character generator ROM : 160 of 5x7 dot of array word
Character generator RAM : 8 different users programmed 5x7 dot of array
Kinds of instructions : Clear the display, send cursor home (HOME), ON/OFF display. Cursor ON/OFF, character blinking cursor move to another position, display change position. When the internal power is on, the circuit is reset.
Functional Block Diagram
Note: Some models incorporate a temperature compensation circuit within the bias voltage generator.
The LCD0. modular has 2, 8-bits register-one instruction register (IR) and one data register (DR).
The instruction register stores the instruction code and address information, which contains display data RAM and address of character generator RAM. However, the content of IR is only for read-in but not read-out.
The data register can only temporary store data, the input data first goes through LCD and is stored in the data register. It will then automatically be transferred to display data RAM or character generator RAM. When the CPU read the data from the displayed RAM or from the
character generator RAM, it wills also temporary store the data in the data register. When the address information is input into the instruction register, the relative data will be moved from display register RAM or character generator RAM to the data register. Then the data can be read from data register by using the output instruction of CPU.
One way to select the two registers is to select the register signal (RS) like follow: RS R/W Function
0 0 Data Bus —> instruction Register
0 1 Read out busy flags (BUSY FLAG DB7) and address counter (DB0-DB6)
1 0
Input into data register and execute the inner instruction: (D.R.RAM— > D.R.
OR C.G.RAM — D.R.)
1 1
Get the data out from register, and execute the inner instruction: (D.D.RAM—> D.R.
OR C.G.RAM—> D.R.) Busy Flag (B.F.):
When busy flag is ―1‖, it indicates that the LCD Modular is executing the inner instruction and no other instruction can be accepted. The LCD Modular can only accept information when BF is lower to ―0‖.
Address Counter (A.C.):
The address counter is used to count the display data RAM, or address of character generator RAM. When the address setting instruction address will be sent into the address counter. When the data is sent into or read out from display register RAM or from the character generator RAM, the address counter will automatically add or subtract 1.
When the content of address counter is in RS = 0 and R/W = 1, the output data line is DB0 DB6.
Display Data RAM (D.D. RAM):
This is an 80x8 bit RAM, which can store 80 8-bit character codes as the display data; it can be sent to CPU as the RAM data section without going through RAM section.
Address setting of data display RAM is as followed:
High level bus Low level bus AC6 AC5
AC4
AC3 AC2 AC1 AC0 Data displays RAM and display position of LCD is as followed: Character Position: 1 2 3 4 5 6 7 8 9 10 11…19 20
(Decimal)
First Line: 00 01 02 03 04 05 06 07 08 09 0A..16 17 (Hexadecimal)
Second Line: 40 41 42 43 44 45 46 47 48 49 4A...56 57 (Hexadecimal)
Character Generator ROM (C.G. ROM):
This ROM generates 5x7 dot of array character has 160 different 8-bit character code. The shape and code are shown in Table 2 and 3.
Character Generator RAM (C.G.RAM):
This RAM stores 8 different 5x7 dot of array character which allows the user to design the program. When the character codes are stored in the C.G.RAM, which are the same as the characters in Table 2 and 3, they will be sent to display data RAM. The display data and characters are shown in Table 4.
Timing Generator:
Character Codes:
Note:
1. The CG RAM generates character patterns in accordance with the user‘s program. 2. Shaded areas indicate 5x10 dot character patterns.
Character code:
Note :
1. The CG RAM generates character patterns in accordance with the user‘s program. 2. Shaded areas indicate 5x10 dot character patterns.
Relationship among Character Code:
(DD RAM), CG RAM Address, And Character Pattern (CG RAM) Character Pattern for 5x7
* Signifies a ―don‘t care‖ bit. Note:
1. Character code bits 0-2 correspond to CG RAM address bits 3-5. Each of the 8 unique bit strings designated one of the 8 character patterns.
2. A CG RAM address bit 0-2 designates the row position of each character pattern. The 8 the row is the cursor position. CG RAM data in the 8 the row is OR‘ed with the
display cursor. Any ―1‖ bits in the 8 the row will result in the displayed dot regardless of the cursor status (ON/OFF). Accordingly, if the cursor is to be used, CG RAM data for the 8 the row should be set to ―0‖.
3. CG RAM data bits 0-4 correspond to the column position of each character pattern bit 4 corresponding to the leftmost column of the character pattern CG RAM data bus are not used for displaying character patterns, but may be used as a general.
4. As shown in tables 2 and 3, character patterns in the CG RAM are accessed by character codes with bits 4-7 equal to ―0‖. For example, the character code ―00‖ (HEX) or ―80‖ (HEX), since bit 3 of the character code is a don‘t care bit (i.e. can take either value ―0‖ or ―1‖).
5. CG RAM data ―1‖ produces a dark dot, and data ―0‖ produces a light dot in the corresponding position on the display panel.
Functions of Reset:
Using the Internal Reset Circuit to Start:
LCD Modular internal has an automatic power supply to be used to RESET when the power rises. During RESET, the busy flag is set. When the voltage is raised to 4.5V in about 10ms, it is in the busy stage. The following instructions are then used to set the beginning stage of LCD.
1. Clear display 2. Function set
DL = 1 8-bit data length interface N = 0 (single line display)
F = 0 The source of 5x7 dot of array character 3. Display ON/OFF control
D = 1 Display OFF C = 0 Cursor OFF
B = 0 Character flashing function OFF 4. Entry mode set
I/D = 1 Increase mode S = 0 Display OFF
Note : If the time for the power to increases from 0.2V to 4.5V is greater than 0.1ms but less than 10ms, the current cut-off will drop to 0.2V before it rises again. If it takes more than 1ms, the LCD modular will automatically RESET. Otherwise, it has to depend on an external software instruction to RESET (As describe below).
Diagram of module RESET power. Instruction Set:
1. Symbol ―*‖ signifies a ―don‘t care‖ bit
2. Correct input value for ―N‖ is predetermined for each model Initialization by Instructions:
If the power conditions for the normal operation of the internal reset circuit are not satisfied. LCD unit must be initialized by executing a sense of the instructions. The procedure fro this initialization process is as follows.
When the LCD is controlled by the CPU, only the instruction register (IR) and the data register (DR) can be read directly by the CPU. The commands from outside the modular can decide the internal operation of LCD. These commands include the register selection (RS) signals, read/write (R/W) signals, and data buffering signals (DB0-DB6).
Table 5 lists all the useful commands in the LCD modular and the execution time, these commands are divided into the following group:
1. Commands of set LCD module
2. Commands of internal set address RAM
3. Commands of data transfer in or out from the internal RAM 4. Other commands
When the LCD modular is executing a command it will reject other commands. Except the ―busy flag/read address counter, the internal counting period of busy flag is set to as ―1‖. If the CPU wants to send in other commands it will have to check the busy flag first, until it is cleared to ―0‖ before it send in. The explanation is as followed:
Display Clear command:
This command will put the display data into a empty space‖ code (20H), address counter will be cleared to 0. When executing this command, display OFF, the cursor or the character blinking function will be moved to the most left side if it is in the set condition.
Display/Cursor Home:
The address counter will be cleared to 0, content of D.D. RAM will not be influenced; but if the cursor or the character blinking function is in the set condition, it will be moved to the most left side position.
Entry Mode Set:
I/D bit = ―1‖, ―1‖ is added in the address counter after each time it read/write a display data RAM character code, so that the cursor or the character blinking function will move one place to the left and vice-versa when I/D=0. The read/write (R/W) character generator also has the same function.
S bit = 1, but each time it read/write a display data RAM code, it will move to the display direction and move one space to the left (I/D=0) or one space to the right (I/D=1). When S=0, the display will not move.
When data enters the character generator RAM, the display will not move. Display ON/OFF:
D: D=1 - Display ON D=0 - Display OFF
C: C=1 - Cursor display on the display address of the display counter C=0 - Cursor does not display
B: B=1 - Character blinking of cursor position at feq or fosc=250kHz freq, therefore all black points and character display will exchange with each other. Each character display and overshadow 409.6ms.
Display/Cursor Shift: S/C R/L
0 0 - Cursor move to the left (AC AC-1) 0 0 - Cursor move to the right (AC AC+1) 1 0 - All the characters and cursor move to the left 1 1 - All the characters and cursor move to the right Note:
When the display moves, the address counter will not move. Function Set:
DL : Select data length for the interface circuit. DL=1 - Using the 8 bits data length.
DL=0 - Using the 4 bits data length.
N : Select the display format (one or two lines) C.G. RAM Address Set:
Address counter and character generator RAM have address which is driven by the binary 6-bit. When this instruction is driven in, data can be sent into the CPU and character generator -RAM.
D.D. RAM Address Set:
Address counter and display data RAM have addresses which are driven by the binary 7-bit. When this instruction is driven in, data can be sent into the CPU and the display data RAM. When N=0 (a single line display), binary code ADD between 00H and 4FH; when N=1 (a two lines display), the binary code ADD from 00H until 27H as the first line of from 40H until 67H as the second line.
Read Busy Flag/Address Counter:
The busy flag (BF) in LCD can be read from the CPU, using the instruction of LCD modular is the execution of the internal instruction BF = 1 represents the busy stage (execution of the internal instruction), it will not accept any instruction at this time until BF = 0.
Content of address counter and the busy flag will be read out at the same time, it is a 7-bit binary, the address counter will instruct one of the addresses, either the character generator RAM or display data RAM. This is determined by the final input address set instruction. Send Data Into C.G. RAM/D.D. RAM:
