Embedded Computer Architectures: Associative Processing

(1)

5-10-20064/4 Jan Jacobs, Océ Technologies BV, 02/10/06 1

Embedded Computer

Architectures:

Associative Processing

Jan Jacobs

Océ Technologies BV

Monday, October 2, 2006

10:40 Part I: Concept, Hardware

11:40 Part II: Applications

(2)

Part I: Associative Processing

(3)

5-10-2006 Jan Jacobs, Océ Technologies BV, 02/10/06 3

Overview

n

intro Océ, vision, problem

n

associative processing:

- concepts

- design considerations

- chips

(4)

(5)

(6)

(7)

5-10-2006 Jan Jacobs, Océ Technologies BV, 02/10/06 7 Office scan print copy publishing / navigation publishing / navigation

rational and story writing rational and story

writing security / integrity security / integrity corporate intelligence server corporate intelligence server extracting / information fusion building building scan _print

Affordable

hi-Q Services

by Sharing

(8)

Problems

n

Need for Speed!

n

Large Development effort?

… and answers

n

HW: Embedded massively // SIMD

(9)

associative

processing

(10)

HW: Embedded massive // SIMD

n

Flynn’s classification

n

SIMD concept

(11)

(12)

(13)

Properties

n

Address by content (not address)

n

“Instantaneous” association

n

SIMD

n

Ultra RISC (2 instructions: Compare, Write)

Associative Processing

History

n

Vannevar Bush [1945]: Memex

n

Slade and McMahon [1957]: "catalog" memory

(14)

Search

FF FF 00 00 00 00 00 J O * * * * * pattern mask J P J F J O E O R A 0 6 8 0 5 N E H D H T S E N 9 5 3 1 2 0 0 0 0 0 tag array PE0

(15)

5-10-2006 Jan Jacobs, Océ Technologies BV, 02/10/06 15 FF FF 00 00 00 00 00 J O * * * * * pattern mask array J P J F J O E O R A 0 6 8 0 5 N E H D H T S E N 9 5 3 1 2 0 0 0 0 0 tag 1 0 1 0 0 J O J O

Compare

Found...

PE0

(16)

…and write!

FF FF 00 00 FF 00 00 * * * * 0 0 0 0 6 0 0 5 0 5 0 1 2 0 0 0 0 0 1 0 1 0 0 J P J F J O E O R A N E H D H T S E N pattern mask

Write

PE0

(17)

1 2 1

2 4 2

1 2 1

16 x kernel

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

image

Smooth, 3x3 kernel (1)

(18)

Smooth, 3x3 kernel (2)

1 2 1 2 4 2 1 2 1 scanline a e c d b shift(1) a e c d b plus d+e b+c c+d a+b shift(-1) d+e b+c c+d a+b b+2c+d c+2d+e a+2b+c horizontal intermediate plus ==

(19)

Operations which benefit...

n

searching

n

max/min

n

zoom (reduction/enlargement)

n

rotate (multiple deskews)

n

trig functions (Cordic)

n

DFT

n

compression

n

…

Operations which don’t benefit...

n

Inherent sequential problems (e.g. Huffman

decoding, error diffusion)

n

Control intensive (e.g. floating point)

(20)

Just remember…

Von Neumann (1 data item per cycle)

SIMD Associative (1 bit per cycle) +1

N

W W << N

(21)

associative

processing

design

(22)

Implementing the concepts

row select c o lu m n s e le c t Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop mask register pattern register = = = = = = ta g ( s h if t) r e g is te r

Basics

(23)

Addition (1): LUT approach [4 cycles/bit]

*

0110

1 0111

0 *

*

0100

1 1100

0 *

*

1010

1 0111

0 *

*

0111

1 1111

0

1 1100

1 0101

1

0

0 1010

0 1000

0 Result

Carry

A B

1 1

Pattern Reg.

Mask Reg.

1 0

Reg.

1

0

0 Input/

Output

Buffer

Video

Memory

(24)

Addition (2): LUT approach [4 cycles/bit]

1

0 0110

1 0111

0

1

0 0100

1 1100

0

1

0 1010

1 0111

0

1

0 0111

1 1111

0

1 1100

1 0101

1

0

0 1010

0 1000

0 Pattern Reg.

Mask Reg.

1 0

Reg.

1

0

0 Input/

Output

Buffer

Video

Memory

1 1

(25)

(26)

associative

processing

(27)

Aspex Semiconductor Ltd

n

Est. 1999, off spring Brunel university (UK)

n

Fabless semiconductor company

n

high-speed signal processing devices

n

markets: telecommunications, imaging and

networking

n

35 employees

n

2004: raised 10M$ public capital

n

Customers: broadcasting (Imagineer Systems),

medical (X), wireless communication (Philips),

machine vision (X)

(28)

(29)

AsproCore architecture

b0 db0 w0 b1 b2 b3 b4 b5 b6 b7 db1 db2 db3 db4 db5 db6 db7 w1 … Ext [191..64] CAM [63..0] ab PDS [63..0] [0..7] sy n c as y n c serial Bit Mask Logic

X ALU ALU ALU ALU 4K X

RLinkPort

0 ALU ALU ALU ALU 15 1

LLinkPort

D64 D32 D32 D16 D8 D16 D16 D16 D8D8 D8 D8D8D8D8 Bit Mask b0 db0 w0 b1 b2 b3 b4 b5 b6 b7 db2 db4 db6 w1 S c a la r O u tp u t S c a la r In p u t